IT1021424B - Circuito regolatore di fase digitale - Google Patents
Circuito regolatore di fase digitaleInfo
- Publication number
- IT1021424B IT1021424B IT27341/74A IT2734174A IT1021424B IT 1021424 B IT1021424 B IT 1021424B IT 27341/74 A IT27341/74 A IT 27341/74A IT 2734174 A IT2734174 A IT 2734174A IT 1021424 B IT1021424 B IT 1021424B
- Authority
- IT
- Italy
- Prior art keywords
- regulator circuit
- digital phase
- phase regulator
- digital
- circuit
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/14—Digital recording or reproducing using self-clocking codes
- G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
- G11B20/1407—Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol
- G11B20/1419—Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol to or from biphase level coding, i.e. to or from codes where a one is coded as a transition from a high to a low level during the middle of a bit cell and a zero is encoded as a transition from a low to a high level during the middle of a bit cell or vice versa, e.g. split phase code, Manchester code conversion to or from biphase space or mark coding, i.e. to or from codes where there is a transition at the beginning of every bit cell and a one has no second transition and a zero has a second transition one half of a bit period later or vice versa, e.g. double frequency code, FM code
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Computer Networks & Wireless Communication (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19732346934 DE2346934A1 (de) | 1973-09-18 | 1973-09-18 | Digitaler phasenregelkreis |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| IT1021424B true IT1021424B (it) | 1978-01-30 |
Family
ID=5892944
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| IT27341/74A IT1021424B (it) | 1973-09-18 | 1974-09-17 | Circuito regolatore di fase digitale |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US3893170A (fr) |
| BE (1) | BE820065A (fr) |
| DE (1) | DE2346934A1 (fr) |
| FR (1) | FR2244305B3 (fr) |
| IT (1) | IT1021424B (fr) |
| NL (1) | NL7412357A (fr) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2365178A1 (fr) * | 1976-09-20 | 1978-04-14 | Cii Honeywell Bull | Procede de lecture d'adresses sur un support d'enregistrement magnetique et dispositif pour le mettre en oeuvre |
| US4158436A (en) * | 1977-07-25 | 1979-06-19 | Amp Incorporated | Variable timing circuit for card readers and the like |
| JPS5813046A (ja) * | 1981-07-17 | 1983-01-25 | Victor Co Of Japan Ltd | デ−タ読み取り回路 |
| DE3322623A1 (de) * | 1983-06-23 | 1985-01-03 | Siemens AG, 1000 Berlin und 8000 München | Schaltungsanordnung zum wiedergewinnen von in binaeren datensignalen enthaltenden daten |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3631424A (en) * | 1969-07-22 | 1971-12-28 | Honeywell Inc | Binary data detecting apparatus responsive to the change in sign of the slope of a waveform |
| BE790688A (fr) * | 1971-10-27 | 1973-04-27 | Xerox Corp | Dispositif pour reproduire des bits de donnees enregistrees surun milieu d'enregistrement magnetique |
| US3736582A (en) * | 1972-03-20 | 1973-05-29 | Leach Corp | Galloping base line compensating circuit |
| US3795903A (en) * | 1972-09-29 | 1974-03-05 | Ibm | Modified phase encoding |
-
1973
- 1973-09-18 DE DE19732346934 patent/DE2346934A1/de active Pending
-
1974
- 1974-09-03 US US502510A patent/US3893170A/en not_active Expired - Lifetime
- 1974-09-12 FR FR7430845A patent/FR2244305B3/fr not_active Expired
- 1974-09-17 IT IT27341/74A patent/IT1021424B/it active
- 1974-09-18 BE BE148659A patent/BE820065A/fr unknown
- 1974-09-18 NL NL7412357A patent/NL7412357A/xx unknown
Also Published As
| Publication number | Publication date |
|---|---|
| US3893170A (en) | 1975-07-01 |
| FR2244305A1 (fr) | 1975-04-11 |
| NL7412357A (nl) | 1975-03-20 |
| DE2346934A1 (de) | 1975-04-03 |
| BE820065A (fr) | 1975-03-18 |
| FR2244305B3 (fr) | 1977-06-17 |
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