IN2014KN02632A - - Google Patents

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Publication number
IN2014KN02632A
IN2014KN02632A IN2632KON2014A IN2014KN02632A IN 2014KN02632 A IN2014KN02632 A IN 2014KN02632A IN 2632KON2014 A IN2632KON2014 A IN 2632KON2014A IN 2014KN02632 A IN2014KN02632 A IN 2014KN02632A
Authority
IN
India
Prior art keywords
erasing
memory cells
programming
cycle including
steps
Prior art date
Application number
Inventor
Marc Merandat
Original Assignee
Inside Secure
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Inside Secure filed Critical Inside Secure
Publication of IN2014KN02632A publication Critical patent/IN2014KN02632A/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/22—Safety or protection circuits preventing unauthorised or accidental access to memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/344—Arrangements for verifying correct erasure or for detecting overerased cells
    • G11C16/3445—Circuits or methods to verify correct erasure of nonvolatile memory cells

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Read Only Memory (AREA)
  • Storage Device Security (AREA)

Abstract

The present invention relates to a method for programming or erasing memory cells of a nonvolatile memory, including a first erasing or programming cycle including the steps involving i) applying (S11) at least one erasing or programming pulse (Np) to the first memory cells, ii) determining (S14) the state, erased or programmed, of the memory cells, and repeating the steps i) and ii) if the memory cells are not in the desired state, and a second erasing or programming cycle including the application of a predetermined number of erasing or programming pulses to the second memory cells.
IN2632KON2014 2012-07-09 2013-06-28 IN2014KN02632A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1201940A FR2993089B1 (en) 2012-07-09 2012-07-09 METHOD OF ERASING OR PROGRAMMING A FACTICE MEMORY PROTECTED AGAINST DETECTION
PCT/FR2013/051519 WO2014009627A1 (en) 2012-07-09 2013-06-28 Dummy memory erasing or programming method having protection against detection

Publications (1)

Publication Number Publication Date
IN2014KN02632A true IN2014KN02632A (en) 2015-05-08

Family

ID=48914335

Family Applications (1)

Application Number Title Priority Date Filing Date
IN2632KON2014 IN2014KN02632A (en) 2012-07-09 2013-06-28

Country Status (8)

Country Link
US (1) US9478294B2 (en)
EP (1) EP2870605B1 (en)
JP (1) JP2015525942A (en)
KR (1) KR20150030257A (en)
CN (1) CN104428838A (en)
FR (1) FR2993089B1 (en)
IN (1) IN2014KN02632A (en)
WO (1) WO2014009627A1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3039921B1 (en) * 2015-08-06 2018-02-16 Stmicroelectronics (Rousset) Sas METHOD AND SYSTEM FOR CONTROLLING A DATA WRITE OPERATION IN A MEMORY CELL OF THE EEPROM TYPE
KR102435026B1 (en) * 2015-12-15 2022-08-22 삼성전자주식회사 Method of operating storage device
US10777271B2 (en) * 2017-09-29 2020-09-15 Intel Corporation Method and apparatus for adjusting demarcation voltages based on cycle count metrics

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1186575A (en) * 1997-09-05 1999-03-30 Oki Electric Ind Co Ltd Non-volatile semiconductor memory
FR2790347B1 (en) * 1999-02-25 2001-10-05 St Microelectronics Sa METHOD FOR SECURING A CHAIN OF OPERATIONS CARRIED OUT BY AN ELECTRONIC CIRCUIT IN THE CONTEXT OF THE EXECUTION OF AN ALGORITHM
WO2001061503A1 (en) * 2000-02-16 2001-08-23 Fujitsu Limited Nonvolatile memory
JP2002230982A (en) * 2001-02-01 2002-08-16 Mitsubishi Electric Corp Non-volatile semiconductor memory
US7292473B2 (en) * 2005-09-07 2007-11-06 Freescale Semiconductor, Inc. Method and apparatus for programming/erasing a non-volatile memory
KR100830584B1 (en) * 2006-11-21 2008-05-21 삼성전자주식회사 Flash memory device and smart card including the same
US7983078B2 (en) 2008-09-24 2011-07-19 Sandisk Technologies Inc. Data retention of last word line of non-volatile memory arrays
JP5542737B2 (en) * 2011-05-12 2014-07-09 株式会社東芝 Nonvolatile semiconductor memory device

Also Published As

Publication number Publication date
EP2870605B1 (en) 2016-07-20
US9478294B2 (en) 2016-10-25
US20150124532A1 (en) 2015-05-07
KR20150030257A (en) 2015-03-19
JP2015525942A (en) 2015-09-07
FR2993089A1 (en) 2014-01-10
WO2014009627A1 (en) 2014-01-16
EP2870605A1 (en) 2015-05-13
CN104428838A (en) 2015-03-18
FR2993089B1 (en) 2014-07-18

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