IN2014DN08648A - - Google Patents

Info

Publication number
IN2014DN08648A
IN2014DN08648A IN8648DEN2014A IN2014DN08648A IN 2014DN08648 A IN2014DN08648 A IN 2014DN08648A IN 8648DEN2014 A IN8648DEN2014 A IN 8648DEN2014A IN 2014DN08648 A IN2014DN08648 A IN 2014DN08648A
Authority
IN
India
Prior art keywords
cache
cache memory
memory
subsystem
shutdown
Prior art date
Application number
Other languages
English (en)
Inventor
Srilatha Manne
William L Bircher
Madhu Sarvana Sibi Govindan
James M Oconnor
Michael J Schulte
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of IN2014DN08648A publication Critical patent/IN2014DN08648A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0888—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G06F2212/1024—Latency reduction
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
IN8648DEN2014 2012-03-30 2013-04-01 IN2014DN08648A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/435,539 US20130262780A1 (en) 2012-03-30 2012-03-30 Apparatus and Method for Fast Cache Shutdown
PCT/US2013/034847 WO2013149254A1 (en) 2012-03-30 2013-04-01 Apparatus and method for fast cache shutdown

Publications (1)

Publication Number Publication Date
IN2014DN08648A true IN2014DN08648A (zh) 2015-05-22

Family

ID=48143370

Family Applications (1)

Application Number Title Priority Date Filing Date
IN8648DEN2014 IN2014DN08648A (zh) 2012-03-30 2013-04-01

Country Status (7)

Country Link
US (1) US20130262780A1 (zh)
EP (1) EP2831744A1 (zh)
JP (1) JP2015515687A (zh)
KR (1) KR20140139610A (zh)
CN (1) CN104272277A (zh)
IN (1) IN2014DN08648A (zh)
WO (1) WO2013149254A1 (zh)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140108734A1 (en) * 2012-10-17 2014-04-17 Advanced Micro Devices, Inc. Method and apparatus for saving processor architectural state in cache hierarchy
US9541984B2 (en) * 2013-06-05 2017-01-10 Apple Inc. L2 flush and memory fabric teardown
KR20170023813A (ko) * 2014-06-20 2017-03-06 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
US11169925B2 (en) * 2015-08-25 2021-11-09 Samsung Electronics Co., Ltd. Capturing temporal store streams into CPU caches by dynamically varying store streaming thresholds
US9946646B2 (en) * 2016-09-06 2018-04-17 Advanced Micro Devices, Inc. Systems and method for delayed cache utilization
DE102017124805B4 (de) * 2017-10-24 2019-05-29 Infineon Technologies Ag Speicheranordnung und verfahren zum zwischenspeichern von speicherinhalten
US20200388319A1 (en) 2019-06-07 2020-12-10 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, electronic component, and electronic device
US11436251B2 (en) * 2020-10-02 2022-09-06 EMC IP Holding Company LLC Data size based replication

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0325422B1 (en) * 1988-01-20 1996-05-15 Advanced Micro Devices, Inc. Integrated cache unit
US5664149A (en) * 1992-11-13 1997-09-02 Cyrix Corporation Coherency for write-back cache in a system designed for write-through cache using an export/invalidate protocol
JP3136036B2 (ja) * 1993-11-16 2001-02-19 富士通株式会社 ディスク制御装置の制御方法
US6052789A (en) * 1994-03-02 2000-04-18 Packard Bell Nec, Inc. Power management architecture for a reconfigurable write-back cache
US5761705A (en) * 1996-04-04 1998-06-02 Symbios, Inc. Methods and structure for maintaining cache consistency in a RAID controller having redundant caches
US6338119B1 (en) * 1999-03-31 2002-01-08 International Business Machines Corporation Method and apparatus with page buffer and I/O page kill definition for improved DMA and L1/L2 cache performance
US6711691B1 (en) * 1999-05-13 2004-03-23 Apple Computer, Inc. Power management for computer systems
US20020138778A1 (en) * 2001-03-22 2002-09-26 Cole James R. Controlling CPU core voltage to reduce power consumption
US7231497B2 (en) * 2004-06-15 2007-06-12 Intel Corporation Merging write-back and write-through cache policies
US7496770B2 (en) * 2005-09-30 2009-02-24 Broadcom Corporation Power-efficient technique for invoking a co-processor
US7562191B2 (en) * 2005-11-15 2009-07-14 Mips Technologies, Inc. Microprocessor having a power-saving instruction cache way predictor and instruction replacement scheme
US7257507B1 (en) * 2006-01-31 2007-08-14 Credence Systems Corporation System and method for determining probing locations on IC
US8285936B2 (en) * 2009-10-20 2012-10-09 The Regents Of The University Of Michigan Cache memory with power saving state
EP2330753A1 (en) * 2009-12-04 2011-06-08 Gemalto SA Method of power negotiation between two contactless devices
JP5445326B2 (ja) * 2010-05-19 2014-03-19 株式会社リコー 画像形成装置

Also Published As

Publication number Publication date
US20130262780A1 (en) 2013-10-03
JP2015515687A (ja) 2015-05-28
KR20140139610A (ko) 2014-12-05
WO2013149254A1 (en) 2013-10-03
CN104272277A (zh) 2015-01-07
EP2831744A1 (en) 2015-02-04

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