IN2014CN03703A - - Google Patents
Info
- Publication number
- IN2014CN03703A IN2014CN03703A IN3703CHN2014A IN2014CN03703A IN 2014CN03703 A IN2014CN03703 A IN 2014CN03703A IN 3703CHN2014 A IN3703CHN2014 A IN 3703CHN2014A IN 2014CN03703 A IN2014CN03703 A IN 2014CN03703A
- Authority
- IN
- India
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/3017—Runtime instruction translation, e.g. macros
- G06F9/30174—Runtime instruction translation, e.g. macros for non-native instruction set, e.g. Javabyte, legacy code
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3802—Instruction prefetching
- G06F9/3808—Instruction prefetching for instruction reuse, e.g. trace cache, branch target cache
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3824—Operand accessing
- G06F9/3834—Maintaining memory consistency
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
- G06F9/384—Register renaming
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
- G06F9/3856—Reordering of instructions, e.g. using queues or age tags
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
- G06F9/3887—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple data lanes [SIMD]
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Advance Control (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/US2011/061940 WO2013077872A1 (en) | 2011-11-22 | 2011-11-22 | A microprocessor accelerated code optimizer and dependency reordering method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| IN2014CN03703A true IN2014CN03703A (en) | 2015-10-09 |
Family
ID=48470170
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| IN3703CHN2014 IN2014CN03703A (en) | 2011-11-22 | 2014-05-16 |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US20140344554A1 (en) |
| EP (1) | EP2783282B1 (en) |
| KR (1) | KR101648278B1 (en) |
| CN (1) | CN104040492B (en) |
| IN (1) | IN2014CN03703A (en) |
| WO (1) | WO2013077872A1 (en) |
Families Citing this family (34)
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| WO2007143278A2 (en) | 2006-04-12 | 2007-12-13 | Soft Machines, Inc. | Apparatus and method for processing an instruction matrix specifying parallel and dependent operations |
| EP2122461A4 (en) | 2006-11-14 | 2010-03-24 | Soft Machines Inc | Apparatus and method for processing instructions in a multi-threaded architecture using context switching |
| EP2616928B1 (en) | 2010-09-17 | 2016-11-02 | Soft Machines, Inc. | Single cycle multi-branch prediction including shadow cache for early far branch prediction |
| WO2012135041A2 (en) | 2011-03-25 | 2012-10-04 | Soft Machines, Inc. | Register file segments for supporting code block execution by using virtual cores instantiated by partitionable engines |
| EP2689327B1 (en) | 2011-03-25 | 2021-07-28 | Intel Corporation | Executing instruction sequence code blocks by using virtual cores instantiated by partitionable engines |
| US9274793B2 (en) | 2011-03-25 | 2016-03-01 | Soft Machines, Inc. | Memory fragments for supporting code block execution by using virtual cores instantiated by partitionable engines |
| KR101639853B1 (en) | 2011-05-20 | 2016-07-14 | 소프트 머신즈, 인크. | Decentralized allocation of resources and interconnect structures to support the execution of instruction sequences by a plurality of engines |
| TWI548994B (en) | 2011-05-20 | 2016-09-11 | 軟體機器公司 | An interconnect structure to support the execution of instruction sequences by a plurality of engines |
| KR101842550B1 (en) | 2011-11-22 | 2018-03-28 | 소프트 머신즈, 인크. | An accelerated code optimizer for a multiengine microprocessor |
| EP2783281B1 (en) | 2011-11-22 | 2020-05-13 | Intel Corporation | A microprocessor accelerated code optimizer |
| US9891924B2 (en) | 2013-03-15 | 2018-02-13 | Intel Corporation | Method for implementing a reduced size register view data structure in a microprocessor |
| EP2972845B1 (en) | 2013-03-15 | 2021-07-07 | Intel Corporation | A method for executing multithreaded instructions grouped onto blocks |
| WO2014150971A1 (en) | 2013-03-15 | 2014-09-25 | Soft Machines, Inc. | A method for dependency broadcasting through a block organized source view data structure |
| US10140138B2 (en) | 2013-03-15 | 2018-11-27 | Intel Corporation | Methods, systems and apparatus for supporting wide and efficient front-end operation with guest-architecture emulation |
| US9569216B2 (en) | 2013-03-15 | 2017-02-14 | Soft Machines, Inc. | Method for populating a source view data structure by using register template snapshots |
| WO2014150806A1 (en) | 2013-03-15 | 2014-09-25 | Soft Machines, Inc. | A method for populating register view data structure by using register template snapshots |
| US9811342B2 (en) | 2013-03-15 | 2017-11-07 | Intel Corporation | Method for performing dual dispatch of blocks and half blocks |
| US10275255B2 (en) | 2013-03-15 | 2019-04-30 | Intel Corporation | Method for dependency broadcasting through a source organized source view data structure |
| US9886279B2 (en) | 2013-03-15 | 2018-02-06 | Intel Corporation | Method for populating and instruction view data structure by using register template snapshots |
| CN105247484B (en) | 2013-03-15 | 2021-02-23 | 英特尔公司 | Method for emulating a guest centralized flag architecture using a locally distributed flag architecture |
| WO2014150991A1 (en) | 2013-03-15 | 2014-09-25 | Soft Machines, Inc. | A method for implementing a reduced size register view data structure in a microprocessor |
| US9904625B2 (en) | 2013-03-15 | 2018-02-27 | Intel Corporation | Methods, systems and apparatus for predicting the way of a set associative cache |
| US11281481B2 (en) | 2014-07-25 | 2022-03-22 | Intel Corporation | Using a plurality of conversion tables to implement an instruction set agnostic runtime architecture |
| US10353680B2 (en) * | 2014-07-25 | 2019-07-16 | Intel Corporation | System converter that implements a run ahead run time guest instruction conversion/decoding process and a prefetching process where guest code is pre-fetched from the target of guest branches in an instruction sequence |
| CN104699464B (en) * | 2015-03-26 | 2017-12-26 | 中国人民解放军国防科学技术大学 | A kind of instruction level parallelism dispatching method based on dependence grid |
| JP2017068534A (en) * | 2015-09-30 | 2017-04-06 | 富士通株式会社 | Analysis method, analysis device and analysis program |
| KR20180038793A (en) * | 2016-10-07 | 2018-04-17 | 삼성전자주식회사 | Method and apparatus for processing image data |
| CN107688544B (en) * | 2016-12-23 | 2020-02-11 | 北京国睿中数科技股份有限公司 | Method for recovering alias table of register |
| JP7403450B2 (en) * | 2017-11-30 | 2023-12-22 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Dependency matrix extensible with one or more summary bits in an out-of-order processor |
| US10884751B2 (en) | 2018-07-13 | 2021-01-05 | Advanced Micro Devices, Inc. | Method and apparatus for virtualizing the micro-op cache |
| CN109491667A (en) * | 2018-12-21 | 2019-03-19 | 芯海科技（深圳）股份有限公司 | A kind of method of C language compiling efficiency optimization |
| US11068272B2 (en) | 2019-09-20 | 2021-07-20 | Microsoft Technology Licensing, Llc | Tracking and communication of direct/indirect source dependencies of producer instructions executed in a processor to source dependent consumer instructions to facilitate processor optimizations |
| CN112579272B (en) * | 2020-12-07 | 2023-11-14 | 海光信息技术股份有限公司 | Micro instruction distribution method, micro instruction distribution device, processor and electronic equipment |
| US20240004657A1 (en) * | 2022-06-30 | 2024-01-04 | Advanced Micro Devices, Inc. | Encoded data dependency matrix for power efficiency scheduling |
Family Cites Families (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5710902A (en) * | 1995-09-06 | 1998-01-20 | Intel Corporation | Instruction dependency chain indentifier |
| US6016540A (en) * | 1997-01-08 | 2000-01-18 | Intel Corporation | Method and apparatus for scheduling instructions in waves |
| US6065105A (en) * | 1997-01-08 | 2000-05-16 | Intel Corporation | Dependency matrix |
| US6122656A (en) * | 1998-07-31 | 2000-09-19 | Advanced Micro Devices, Inc. | Processor configured to map logical register numbers to physical register numbers using virtual register numbers |
| US6728866B1 (en) * | 2000-08-31 | 2004-04-27 | International Business Machines Corporation | Partitioned issue queue and allocation strategy |
| US7363467B2 (en) * | 2002-01-03 | 2008-04-22 | Intel Corporation | Dependence-chain processing using trace descriptors having dependency descriptors |
| US6920530B2 (en) * | 2002-04-23 | 2005-07-19 | Sun Microsystems, Inc. | Scheme for reordering instructions via an instruction caching mechanism |
| KR101355496B1 (en) * | 2005-08-29 | 2014-01-28 | 디 인벤션 사이언스 펀드 원, 엘엘씨 | Scheduling mechanism of a hierarchical processor including multiple parallel clusters |
| WO2007143278A2 (en) | 2006-04-12 | 2007-12-13 | Soft Machines, Inc. | Apparatus and method for processing an instruction matrix specifying parallel and dependent operations |
| CN100495324C (en) * | 2006-07-27 | 2009-06-03 | 中国科学院计算技术研究所 | Deepness priority exception handling method in sophisticated vocabulary architecture |
| US20080189501A1 (en) * | 2007-02-05 | 2008-08-07 | Irish John D | Methods and Apparatus for Issuing Commands on a Bus |
| US8555039B2 (en) * | 2007-05-03 | 2013-10-08 | Qualcomm Incorporated | System and method for using a local condition code register for accelerating conditional instruction execution in a pipeline processor |
| US7711929B2 (en) * | 2007-08-30 | 2010-05-04 | International Business Machines Corporation | Method and system for tracking instruction dependency in an out-of-order processor |
| US9513905B2 (en) * | 2008-03-28 | 2016-12-06 | Intel Corporation | Vector instructions to enable efficient synchronization and parallel reduction operations |
| US8135942B2 (en) * | 2008-08-28 | 2012-03-13 | International Business Machines Corpration | System and method for double-issue instructions using a dependency matrix and a side issue queue |
| US7769984B2 (en) * | 2008-09-11 | 2010-08-03 | International Business Machines Corporation | Dual-issuance of microprocessor instructions using dual dependency matrices |
| US7848129B1 (en) * | 2008-11-20 | 2010-12-07 | Netlogic Microsystems, Inc. | Dynamically partitioned CAM array |
| CN101582025B (en) * | 2009-06-25 | 2011-05-25 | 浙江大学 | Implementation method of rename table of global register under on-chip multi-processor system framework |
-
2011
- 2011-11-22 US US14/360,280 patent/US20140344554A1/en not_active Abandoned
- 2011-11-22 KR KR1020147016774A patent/KR101648278B1/en active IP Right Grant
- 2011-11-22 WO PCT/US2011/061940 patent/WO2013077872A1/en active Application Filing
- 2011-11-22 CN CN201180076245.7A patent/CN104040492B/en active Active
- 2011-11-22 EP EP11876130.3A patent/EP2783282B1/en active Active
-
2014
- 2014-05-16 IN IN3703CHN2014 patent/IN2014CN03703A/en unknown
Also Published As
| Publication number | Publication date |
|---|---|
| WO2013077872A1 (en) | 2013-05-30 |
| EP2783282B1 (en) | 2020-06-24 |
| EP2783282A4 (en) | 2016-06-29 |
| CN104040492B (en) | 2017-02-15 |
| US20140344554A1 (en) | 2014-11-20 |
| KR20140094015A (en) | 2014-07-29 |
| KR101648278B1 (en) | 2016-08-12 |
| CN104040492A (en) | 2014-09-10 |
| EP2783282A1 (en) | 2014-10-01 |