CN100495324C - Deepness priority exception handling method in sophisticated vocabulary architecture - Google Patents
Deepness priority exception handling method in sophisticated vocabulary architecture Download PDFInfo
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- CN100495324C CN100495324C CNB2006100889393A CN200610088939A CN100495324C CN 100495324 C CN100495324 C CN 100495324C CN B2006100889393 A CNB2006100889393 A CN B2006100889393A CN 200610088939 A CN200610088939 A CN 200610088939A CN 100495324 C CN100495324 C CN 100495324C
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Abstract
The invention discloses a depth-first exception handling method in a complex instruction set architecture. The method includes the following steps: in abnormal times, 1) an instruction reordering buffer sends out anomaly information to each module which sets a register in the module to be invalid in order to brush a pipeline empty; 2) a decoding component transforms the anomaly information into a predefined instruction; 3) the decoding component indexes a read-only memory to find out a corresponding microinstruction and sends the microinstruction into an emission part according to the predefined instruction; 4) the emission part sends the microinstruction which is not correlative with data into an execution part to be conducted; 5) the execution part executes the microinstruction and writes the executing outcomes into the instruction reordering buffer; 6) whether a first microinstruction in the instruction reordering buffer is abnormal or not is checked; 7) if the first microinstruction in the instruction reordering buffer is abnormal, returning to the step one: brushing the pipeline empty; 8) if the first microinstruction in the instruction reordering buffer is normal, the instruction reordering buffer commits the first microinstruction which is written back and the processing is finished.
Description
Technical field
The present invention relates to field of computer, specifically, relate to processor internal abnormality process field.The present invention proposes the depth-first abnormality eliminating method in a kind of sophisticated vocabulary architecture.
Background technology
In the computer system of sophisticated vocabulary, most of instruction all is translated as many micro-orders, and what the instruction pipelining in the processor was handled is these micro-orders, rather than the instruction of the operating system visible before the translation.These micro-orders can be operated usually than the more register resources of complicated order, such as concentrating at complicated order 8 visible general-purpose registers are arranged, and may have the visible general-purpose register more than 32 or 64 in microinstruction set.With 32 visible general-purpose registers is example, and 8 general-purpose registers that can be used as sophisticated vocabulary wherein, 24 remaining registers then keep code translator to microinstruction set as temporary register or as other purposes.Certainly, for also there being the relevant problem of data between the visible general-purpose register of microinstruction set.This problem solves by register renaming usually.In many micro-orders that the instruction translation of a complexity becomes, some micro-orders can take place unusually under certain conditions, after taking place unusually, at first can carry out some pre-service micro-orders, pre-service micro-order save register scene, obtain the destination address of redirect, jump to the exception handler of operating system visible then.There is a problem in this mechanism, may take place again in the pre-service micro-order after taking place unusually so just to have formed the unusual multilayer nest of micro-order unusually.So just need a kind of method to guarantee the order that these are unusual, correct reparation.In addition, instruction for sophisticated vocabulary, they are translated as a plurality of micro-orders usually, each all might take place these a plurality of micro-orders unusually, unusually how these obtain handling, and don't, the present invention proposes and a kind ofly repairing the method that all these turn back to normal instruction execution flow after unusual as for causing the chaotic even unusual endless loop of instruction flow.
Summary of the invention
The invention provides a kind of method of depth-first abnormality processing, can solve in unusual preprocessing process unusual problem takes place again, and can guarantee the recovery of dependence between the register, and unusual normal reparation, thus can continue execution command from breakpoint.
To achieve these goals, according to the present invention, depth-first abnormality eliminating method in a kind of sophisticated vocabulary architecture has been proposed, may further comprise the steps: when generation is unusual, 1) the instruction resequencing buffer sends abnormal information and gives affected module, it is invalid that affected module is changed to self register, thereby brush empty streamline; 2) decoding unit is converted to predefined instruction with described abnormal information; 3) decoding unit is according to described predefined instruction, and the index ROM (read-only memory) is found out micro-order correspondingly, and described micro-order is sent into emission element; 4) emission element will not have the relevant micro-order of data to send into the execution unit execution; 5) execution unit is carried out described micro-order, and execution result is write the instruction resequencing buffer; 6) check whether article one micro-order in the instruction resequencing buffer is unusual; 7) if article one micro-order of instruction in the resequencing buffer is unusual, then returning 1) streamline brushes empty step; 8) if article one micro-order in the instruction resequencing buffer does not take place unusually, article one micro-order of then instructing resequencing buffer to have write back is submitted to, finishes processing.
Preferably, described 3) the micro-order finding step also comprises: described predefined instruction is decoded, and according to decoded result, the index ROM (read-only memory).
Preferably, described 3) the micro-order finding step also comprises: described micro-order is left in the instruction resequencing buffer according to the order of sequence.
Preferably, described execution unit comprises a plurality of performance elements.
Preferably, described 6) in the follow-up for anomaly step, check whether many forward micro-orders of ordering in the instruction resequencing buffer are unusual.
Preferably, many forward micro-orders of ordering are meant article one and second micro-order in the ream weight ordering impact damper in the instruction resequencing buffer.
Preferably, many forward micro-orders of ordering are meant four micro-orders of article one to the in the ream weight ordering impact damper in the instruction resequencing buffer.
Preferably,, wait for the generation of related data, when producing all related datas, the relevant micro-order of these data is labeled as the micro-order that does not have data relevant for the relevant micro-order of data.
Description of drawings
Below with reference to accompanying drawings, the preferred embodiments of the present invention are described in detail, wherein:
Fig. 1 shows the fundamental block diagram of using microprocessor of the present invention.
Fig. 2 is the unusual processing flow chart when nested of pre-service micro-order.
Fig. 3 is the cut-away view of ROQ, and it is a round-robin queue.
Fig. 4 is the implementation that unusual pretreated instruction when nested does not take place.
Fig. 5 is the implementation that unusual pretreated instruction when nested takes place.
Fig. 6 has described the target logic register of micro-order correspondence in the rename module and the dependence between the physical register.
Fig. 7 is a structured flowchart of realizing code translator of the present invention.
Embodiment
Below in conjunction with description of drawings the specific embodiment of the present invention.Be noted that described embodiment only is for illustrative purposes, rather than limitation of the scope of the invention.Described various numerical value is not to be used to limit the present invention, and these numerical value can carry out any suitable modification according to those of ordinary skills' needs.
Fig. 1 is based on a kind of CPU structured flowchart of the present invention.The execution process instruction of this class CPU is as follows: instruction fetching component 101 comprises order register, instruction cache (cache), instruction bypass impact damper, branch predictor etc., can different the work regulate accordingly with the complexity of the system of realization.Instruction fetching component 101 is responsible for taking out corresponding instruction and is given decoding unit 102 from instruction cache, decoding unit 102 obtains to instruct the back to get micro-order from ROM 103 and deciphers, micro-order after the decoding is delivered to emission element 104 and instruction resequencing buffer (ROQ) 106, emission element 104 contains rename logic or counter circuit etc., being used for eliminating writing between the register is correlated with relevant with read-write, the also responsible instruction that will be ready to data of emission element 104 sends to execution unit 105 and goes to carry out, execution unit 105 writes back to ROQ 106 with the object information of carrying out, the status information that contains every instruction in the streamline among the ROQ 106, for example, whether be finished, whether submit to etc.Also have states such as branch writes back, branch's triggering for branch instruction.
Shown in Fig. 2 be unusual pre-service micro-order generation multilayer nest the time CPU shown in Figure 1 the execution flow process.Take place unusual after, ROQ 106 output abnormality information (step S202) are given each module, it is invalid that each module is put self register, thereby brush empty streamline.Abnormal information is buffered in the impact damper in the decoding unit 102.This abnormal information is encoded as a predefined instruction (step S203) in decoding unit 102, in next bat this predefined instruction is decoded, produce a urom_pc and remove index ROM 103, and the micro-order that will obtain from ROM 103 is transmitted to emission element 104 (step S204), simultaneously in ROQ106, also can deposit corresponding micro-order according to the order of sequence, emission element 104 will not have the relevant micro-order of data to send into execution unit 105 execution (step S205), execution unit 105 can be more than one, decides with specific design.Micro-order needs 1 to clap or clap in execution unit 105 more, then the object information that produces is issued ROQ 106 (step S206), in step S207, ROQ 106 claps at each and checks a micro-order indexed registers Roq_head micro-order pointed, can check 4,2 or only check 1, decide with design.If this micro-order writes back, and not unusual the generation, then this instruction can be submitted (step S208) to, if trigger unusual once more, streamline is empty by brush again, code translator 102 cushions this abnormal information again, and send the abnormality processing micro-order once more, reappeared above-mentioned treatment scheme, so just formed a depth-first traversal, behind unusual processed the finishing of bottommost layer, the sort processor structure can trigger the unusual of time profound level, behind all unusually all processed finishing, complicated order can obtain carrying out.In addition,, wait for the generation of related data, when producing all related datas, the relevant micro-order of these data is labeled as the micro-order that does not have data relevant for the relevant micro-order of data.
Shown in Figure 3 is the structure of ROQ 106, and the micro-order among the ROQ 106 is deposited in order.A micro-order indexed registers Roq_head points to the instruction of ROQ 106 queue heads, and the micro-order pygochord draws the next item down that register Roq_tail points to rear of queue.ROQ 106 is be used for guaranteeing instructing precise abnormal, and the execution result that micro-orders all thereafter when unusual takes place when micro-order wherein all can be cancelled.After a micro-order among the ROQ 106 took place unusually, this unusual information can be issued instruction fetching component 101, decoding unit 102, emission element 104 etc.
Fig. 4 is that unusual pre-service is in the implementation that does not have complicated order under the nested situation, after a complicated order takes place unusually, at first arrange one section pre-service micro-order to carry out operations such as pop down, scope check, instruct by jump (far jump) far away at last, jump to the exception handler of complicated order.
Fig. 5 is in the implementation that unusual pretreated three layers of complicated order when nested take place, what as can be seen from the figure at first handle is the 3rd layer unusual, this the 3rd layer be to produce unusually by the unusual pre-service micro-order of the second layer, turn back to breakpoint and re-execute this instruction handling preprocessor, the result takes place unusually once more, at most only can trigger the unusual of the second layer this moment, the 3rd layer when triggering for the first time, be repaired unusually, returning preprocessor unusually and can carry out the unusual instruction of this generation once more at the second layer, the result causes triggering for the third time unusually, this moment the 3rd layer and the second layer unusually all obtained repaired, so only can trigger the unusual of ground floor, equally, at first be one section pre-service, carry out pop down, exception handler is jumped in operations such as scope check then, turn back to this instruction after exception handler is finished dealing with and carry out, this instruction this moment just can be by having carried out.
For the register dependence that cancellation after exception-triggered has been set up, need specify the micro-order numbering for each register relies on.Shown in Fig. 6 is to set up a kind of method that relies on and cancel dependence for register in the rename module.As shown in Figure 6, running into instruction 2 o'clock, logic register numbering 1 is mapped to physical register number 3, is running into instruction 6 o'clock, logic register numbering 2 is mapped to physical register number 1, running into instruction 8 o'clock, logic register numbering 3 is mapped to physical register number 5, instruction 3,4,5 and 7 not and register set up corresponding relation, this is because these instructions do not have corresponding destination register, i.e. only execution and not writing back of these instructions.Running into instruction 9 o'clock at last, logic register numbering 1 is mapped to physical register number 7, and this moment, same logic register number 1 shone upon two physical registers numbers 3 and 7, and their difference is corresponding order number difference, is respectively 2 and 9.If instruct 8 to take place one unusually, the rename module receives that this is unusual, each dependence and this unusual order number are compared, if the instruction at dependence place is after unusual instruction takes place, then this dependence need be canceled.Therefore, the logic register among Fig. 6 number 1 is cancelled to the dependence of physical register numbers 7, and other dependence keeps.
Fig. 7 is the inner structure block diagram for the code translator 102 of realizing this unusual nested processing.Execution unit 105 notes abnormalities in the process of implementation; it is giving ROQ 106 by result bus 711 unusually; ROQ 106 is in due course and sends exception bus 710 to decoding unit 712; decoding unit 712 is received and ir703 is put behind this signal invalidly, and this is buffered in the exception impact damper 702 unusually.In next bat, rom_pc maker 705 selects the abnormal information of exception impact damper 702 to decipher, generate urom_pc701, and index uROM 704, the micro-order of generation is given micro-order maker 708 by micro-order selector switch 707 and is further deciphered and output on the decoding bus.If take place nestedly unusually, abnormal information can be buffered in the instruction buffer 703 again.Abnormality processing has begun so again.Wherein rom_pc maker 705 is one No. two selector switchs, is responsible for getting corresponding information from exception impact damper 702 and instruction buffer 703 and deciphers, and the information priority of the impact damper 702 that wherein makes an exception is handled.Micro-order selector switch 707 also is one No. two selector switch, is responsible for selecting micro-order to give micro-order maker 708 from uROM 704 and simple demoder 706.Equally, uROM 704 is than the priority height of simple demoder 706.This is because abnormal information need in time be handled.What take place in the time of just can handling the unusual pre-service of complicated order according to this decoder architecture design is nested unusually.
Processor with x86 is an example, and a lot of complicated orders are arranged in the processor of x86 series, and common instructs as the string copy, soft interruption int n instruction, indirect jump instruction etc.These instruct pairing micro-order to be stored in a rom (ROM 103 as shown in Figure 1).Decoding unit is obtained complicated order from storer after, can remove this rom of index, take out micro-order and give the rear end according to the operation code field of this instruction and other the domain of dependence.The rear end comprises rename logic and emission element.The visible general-purpose register of X86 has 8, i.e. eax, ebx, ecx, edx, esi, edi, ebp, esp are corresponding to 8 general registers of micro-order.In addition, also 24 temporary registers have been distributed for microinstruction set.These 24 registers are used for cushioning the operation result of each execution unit, comprise adding unit, multiplying unit, division parts, memory access parts etc.Because it is relevant to produce data to these 32 registers when micro-order is carried out, this being correlated with carried out rename by the rename logic of rear end, thereby eliminated the false appearance pass.Micro-order after the rename is stored in the instruction resequencing buffer according to the order of sequence.The micro-order of instruction in reordering has three state, dummy status, mapping status, writes back state.A certain state in instruction is reordered represents that this can deposit a micro-order when empty, just is not used at present.Mapping status represents that current list item deposited a micro-order, and this micro-order is to come from the rename components, which transmits, and this instruction just carries out or just medium to be launched in scoring plug at execution unit, does not also have operation result to produce.Write back the current instruction of state representation and be finished, and execution result write in the register file, only waited for that processor does last affirmation at execution unit.
The submission of micro-order is carried out according to the order of sequence in the resequencing buffer, at first submits the micro-order that has write back of queue heads to, and the information of submission can be issued the rename parts, and the rename parts go to revise the status information of respective objects register according to the submission information that obtains.If the micro-order of queue heads has been attached unusually, submission information is invalid, abnormal information can be delivered to decoding unit and rename parts, the rename parts are analyzed abnormal information, cancel the dependence that all were once set up then, decoding unit then obtains unusual vector wherein, this is encoded to a special instruction unusually, and the instruction address at the unusual place of record generation, getting corresponding micro-order then from rom carries out, by the exception handler address that micro-order obtains jumping to, carrying out pop down, after preserving pretreatment operation such as crucial scene, change formal exception handler over to.Re-execute this instruction after exception handler is complete, this moment, first unusually obtained repairing, and can not trigger again, only may trigger next unusual.If pop down again, preserve in the crucial on-the-spot process and taken place again unusually, the new vector that the decoding unit buffering obtains, continue the instruction address at this unusual place of buffering, again send same micro-order, unique difference this moment is that unusual numbering has become, and this unusual numbering can be delivered in the corresponding micro-order territory as a micro-order constant.At this moment, the instruction Re-Order Buffer is cleared, and other various functional parts have also all been done removing work.Equally, in the unusual pre-service micro-order of the second layer, also to carry out operations such as pop down, preservation scene, jump to the exception handler of operating system visible at last by a special jump instruction.After exception handler returns, continue to carry out from interrupted instruction, like this owing in exception handler, fault is repaired, just can not take place unusually again running into that trouble spot, and it is unusual only can to handle that of top layer.After disposing, the unusual pairing fault of top layer also obtains repairing, and processor continues down to carry out.Processor is to handle with following order execute exception: after the inferior exception handler of bottommost layer executes, re-execute time profound exception handler, after the exception handler of inferior profound level executes, re-execute profound once more exception handler, the rest may be inferred, carries out the exception handler of top layer time at last.This method is similar to the depth-first traversal in the sort algorithm.
It should be noted last that: above embodiment is the unrestricted technical scheme of the present invention in order to explanation only, although the present invention is had been described in detail with reference to the foregoing description, those of ordinary skill in the art is to be understood that: still can make amendment or be equal to replacement the present invention, and not breaking away from any modification or partial replacement of the spirit and scope of the present invention, it all should be encompassed in the middle of the claim scope of the present invention.
Claims (8)
1. the depth-first abnormality eliminating method in the sophisticated vocabulary architecture may further comprise the steps:
When generation is unusual,
1) the instruction resequencing buffer sends abnormal information and gives affected module, and it is invalid that affected module is changed to self register, thereby brush empty streamline;
2) decoding unit is converted to predefined instruction with described abnormal information;
3) decoding unit is according to described predefined instruction, and the index ROM (read-only memory) is found out micro-order correspondingly, and described micro-order is sent into emission element;
4) emission element will not have the relevant micro-order of data to send into the execution unit execution;
5) execution unit is carried out described micro-order, and execution result is write the instruction resequencing buffer;
6) check whether article one micro-order in the instruction resequencing buffer is unusual;
7) if article one micro-order of instruction in the resequencing buffer is unusual, then returning 1) streamline brushes empty step;
8) if article one micro-order in the instruction resequencing buffer does not take place unusually, article one micro-order of then instructing resequencing buffer to have write back is submitted to, finishes processing.
2. the depth-first abnormality eliminating method in the sophisticated vocabulary architecture according to claim 1, it is characterized in that described 3) the micro-order finding step also comprises: described predefined instruction decoded, and according to decoded result, the index ROM (read-only memory).
3. the depth-first abnormality eliminating method in the sophisticated vocabulary architecture according to claim 1 is characterized in that described 3) the micro-order finding step also comprises: described micro-order left in the instruction resequencing buffer according to the order of sequence.
4. the depth-first abnormality eliminating method in the sophisticated vocabulary architecture according to claim 1 is characterized in that described execution unit comprises a plurality of performance elements.
5. the depth-first abnormality eliminating method in the sophisticated vocabulary architecture according to claim 1 is characterized in that described 6) in the follow-up for anomaly step, check whether many forward micro-orders of ordering in the instruction resequencing buffer are unusual.
6. the depth-first abnormality eliminating method in the sophisticated vocabulary architecture according to claim 5 is characterized in that instructing many forward micro-orders of ordering in the resequencing buffer to be meant article one and second micro-order in the ream weight ordering impact damper.
7. the depth-first abnormality eliminating method in the sophisticated vocabulary architecture according to claim 5 is characterized in that instructing many forward micro-orders of ordering in the resequencing buffer to be meant four micro-orders of article one to the in the ream weight ordering impact damper.
8. according to the depth-first abnormality eliminating method in the described sophisticated vocabulary architecture of one of claim 1～7, it is characterized in that for the relevant micro-order of data, wait for the generation of related data, when producing all related datas, the relevant micro-order of these data is labeled as the micro-order that does not have data relevant.
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