IN2014CN00296A - - Google Patents

Info

Publication number
IN2014CN00296A
IN2014CN00296A IN296CHN2014A IN2014CN00296A IN 2014CN00296 A IN2014CN00296 A IN 2014CN00296A IN 296CHN2014 A IN296CHN2014 A IN 296CHN2014A IN 2014CN00296 A IN2014CN00296 A IN 2014CN00296A
Authority
IN
India
Prior art keywords
mram
address information
cell address
memory
array
Prior art date
Application number
Other languages
English (en)
Inventor
Jung Pill Kim
Taehyun Kim
Hari M Rao
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of IN2014CN00296A publication Critical patent/IN2014CN00296A/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
    • G11C29/789—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes using non-volatile cells or latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/84—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability
    • G11C29/846—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability by choosing redundant lines at an output stage
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C2029/4402—Internal storage of test result, quality data, chip identification, repair information

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Mram Or Spin Memory Techniques (AREA)
  • Hall/Mr Elements (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
IN296CHN2014 2011-07-25 2012-07-25 IN2014CN00296A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/189,784 US8638596B2 (en) 2011-07-25 2011-07-25 Non-volatile memory saving cell information in a non-volatile memory array
PCT/US2012/048208 WO2013016467A1 (en) 2011-07-25 2012-07-25 Non-volatile memory saving cell information in a non-volatile memory array

Publications (1)

Publication Number Publication Date
IN2014CN00296A true IN2014CN00296A (zh) 2015-04-03

Family

ID=46750429

Family Applications (1)

Application Number Title Priority Date Filing Date
IN296CHN2014 IN2014CN00296A (zh) 2011-07-25 2012-07-25

Country Status (7)

Country Link
US (1) US8638596B2 (zh)
EP (1) EP2737484A1 (zh)
JP (2) JP6400535B2 (zh)
KR (2) KR20140047145A (zh)
CN (1) CN103733260B (zh)
IN (1) IN2014CN00296A (zh)
WO (1) WO2013016467A1 (zh)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102083266B1 (ko) * 2013-11-29 2020-03-03 삼성전자주식회사 반도체 메모리 장치의 테스트 방법 및 반도체 메모리 시스템
US9747967B2 (en) 2014-09-26 2017-08-29 Intel Corporation Magnetic field-assisted memory operation
US9401226B1 (en) * 2015-09-14 2016-07-26 Qualcomm Incorporated MRAM initialization devices and methods
US10415408B2 (en) * 2016-02-12 2019-09-17 General Electric Company Thermal stress relief of a component
US10283212B2 (en) 2016-11-29 2019-05-07 International Business Machines Corporation Built-in self-test for embedded spin-transfer torque magnetic random access memory
US9805828B1 (en) 2017-02-21 2017-10-31 Micron Technology, Inc. Memory apparatus with post package repair
JP6819843B1 (ja) * 2020-03-05 2021-01-27 Tdk株式会社 磁気記録アレイ、ニューロモルフィックデバイスおよび磁気記録アレイの制御方法
CN114187954B (zh) * 2020-09-15 2024-08-23 长鑫存储技术有限公司 存储器装置及其测试方法和使用方法、存储器系统
EP4036917B1 (en) * 2020-09-15 2023-05-24 Changxin Memory Technologies, Inc. Memory device, testing method therefor and usage method therefor, and memory system

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63219045A (ja) * 1987-03-09 1988-09-12 Hitachi Ltd Ｉｃカ−ド
JP2914171B2 (ja) * 1994-04-25 1999-06-28 松下電器産業株式会社 半導体メモリ装置およびその駆動方法
JPH11249969A (ja) * 1997-10-09 1999-09-17 Matsushita Electric Ind Co Ltd アドレス変換回路およびアドレス変換システム
US6256237B1 (en) * 1999-12-28 2001-07-03 United Microelectronics Corp. Semiconductor device and method for repairing failed memory cell by directly programming fuse memory cell
JP2002015595A (ja) * 2000-06-29 2002-01-18 Sanyo Electric Co Ltd 冗長メモリ回路
JP2003208796A (ja) * 2002-01-15 2003-07-25 Mitsubishi Electric Corp 薄膜磁性体記憶装置
US6801471B2 (en) 2002-02-19 2004-10-05 Infineon Technologies Ag Fuse concept and method of operation
JP2004013961A (ja) * 2002-06-04 2004-01-15 Mitsubishi Electric Corp 薄膜磁性体記憶装置
JP2004062922A (ja) * 2002-07-25 2004-02-26 Renesas Technology Corp 不揮発性半導体記憶装置
DE10341616A1 (de) * 2003-09-10 2005-05-04 Hyperstone Ag Verwaltung defekter Blöcke in Flash-Speichern
JP2005276276A (ja) 2004-03-23 2005-10-06 Toshiba Corp 半導体集積回路装置
CN1862706A (zh) * 2005-05-12 2006-11-15 恩益禧电子股份有限公司 易失性半导体存储器
JP4686350B2 (ja) * 2005-12-09 2011-05-25 株式会社東芝 不揮発性半導体記憶装置及びその自己テスト方法
KR101228519B1 (ko) * 2005-12-12 2013-02-01 삼성전자주식회사 반도체 메모리 장치, 그것을 포함한 테스트 시스템, 그리고반도체 메모리 장치의 리페어 방법
US7362644B2 (en) * 2005-12-20 2008-04-22 Magic Technologies, Inc. Configurable MRAM and method of configuration
US7764537B2 (en) 2007-04-05 2010-07-27 Qualcomm Incorporated Spin transfer torque magnetoresistive random access memory and design methods
KR101373183B1 (ko) * 2008-01-15 2014-03-14 삼성전자주식회사 3차원 어레이 구조를 갖는 메모리 장치 및 그것의 리페어방법

Also Published As

Publication number Publication date
JP2014522074A (ja) 2014-08-28
CN103733260A (zh) 2014-04-16
JP2015228274A (ja) 2015-12-17
KR20160029871A (ko) 2016-03-15
EP2737484A1 (en) 2014-06-04
US20130028009A1 (en) 2013-01-31
US8638596B2 (en) 2014-01-28
JP6086451B2 (ja) 2017-03-01
KR20140047145A (ko) 2014-04-21
CN103733260B (zh) 2016-12-07
WO2013016467A1 (en) 2013-01-31
JP6400535B2 (ja) 2018-10-03

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