IN2014CH00978A - - Google Patents

Info

Publication number
IN2014CH00978A
IN2014CH00978A IN978CH2014A IN2014CH00978A IN 2014CH00978 A IN2014CH00978 A IN 2014CH00978A IN 978CH2014 A IN978CH2014 A IN 978CH2014A IN 2014CH00978 A IN2014CH00978 A IN 2014CH00978A
Authority
IN
India
Prior art keywords
requester
operating system
execution circuitry
registers
data structures
Prior art date
Application number
Other languages
English (en)
Inventor
V Patel Baiju
B Crossland James
A Khare Atul
Opferman Toby
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of IN2014CH00978A publication Critical patent/IN2014CH00978A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30101—Special purpose registers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/10—Protecting distributed programs or content, e.g. vending or licensing of copyrighted material ; Digital rights management [DRM]
    • G06F21/12—Protecting executable software
    • G06F21/121—Restricting unauthorised execution of programs
    • G06F21/125—Restricting unauthorised execution of programs by manipulating the program code, e.g. source code, compiled code, interpreted code, machine code
    • G06F21/126—Interacting with the operating system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G06F9/30054—Unconditional branch instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/342—Extension of operand address space
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G06F9/545—Interprogram communication where tasks reside in different layers, e.g. user- and kernel-space
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2209/00—Indexing scheme relating to G06F9/00
    • G06F2209/52—Indexing scheme relating to G06F9/52
    • G06F2209/521—Atomic
IN978CH2014 2013-03-15 2014-02-26 IN2014CH00978A (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US13/837,878 US9207940B2 (en) 2013-03-15 2013-03-15 Robust and high performance instructions for system call

Publications (1)

Publication Number Publication Date
IN2014CH00978A true IN2014CH00978A (zh) 2015-05-08

Family

ID=50554831

Family Applications (1)

Application Number Title Priority Date Filing Date
IN978CH2014 IN2014CH00978A (zh) 2013-03-15 2014-02-26

Country Status (7)

Country Link
US (2) US9207940B2 (zh)
JP (1) JP5985526B2 (zh)
KR (2) KR20140113557A (zh)
CN (1) CN104050415B (zh)
DE (1) DE102014003854A1 (zh)
GB (1) GB2514881B (zh)
IN (1) IN2014CH00978A (zh)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6370098B2 (ja) * 2014-05-16 2018-08-08 杉中 順子 情報処理装置、情報処理監視方法、プログラム、及び記録媒体
US10528345B2 (en) * 2015-03-27 2020-01-07 Intel Corporation Instructions and logic to provide atomic range modification operations
US10761877B2 (en) * 2017-07-21 2020-09-01 Intel Corporation Apparatuses, methods, and systems for blockchain transaction acceleration
CN108958798B (zh) * 2018-06-15 2021-04-20 上海兆芯集成电路有限公司 指令翻译电路、处理器电路及其执行方法
US11366663B2 (en) * 2018-11-09 2022-06-21 Intel Corporation Systems and methods for performing 16-bit floating-point vector dot product instructions
US20200409711A1 (en) * 2019-06-29 2020-12-31 Intel Corporation Processor instruction support for mitigating controlled-channel and cache-based side-channel attacks
CN111679857B (zh) * 2020-06-15 2024-01-23 上海兆芯集成电路股份有限公司 高效能复杂指令译码的微处理器
US20240028336A1 (en) * 2022-07-21 2024-01-25 Vmware, Inc. Techniques for reducing cpu privilege boundary crossings

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62286155A (ja) * 1986-06-05 1987-12-12 Sharp Corp マルチｃｐｕ制御方式
JPH03163630A (ja) * 1989-11-21 1991-07-15 Mitsubishi Electric Corp プロセッサのスタック制御方法
US6901505B2 (en) * 2001-08-09 2005-05-31 Advanced Micro Devices, Inc. Instruction causing swap of base address from segment register with address from another register
US20030226014A1 (en) * 2002-05-31 2003-12-04 Schmidt Rodney W. Trusted client utilizing security kernel under secure execution mode
US8607235B2 (en) * 2004-12-30 2013-12-10 Intel Corporation Mechanism to schedule threads on OS-sequestered sequencers without operating system intervention
CN100470571C (zh) * 2006-08-23 2009-03-18 北京同方微电子有限公司 一种用于密码学运算的微处理器内核装置
CN200941211Y (zh) * 2006-08-23 2007-08-29 北京同方微电子有限公司 用于密码学运算的微处理器内核
JP2008102847A (ja) * 2006-10-20 2008-05-01 Nec Corp マルチスレッドプログラム処理方法及び装置
US8578483B2 (en) * 2008-07-31 2013-11-05 Carnegie Mellon University Systems and methods for preventing unauthorized modification of an operating system
US8312468B2 (en) * 2009-06-09 2012-11-13 Open Kernel Labs Methods and apparatus for fast context switching in a virtualized system
US9135215B1 (en) * 2009-09-21 2015-09-15 Tilera Corporation Route prediction in packet switched networks

Also Published As

Publication number Publication date
CN104050415A (zh) 2014-09-17
KR20160072085A (ko) 2016-06-22
US20160092227A1 (en) 2016-03-31
KR20140113557A (ko) 2014-09-24
JP2014182799A (ja) 2014-09-29
KR101780303B1 (ko) 2017-09-21
US9207940B2 (en) 2015-12-08
US20140281437A1 (en) 2014-09-18
GB201404223D0 (en) 2014-04-23
DE102014003854A1 (de) 2014-09-18
GB2514881B (en) 2015-09-30
GB2514881A (en) 2014-12-10
JP5985526B2 (ja) 2016-09-06
CN104050415B (zh) 2017-10-13

Similar Documents

Publication Publication Date Title
IN2014CH00978A (zh)
GB2520644A (en) Accelerated interlane vector reduction instructions
GB2508533A (en) Instruction and logic to provide vector scatter-op and gather-op functionality
PH12017550124A1 (en) Decoupled processor instruction window and operand buffer
GB2533256A (en) Data processing systems
MY177359A (en) User gesture input to wearable electronic device involving movement of device
MX347774B (es) Guardar/restablecer los registros seleccionados en el procesamiento transaccional.
MY168402A (en) Handling and routing interrupts to virtual processors
MX346496B (es) Instrucción de calcular la distancia a una frontera de memoria especificada.
GB2519017A (en) Next instruction access intent instruction
MY172572A (en) Exception handling in a data processing apparatus having a secure domain and a less secure domain
GB2508312A (en) Instruction and logic to provide vector load-op/store-op with stride functionality
GB2518116A (en) Vector move instruction controlled by read and write masks
GB2513266A (en) Providing logical partitions with hardware-thread specific information reflective of exclusive use of a processor core
MX2015014300A (es) Pre-generacion de un objeto de presentacion.
WO2014150727A3 (en) Method, apparatuses and program product to save and store system memory management unit contexts
GB2517877A (en) Controlling an order for processing data elements during vector processing
IN2014DN05705A (zh)
GB2507018A (en) Instruction and logic to provide vector loads and stores with strides and masking functionality
GB2520856A (en) Enabling Virtualization of a processor resource
MY159188A (en) Controlling generation of debug exceptions
WO2014033639A3 (en) Introspection of software program components and conditional generation of memory dump
GB2520860A (en) Systems, apparatuses, and methods for performing conflict detection and broadcasting contents of a register to data element positions of another register
JP2015504226A5 (zh)
GB2562014A (en) Prioritization of transactions