IN2014CH00859A - - Google Patents
Info
- Publication number
- IN2014CH00859A IN2014CH00859A IN859CH2014A IN2014CH00859A IN 2014CH00859 A IN2014CH00859 A IN 2014CH00859A IN 859CH2014 A IN859CH2014 A IN 859CH2014A IN 2014CH00859 A IN2014CH00859 A IN 2014CH00859A
- Authority
- IN
- India
- Prior art keywords
- instruction
- instructions
- test
- operand
- branch
- Prior art date
Links
- 230000001419 dependent effect Effects 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30029—Logical and Boolean instructions, e.g. XOR, NOT
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/40—Transformation of program code
- G06F8/52—Binary to binary
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
- G06F9/30058—Conditional branch instructions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30094—Condition code generation, e.g. Carry, Zero flag
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/3017—Runtime instruction translation, e.g. macros
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30181—Instruction operation extension or modification
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30181—Instruction operation extension or modification
- G06F9/30196—Instruction operation extension or modification using decoder, e.g. decoder per instruction set, adaptable or programmable decoders
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
- G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
- G06F9/323—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for indirect branch instructions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3853—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution of compound instructions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
- G06F9/45504—Abstract machines for programme code execution, e.g. Java virtual machine [JVM], interpreters, emulators
- G06F9/45516—Runtime code conversion or optimisation
- G06F9/4552—Involving translation to a different instruction set architecture, e.g. just-in-time translation in a JVM
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Advance Control (AREA)
- Executing Machine-Instructions (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
Methods and apparatus are disclosed for fusing instructions to provide OR-test and AND-test functionality on multiple test sources. Some embodiments include fetching instructions, said instructions including a first instruction specifying a first operand destination, a second instruction specifying a second operand source, and a third instruction specifying a branch condition. A portion of the plurality of instructions are fused into a single micro-operation, the portion including both the first and second instructions if said first operand destination and said second operand source are the same, and said branch condition is dependent upon the second instruction. Some embodiments generate a novel test instruction dynamically by fusing one logical instruction with a prior-art test instruction. Other embodiments generate the novel test instruction through a just-in-time compiler. Some embodiments also fuse the novel test instruction with a subsequent conditional branch instruction, and perform a branch according to how the condition flag is set.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/842,754 US9886277B2 (en) | 2013-03-15 | 2013-03-15 | Methods and apparatus for fusing instructions to provide OR-test and AND-test functionality on multiple test sources |
Publications (1)
Publication Number | Publication Date |
---|---|
IN2014CH00859A true IN2014CH00859A (en) | 2015-04-24 |
Family
ID=50440386
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
IN859CH2014 IN2014CH00859A (en) | 2013-03-15 | 2014-02-21 |
Country Status (7)
Country | Link |
---|---|
US (1) | US9886277B2 (en) |
JP (2) | JP2014194755A (en) |
KR (1) | KR101712864B1 (en) |
CN (1) | CN104049945B (en) |
DE (1) | DE102014003795A1 (en) |
GB (1) | GB2512726B (en) |
IN (1) | IN2014CH00859A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10310860B2 (en) | 2016-07-29 | 2019-06-04 | International Business Machines Corporation | Starting and stopping instruction dispatch to execution unit queues in a multi-pipeline processor |
Families Citing this family (39)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2480285A (en) * | 2010-05-11 | 2011-11-16 | Advanced Risc Mach Ltd | Conditional compare instruction which sets a condition code when it is not executed |
US9672037B2 (en) * | 2013-01-23 | 2017-06-06 | Apple Inc. | Arithmetic branch fusion |
US9715385B2 (en) | 2013-01-23 | 2017-07-25 | International Business Machines Corporation | Vector exception code |
US9471308B2 (en) * | 2013-01-23 | 2016-10-18 | International Business Machines Corporation | Vector floating point test data class immediate instruction |
US9804840B2 (en) | 2013-01-23 | 2017-10-31 | International Business Machines Corporation | Vector Galois Field Multiply Sum and Accumulate instruction |
US9778932B2 (en) | 2013-01-23 | 2017-10-03 | International Business Machines Corporation | Vector generate mask instruction |
US9513906B2 (en) | 2013-01-23 | 2016-12-06 | International Business Machines Corporation | Vector checksum instruction |
US9823924B2 (en) | 2013-01-23 | 2017-11-21 | International Business Machines Corporation | Vector element rotate and insert under mask instruction |
US9483266B2 (en) * | 2013-03-15 | 2016-11-01 | Intel Corporation | Fusible instructions and logic to provide OR-test and AND-test functionality using multiple test sources |
KR20140134376A (en) * | 2013-05-14 | 2014-11-24 | 한국전자통신연구원 | Processor capable of fault detection and method of detecting fault of processor core using the same |
US20160179542A1 (en) * | 2014-12-23 | 2016-06-23 | Patrick P. Lai | Instruction and logic to perform a fused single cycle increment-compare-jump |
US9940136B2 (en) | 2015-06-26 | 2018-04-10 | Microsoft Technology Licensing, Llc | Reuse of decoded instructions |
US10191747B2 (en) | 2015-06-26 | 2019-01-29 | Microsoft Technology Licensing, Llc | Locking operand values for groups of instructions executed atomically |
US10346168B2 (en) | 2015-06-26 | 2019-07-09 | Microsoft Technology Licensing, Llc | Decoupled processor instruction window and operand buffer |
US9946548B2 (en) | 2015-06-26 | 2018-04-17 | Microsoft Technology Licensing, Llc | Age-based management of instruction blocks in a processor instruction window |
US9952867B2 (en) | 2015-06-26 | 2018-04-24 | Microsoft Technology Licensing, Llc | Mapping instruction blocks based on block size |
US10409606B2 (en) | 2015-06-26 | 2019-09-10 | Microsoft Technology Licensing, Llc | Verifying branch targets |
US10169044B2 (en) | 2015-06-26 | 2019-01-01 | Microsoft Technology Licensing, Llc | Processing an encoding format field to interpret header information regarding a group of instructions |
US10175988B2 (en) | 2015-06-26 | 2019-01-08 | Microsoft Technology Licensing, Llc | Explicit instruction scheduler state information for a processor |
US11755484B2 (en) | 2015-06-26 | 2023-09-12 | Microsoft Technology Licensing, Llc | Instruction block allocation |
US10409599B2 (en) | 2015-06-26 | 2019-09-10 | Microsoft Technology Licensing, Llc | Decoding information about a group of instructions including a size of the group of instructions |
US10095519B2 (en) | 2015-09-19 | 2018-10-09 | Microsoft Technology Licensing, Llc | Instruction block address register |
GB2543304B (en) * | 2015-10-14 | 2020-10-28 | Advanced Risc Mach Ltd | Move prefix instruction |
US10324724B2 (en) * | 2015-12-16 | 2019-06-18 | Intel Corporation | Hardware apparatuses and methods to fuse instructions |
US20170192788A1 (en) * | 2016-01-05 | 2017-07-06 | Intel Corporation | Binary translation support using processor instruction prefixes |
US10372452B2 (en) * | 2017-03-14 | 2019-08-06 | Samsung Electronics Co., Ltd. | Memory load to load fusing |
GB2560892B (en) * | 2017-03-23 | 2021-06-02 | Advanced Risc Mach Ltd | Graphics Processing |
US10559056B2 (en) * | 2017-06-12 | 2020-02-11 | Arm Limited | Graphics processing |
US10592246B2 (en) | 2017-07-12 | 2020-03-17 | International Business Machines Corporation | Low latency execution of floating-point record form instructions |
US11150908B2 (en) * | 2017-08-18 | 2021-10-19 | International Business Machines Corporation | Dynamic fusion of derived value creation and prediction of derived values in a subroutine branch sequence |
CN108509202A (en) * | 2018-03-30 | 2018-09-07 | 天津麒麟信息技术有限公司 | Multiplication of integers optimization method based on platform red fox browser JIT engines of soaring |
US10534881B2 (en) * | 2018-04-10 | 2020-01-14 | Advanced Micro Devices, Inc. | Method of debugging a processor |
US10996952B2 (en) | 2018-12-10 | 2021-05-04 | SiFive, Inc. | Macro-op fusion |
WO2021250689A1 (en) * | 2020-06-12 | 2021-12-16 | Gulzar Singh | Novel hardware accelerator circuit for bit-level operations in a microcontroller |
CN112214242A (en) * | 2020-09-23 | 2021-01-12 | 上海赛昉科技有限公司 | RISC-V instruction compression method, system and computer readable medium |
CN112346780B (en) * | 2020-11-05 | 2022-11-15 | 海光信息技术股份有限公司 | Information processing method, device and storage medium |
US11714649B2 (en) * | 2021-11-29 | 2023-08-01 | Shandong Lingneng Electronic Technology Co., Ltd. | RISC-V-based 3D interconnected multi-core processor architecture and working method thereof |
CN117193861B (en) * | 2023-11-07 | 2024-03-15 | 芯来智融半导体科技(上海)有限公司 | Instruction processing method, apparatus, computer device and storage medium |
CN118312220B (en) * | 2024-06-11 | 2024-08-30 | 北京微核芯科技有限公司 | Method, device and equipment for sending instruction |
Family Cites Families (38)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US2009200A (en) | 1934-03-19 | 1935-07-23 | Arthur J Penick | Tubing head |
US5051940A (en) * | 1990-04-04 | 1991-09-24 | International Business Machines Corporation | Data dependency collapsing hardware apparatus |
JPH0437926A (en) * | 1990-06-01 | 1992-02-07 | Sony Corp | Digital computer |
JP2876773B2 (en) | 1990-10-22 | 1999-03-31 | セイコーエプソン株式会社 | Program instruction word length variable type computing device and data processing device |
CA2173226C (en) | 1993-10-12 | 2001-08-14 | Robert B. Lowe, Jr. | Hardware assisted modify count instruction |
US5596763A (en) | 1993-11-30 | 1997-01-21 | Texas Instruments Incorporated | Three input arithmetic logic unit forming mixed arithmetic and boolean combinations |
US5666300A (en) | 1994-12-22 | 1997-09-09 | Motorola, Inc. | Power reduction in a data processing system using pipeline registers and method therefor |
DE69738810D1 (en) * | 1996-01-24 | 2008-08-14 | Sun Microsystems Inc | COMMAND FOLDING IN A STACK MEMORY PROCESSOR |
JPH09311786A (en) * | 1996-03-18 | 1997-12-02 | Hitachi Ltd | Data processor |
TW325552B (en) | 1996-09-23 | 1998-01-21 | Advanced Risc Mach Ltd | Data processing condition code flags |
GB2317466B (en) | 1996-09-23 | 2000-11-08 | Advanced Risc Mach Ltd | Data processing condition code flags |
US5860107A (en) * | 1996-10-07 | 1999-01-12 | International Business Machines Corporation | Processor and method for store gathering through merged store operations |
JP3790607B2 (en) | 1997-06-16 | 2006-06-28 | 松下電器産業株式会社 | VLIW processor |
US6961846B1 (en) | 1997-09-12 | 2005-11-01 | Infineon Technologies North America Corp. | Data processing unit, microprocessor, and method for performing an instruction |
US6173393B1 (en) | 1998-03-31 | 2001-01-09 | Intel Corporation | System for writing select non-contiguous bytes of data with single instruction having operand identifying byte mask corresponding to respective blocks of packed data |
US6237085B1 (en) | 1998-12-08 | 2001-05-22 | International Business Machines Corporation | Processor and method for generating less than (LT), Greater than (GT), and equal to (EQ) condition code bits concurrent with a logical or complex operation |
US6233675B1 (en) * | 1999-03-25 | 2001-05-15 | Rise Technology Company | Facility to allow fast execution of and, or, and test instructions |
US6338136B1 (en) | 1999-05-18 | 2002-01-08 | Ip-First, Llc | Pairing of load-ALU-store with conditional branch |
US6370625B1 (en) | 1999-12-29 | 2002-04-09 | Intel Corporation | Method and apparatus for lock synchronization in a microprocessor system |
US6647489B1 (en) | 2000-06-08 | 2003-11-11 | Ip-First, Llc | Compare branch instruction pairing within a single integer pipeline |
US6675376B2 (en) | 2000-12-29 | 2004-01-06 | Intel Corporation | System and method for fusing instructions |
US6889318B1 (en) * | 2001-08-07 | 2005-05-03 | Lsi Logic Corporation | Instruction fusion for digital signal processor |
US7051190B2 (en) | 2002-06-25 | 2006-05-23 | Intel Corporation | Intra-instruction fusion |
US6920546B2 (en) | 2002-08-13 | 2005-07-19 | Intel Corporation | Fusion of processor micro-operations |
US20040128483A1 (en) * | 2002-12-31 | 2004-07-01 | Intel Corporation | Fuser renamer apparatus, systems, and methods |
US7529914B2 (en) | 2004-06-30 | 2009-05-05 | Intel Corporation | Method and apparatus for speculative execution of uncontended lock instructions |
US7817767B2 (en) | 2004-12-23 | 2010-10-19 | Rambus Inc. | Processor-controlled clock-data recovery |
US8082430B2 (en) | 2005-08-09 | 2011-12-20 | Intel Corporation | Representing a plurality of instructions with a fewer number of micro-operations |
US7849292B1 (en) | 2005-09-28 | 2010-12-07 | Oracle America, Inc. | Flag optimization of a trace |
US7958181B2 (en) * | 2006-09-21 | 2011-06-07 | Intel Corporation | Method and apparatus for performing logical compare operations |
US20090164758A1 (en) | 2007-12-20 | 2009-06-25 | Haertel Michael J | System and Method for Performing Locked Operations |
US7937561B2 (en) | 2008-04-03 | 2011-05-03 | Via Technologies, Inc. | Merge microinstruction for minimizing source dependencies in out-of-order execution microprocessor with variable data size macroarchitecture |
US9690591B2 (en) | 2008-10-30 | 2017-06-27 | Intel Corporation | System and method for fusing instructions queued during a time window defined by a delay counter |
US20110138156A1 (en) | 2009-10-15 | 2011-06-09 | Awad Tom | Method and apparatus for evaluating a logical expression and processor making use of same |
US8850164B2 (en) | 2010-04-27 | 2014-09-30 | Via Technologies, Inc. | Microprocessor that fuses MOV/ALU/JCC instructions |
US8856496B2 (en) * | 2010-04-27 | 2014-10-07 | Via Technologies, Inc. | Microprocessor that fuses load-alu-store and JCC macroinstructions |
US9672037B2 (en) | 2013-01-23 | 2017-06-06 | Apple Inc. | Arithmetic branch fusion |
US9483266B2 (en) * | 2013-03-15 | 2016-11-01 | Intel Corporation | Fusible instructions and logic to provide OR-test and AND-test functionality using multiple test sources |
-
2013
- 2013-03-15 US US13/842,754 patent/US9886277B2/en active Active
-
2014
- 2014-02-18 JP JP2014028261A patent/JP2014194755A/en active Pending
- 2014-02-19 GB GB1402906.0A patent/GB2512726B/en active Active
- 2014-02-21 IN IN859CH2014 patent/IN2014CH00859A/en unknown
- 2014-03-12 KR KR1020140029213A patent/KR101712864B1/en active IP Right Grant
- 2014-03-14 CN CN201410097423.XA patent/CN104049945B/en active Active
- 2014-03-17 DE DE102014003795.9A patent/DE102014003795A1/en not_active Withdrawn
-
2015
- 2015-12-24 JP JP2015251651A patent/JP6227621B2/en active Active
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10310860B2 (en) | 2016-07-29 | 2019-06-04 | International Business Machines Corporation | Starting and stopping instruction dispatch to execution unit queues in a multi-pipeline processor |
Also Published As
Publication number | Publication date |
---|---|
CN104049945A (en) | 2014-09-17 |
DE102014003795A1 (en) | 2014-09-18 |
CN104049945B (en) | 2018-11-30 |
JP6227621B2 (en) | 2017-11-08 |
US9886277B2 (en) | 2018-02-06 |
US20140281389A1 (en) | 2014-09-18 |
GB2512726B (en) | 2016-02-10 |
GB201402906D0 (en) | 2014-04-02 |
JP2016103280A (en) | 2016-06-02 |
GB2512726A (en) | 2014-10-08 |
KR101712864B1 (en) | 2017-03-08 |
JP2014194755A (en) | 2014-10-09 |
KR20140113432A (en) | 2014-09-24 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
IN2014CH00859A (en) | ||
EP4273765A3 (en) | An apparatus for hardware accelerated machine learning | |
GB201304555D0 (en) | Execute at commit state update instructions,apparatus,methods and systems | |
BR112017004614A2 (en) | anti-cd38 antibody combination therapies | |
EP4354303A3 (en) | Systems, methods, and apparatuses for matrix add, subtract, and multiply | |
BR112016000903A2 (en) | antibodies | |
EP4242892A3 (en) | Code pointer authentication for hardware flow control | |
BR112017010303A2 (en) | cd47 antibodies, methods and uses | |
WO2015036867A3 (en) | Method and system for instruction scheduling | |
CR20160199A (en) | COMBINED THERAPY WITH AN ANTI-ANG2 ANTIBODY AND A CD40 AGONIST | |
CR20150492A (en) | ANTI-LAG-3 UNION PROTEINS | |
BR112014019331A2 (en) | cd47 antibodies and methods of use of these | |
MY192978A (en) | Combination therapies for heme malignancies with anti-cd38 antibodies and survivin inhibitors | |
IN2014CN00797A (en) | ||
GB2508312A (en) | Instruction and logic to provide vector load-op/store-op with stride functionality | |
WO2012083266A3 (en) | Fusing debug information from different compiler stages | |
CO6761367A2 (en) | Viral inactivation using an improved solvent-detergent method | |
GB2515203A (en) | Smart Bulb System | |
BR112014021206A2 (en) | OPTICAL COATING COLLAR LOCATOR SYSTEMS AND METHODS | |
WO2015011567A3 (en) | Method and system for compiler optimization | |
AU2015330266A8 (en) | Efficient interruption routing for a multithreaded processor | |
IN2013CH04831A (en) | ||
BR112012020491A2 (en) | process for the preparation of alpha form of imatinib mesylate. | |
TR201819828T4 (en) | Anti-phospholipase d4 antibody. | |
MX2016002233A (en) | Optical transmission a. |