IN2013KN03842A - - Google Patents

Info

Publication number
IN2013KN03842A
IN2013KN03842A IN3842KON2013A IN2013KN03842A IN 2013KN03842 A IN2013KN03842 A IN 2013KN03842A IN 3842KON2013 A IN3842KON2013 A IN 3842KON2013A IN 2013KN03842 A IN2013KN03842 A IN 2013KN03842A
Authority
IN
India
Prior art keywords
tlp
pcie switching
transmission
destination
active
Prior art date
Application number
Inventor
Dexian Su
Yimin Yao
Jing Wang
Original Assignee
Huawei Tech Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huawei Tech Co Ltd filed Critical Huawei Tech Co Ltd
Publication of IN2013KN03842A publication Critical patent/IN2013KN03842A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/35—Switches specially adapted for specific applications
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Information Transfer Systems (AREA)
  • Communication Control (AREA)

Abstract

Embodiments of the present invention disclose a peripheral component interconnect express interface control unit. The peripheral component interconnect express interface control unit includes a PCI to PCI bridge P2P module, configured to receive a first transaction layer packet TLP from a root complex RC or an endpoint device EP and forward the first TLP to a reliable TLP transmission RTT module for processing; the reliable TLP transmission module, configured to determine, according to the received first TLP, sending links connected to active and standby PCIE switching units, and send the first TLP to the active and standby PCIE switching units through the sending links at the same time, so that a destination PCIE interface controller of the first TLP selectively receives the first TLP forwarded by the active and standby PCIE switching units and sends the first TLP to a destination EP or a destination RC of the first TLP, thereby implementing reliable transmission of a TLP in a case of a PCIE switching dual-plane networking connection, and improving reliability of a system using PCIE switching. The embodiments of the present invention further disclose a method, system, and storage medium for packet transmission in a PCIE switching network.
IN3842KON2013 2012-10-27 2012-10-27 IN2013KN03842A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2012/083631 WO2014063370A1 (en) 2012-10-27 2012-10-27 Method, device, system and storage medium for achieving message transmission of pcie switch network

Publications (1)

Publication Number Publication Date
IN2013KN03842A true IN2013KN03842A (en) 2015-05-01

Family

ID=48208641

Family Applications (1)

Application Number Title Priority Date Filing Date
IN3842KON2013 IN2013KN03842A (en) 2012-10-27 2012-10-27

Country Status (9)

Country Link
US (3) US9652426B2 (en)
EP (2) EP2741456B1 (en)
JP (1) JP5828966B2 (en)
KR (1) KR101579917B1 (en)
CN (1) CN103098428B (en)
AU (1) AU2012384904B2 (en)
CA (1) CA2838836C (en)
IN (1) IN2013KN03842A (en)
WO (1) WO2014063370A1 (en)

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Also Published As

Publication number Publication date
EP2741456A1 (en) 2014-06-11
EP2741456B1 (en) 2016-01-13
US10204070B2 (en) 2019-02-12
CN103098428A (en) 2013-05-08
CA2838836C (en) 2018-05-01
KR101579917B1 (en) 2015-12-23
WO2014063370A1 (en) 2014-05-01
AU2012384904B2 (en) 2015-04-16
CA2838836A1 (en) 2014-04-27
US9535867B2 (en) 2017-01-03
US20170075842A1 (en) 2017-03-16
AU2012384904A1 (en) 2014-05-15
US20140122769A1 (en) 2014-05-01
US9652426B2 (en) 2017-05-16
EP2741456A4 (en) 2014-07-23
US20140122768A1 (en) 2014-05-01
EP3032787B1 (en) 2018-08-29
KR20140082630A (en) 2014-07-02
JP5828966B2 (en) 2015-12-09
EP3032787A1 (en) 2016-06-15
CN103098428B (en) 2016-03-09
JP2015503154A (en) 2015-01-29

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