IN2013CH04627A - - Google Patents

Info

Publication number
IN2013CH04627A
IN2013CH04627A IN4627CH2013A IN2013CH04627A IN 2013CH04627 A IN2013CH04627 A IN 2013CH04627A IN 4627CH2013 A IN4627CH2013 A IN 4627CH2013A IN 2013CH04627 A IN2013CH04627 A IN 2013CH04627A
Authority
IN
India
Prior art keywords
power supply
virtual power
supply node
virtual
nodes
Prior art date
Application number
Inventor
Saif Kunjatur Sheikh Mohammed
Shanmukheswara Rao Setti
Rachamadugu Vinod
Original Assignee
Lsi Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lsi Corp filed Critical Lsi Corp
Priority to IN4627CH2013 priority Critical patent/IN2013CH04627A/en
Priority to US14/102,649 priority patent/US20150103604A1/en
Publication of IN2013CH04627A publication Critical patent/IN2013CH04627A/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

Abstract A memory device includes a memory array having a plurality of memory cells each having first and second power supply nodes, first and second virtual power supply nodes, a latch circuit, and a write assist circuit. The latch circuit includes a first and second inverters in a cross-coupled inverter configuration. The first inverter is connected between the first virtual power supply node and the second power supply node, and the second inverter is connected between the second virtual power supply node and the second power supply node. The write assist circuit selectively supplies power to the first and second virtual power supply nodes during memory access operations, and is controlled by a first control signal to switchably connect the first power supply node to and from the first and second virtual power supply nodes, and a second control signal to switchably connect the one or both of the first and second virtual power supply nodes to a virtual power supply node of an adjacent memory cell of an adj acent row in the memory array.
IN4627CH2013 2013-10-14 2013-10-14 IN2013CH04627A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
IN4627CH2013 IN2013CH04627A (en) 2013-10-14 2013-10-14
US14/102,649 US20150103604A1 (en) 2013-10-14 2013-12-11 Memory array architectures having memory cells with shared write assist circuitry

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IN4627CH2013 IN2013CH04627A (en) 2013-10-14 2013-10-14

Publications (1)

Publication Number Publication Date
IN2013CH04627A true IN2013CH04627A (en) 2015-04-24

Family

ID=52809534

Family Applications (1)

Application Number Title Priority Date Filing Date
IN4627CH2013 IN2013CH04627A (en) 2013-10-14 2013-10-14

Country Status (2)

Country Link
US (1) US20150103604A1 (en)
IN (1) IN2013CH04627A (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10176855B2 (en) * 2013-11-21 2019-01-08 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional (3-D) write assist scheme for memory cells
US9940993B2 (en) * 2016-04-07 2018-04-10 Arm Limited Storage bitcell with isolation
US9837144B1 (en) 2017-01-17 2017-12-05 Qualcomm Incorporated Apparatus and method for controlling boost capacitance for low power memory circuits
US10147483B1 (en) * 2017-09-19 2018-12-04 Qualcomm Incorporated Robust write driver scheme for static random access memory compilers
KR102547658B1 (en) * 2018-05-29 2023-06-27 에스케이하이닉스 주식회사 Data output buffer and memory device having the same
US10446223B1 (en) 2018-08-29 2019-10-15 Bitfury Group Limited Data storage apparatus, and related systems and methods
US11488658B2 (en) 2020-04-29 2022-11-01 Qualcomm Incorporated Write assist scheme with bitline
CN111710355B (en) * 2020-05-21 2022-05-13 中国人民武装警察部队海警学院 Differential power supply circuit for improving writing capability of SRAM chip

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4912016B2 (en) * 2005-05-23 2012-04-04 ルネサスエレクトロニクス株式会社 Semiconductor memory device

Also Published As

Publication number Publication date
US20150103604A1 (en) 2015-04-16

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