IN2012DN02863A - - Google Patents

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Publication number
IN2012DN02863A
IN2012DN02863A IN2863DEN2012A IN2012DN02863A IN 2012DN02863 A IN2012DN02863 A IN 2012DN02863A IN 2863DEN2012 A IN2863DEN2012 A IN 2863DEN2012A IN 2012DN02863 A IN2012DN02863 A IN 2012DN02863A
Authority
IN
India
Prior art keywords
memory
processing unit
private
unit coupled
processing system
Prior art date
Application number
Other languages
English (en)
Inventor
Philip J Rogers
Warren Friz Kruger
Mark Hummel
Eric Demers
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of IN2012DN02863A publication Critical patent/IN2012DN02863A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G06F12/0835—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means for main memory peripheral accesses (e.g. I/O or DMA)
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/001—Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/363—Graphics controllers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2350/00—Solving problems of bandwidth in display systems
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/121—Frame memory handling using a cache memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Human Computer Interaction (AREA)
  • Computer Graphics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Digital Computer Display Output (AREA)
  • Hardware Redundancy (AREA)
  • Multi Processors (AREA)
IN2863DEN2012 2009-09-10 2010-09-10 IN2012DN02863A (en:Method)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US24120309P 2009-09-10 2009-09-10
US12/878,223 US8615637B2 (en) 2009-09-10 2010-09-09 Systems and methods for processing memory requests in a multi-processor system using a probe engine
PCT/US2010/048428 WO2011031969A1 (en) 2009-09-10 2010-09-10 Systems and methods for processing memory requests

Publications (1)

Publication Number Publication Date
IN2012DN02863A true IN2012DN02863A (en:Method) 2015-07-24

Family

ID=43648547

Family Applications (1)

Application Number Title Priority Date Filing Date
IN2863DEN2012 IN2012DN02863A (en:Method) 2009-09-10 2010-09-10

Country Status (7)

Country Link
US (1) US8615637B2 (en:Method)
EP (1) EP2476051B1 (en:Method)
JP (1) JP6196445B2 (en:Method)
KR (1) KR101593107B1 (en:Method)
CN (1) CN102576299B (en:Method)
IN (1) IN2012DN02863A (en:Method)
WO (1) WO2011031969A1 (en:Method)

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US9430391B2 (en) * 2012-03-29 2016-08-30 Advanced Micro Devices, Inc. Managing coherent memory between an accelerated processing device and a central processing unit
US9218289B2 (en) * 2012-08-06 2015-12-22 Qualcomm Incorporated Multi-core compute cache coherency with a release consistency memory ordering model
US9323679B2 (en) * 2012-08-14 2016-04-26 Nvidia Corporation System, method, and computer program product for managing cache miss requests
US9373182B2 (en) 2012-08-17 2016-06-21 Intel Corporation Memory sharing via a unified memory architecture
US20140101405A1 (en) * 2012-10-05 2014-04-10 Advanced Micro Devices, Inc. Reducing cold tlb misses in a heterogeneous computing system
CN104216837A (zh) * 2013-05-31 2014-12-17 华为技术有限公司 一种内存系统、内存访问请求的处理方法和计算机系统
US9734079B2 (en) * 2013-06-28 2017-08-15 Intel Corporation Hybrid exclusive multi-level memory architecture with memory management
KR102329269B1 (ko) * 2013-10-21 2021-11-22 에프엘씨 글로벌 리미티드 최종 레벨 캐시 시스템 및 이에 대응하는 방법
US11822474B2 (en) 2013-10-21 2023-11-21 Flc Global, Ltd Storage system and method for accessing same
JP2016170729A (ja) 2015-03-13 2016-09-23 株式会社東芝 メモリシステム
US9424192B1 (en) 2015-04-02 2016-08-23 International Business Machines Corporation Private memory table for reduced memory coherence traffic
US9842050B2 (en) 2015-04-30 2017-12-12 International Business Machines Corporation Add-on memory coherence directory
CN106651748B (zh) * 2015-10-30 2019-10-22 华为技术有限公司 一种图像处理方法与图像处理装置
US10409614B2 (en) 2017-04-24 2019-09-10 Intel Corporation Instructions having support for floating point and integer data types in the same register
US10474458B2 (en) 2017-04-28 2019-11-12 Intel Corporation Instructions and logic to perform floating-point and integer operations for machine learning
US11030126B2 (en) * 2017-07-14 2021-06-08 Intel Corporation Techniques for managing access to hardware accelerator memory
US10402937B2 (en) 2017-12-28 2019-09-03 Nvidia Corporation Multi-GPU frame rendering
GB2571536B (en) * 2018-02-28 2020-03-11 Imagination Tech Ltd Coherency manager
GB2571538B (en) 2018-02-28 2020-08-19 Imagination Tech Ltd Memory interface
GB2571539B (en) * 2018-02-28 2020-08-19 Imagination Tech Ltd Memory interface
CN112997161B (zh) 2018-06-18 2025-02-21 Flc技术集团股份有限公司 将储存系统用作主存储器的方法和装置
CN113383310A (zh) 2019-03-15 2021-09-10 英特尔公司 矩阵加速器架构内的脉动分解
US11934342B2 (en) 2019-03-15 2024-03-19 Intel Corporation Assistance for hardware prefetch in cache access
EP3938913A1 (en) 2019-03-15 2022-01-19 INTEL Corporation Multi-tile architecture for graphics operations
EP3938893B1 (en) 2019-03-15 2025-10-15 Intel Corporation Systems and methods for cache optimization
US11861761B2 (en) 2019-11-15 2024-01-02 Intel Corporation Graphics processing unit processing and caching improvements
KR20220064230A (ko) * 2020-11-11 2022-05-18 삼성전자주식회사 다중 프로토콜에 기초하여 메모리에 액세스하기 위한 시스템, 장치 및 방법
CN115202892B (zh) * 2022-09-15 2022-12-23 粤港澳大湾区数字经济研究院(福田) 一种机密计算协处理器的内存扩展系统和内存扩展方法

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Also Published As

Publication number Publication date
EP2476051A1 (en) 2012-07-18
US20110060879A1 (en) 2011-03-10
WO2011031969A1 (en) 2011-03-17
CN102576299A (zh) 2012-07-11
CN102576299B (zh) 2015-11-25
KR20120060230A (ko) 2012-06-11
US8615637B2 (en) 2013-12-24
JP6196445B2 (ja) 2017-09-13
KR101593107B1 (ko) 2016-02-11
EP2476051B1 (en) 2019-10-23
JP2013504822A (ja) 2013-02-07

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