IN2012DN02863A - - Google Patents

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Publication number
IN2012DN02863A
IN2012DN02863A IN2863DEN2012A IN2012DN02863A IN 2012DN02863 A IN2012DN02863 A IN 2012DN02863A IN 2863DEN2012 A IN2863DEN2012 A IN 2863DEN2012A IN 2012DN02863 A IN2012DN02863 A IN 2012DN02863A
Authority
IN
India
Prior art keywords
memory
processing unit
private
unit coupled
processing system
Prior art date
Application number
Inventor
Philip J Rogers
Warren Friz Kruger
Mark Hummel
Eric Demers
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of IN2012DN02863A publication Critical patent/IN2012DN02863A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G06F12/0835—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means for main memory peripheral accesses (e.g. I/O or DMA)
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/001—Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/363—Graphics controllers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2350/00—Solving problems of bandwidth in display systems
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/121—Frame memory handling using a cache memory

Abstract

A processing system is provided. The processing system includes a first processing unit coupled to a first memory and a second processing unit coupled to a second memory. The second memory comprises a coherent memory and a private memory that is private to the second processing unit.
IN2863DEN2012 2009-09-10 2010-09-10 IN2012DN02863A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US24120309P 2009-09-10 2009-09-10
US12/878,223 US8615637B2 (en) 2009-09-10 2010-09-09 Systems and methods for processing memory requests in a multi-processor system using a probe engine
PCT/US2010/048428 WO2011031969A1 (en) 2009-09-10 2010-09-10 Systems and methods for processing memory requests

Publications (1)

Publication Number Publication Date
IN2012DN02863A true IN2012DN02863A (en) 2015-07-24

Family

ID=43648547

Family Applications (1)

Application Number Title Priority Date Filing Date
IN2863DEN2012 IN2012DN02863A (en) 2009-09-10 2010-09-10

Country Status (7)

Country Link
US (1) US8615637B2 (en)
EP (1) EP2476051B1 (en)
JP (1) JP6196445B2 (en)
KR (1) KR101593107B1 (en)
CN (1) CN102576299B (en)
IN (1) IN2012DN02863A (en)
WO (1) WO2011031969A1 (en)

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US9218289B2 (en) * 2012-08-06 2015-12-22 Qualcomm Incorporated Multi-core compute cache coherency with a release consistency memory ordering model
US9323679B2 (en) * 2012-08-14 2016-04-26 Nvidia Corporation System, method, and computer program product for managing cache miss requests
US9373182B2 (en) * 2012-08-17 2016-06-21 Intel Corporation Memory sharing via a unified memory architecture
US20140101405A1 (en) * 2012-10-05 2014-04-10 Advanced Micro Devices, Inc. Reducing cold tlb misses in a heterogeneous computing system
CN104216837A (en) * 2013-05-31 2014-12-17 华为技术有限公司 Memory system, memory access request processing method and computer system
US9734079B2 (en) * 2013-06-28 2017-08-15 Intel Corporation Hybrid exclusive multi-level memory architecture with memory management
US11822474B2 (en) 2013-10-21 2023-11-21 Flc Global, Ltd Storage system and method for accessing same
JP2016170729A (en) 2015-03-13 2016-09-23 株式会社東芝 Memory system
US9424192B1 (en) 2015-04-02 2016-08-23 International Business Machines Corporation Private memory table for reduced memory coherence traffic
US9842050B2 (en) 2015-04-30 2017-12-12 International Business Machines Corporation Add-on memory coherence directory
CN106651748B (en) * 2015-10-30 2019-10-22 华为技术有限公司 A kind of image processing method and image processing apparatus
US11030126B2 (en) * 2017-07-14 2021-06-08 Intel Corporation Techniques for managing access to hardware accelerator memory
US10402937B2 (en) 2017-12-28 2019-09-03 Nvidia Corporation Multi-GPU frame rendering
GB2571539B (en) 2018-02-28 2020-08-19 Imagination Tech Ltd Memory interface
GB2571536B (en) * 2018-02-28 2020-03-11 Imagination Tech Ltd Coherency manager
GB2571538B (en) * 2018-02-28 2020-08-19 Imagination Tech Ltd Memory interface
WO2019246139A1 (en) 2018-06-18 2019-12-26 Flc Technology Group Inc. Method and apparatus for using a storage system as main memory
US20220114096A1 (en) 2019-03-15 2022-04-14 Intel Corporation Multi-tile Memory Management for Detecting Cross Tile Access Providing Multi-Tile Inference Scaling and Providing Page Migration
US11934342B2 (en) 2019-03-15 2024-03-19 Intel Corporation Assistance for hardware prefetch in cache access
WO2020190809A1 (en) 2019-03-15 2020-09-24 Intel Corporation Architecture for block sparse operations on a systolic array
US11861761B2 (en) 2019-11-15 2024-01-02 Intel Corporation Graphics processing unit processing and caching improvements
KR20220064230A (en) * 2020-11-11 2022-05-18 삼성전자주식회사 System, device and method for accessing memory based on multi-protocol
CN115202892B (en) * 2022-09-15 2022-12-23 粤港澳大湾区数字经济研究院(福田) Memory expansion system and memory expansion method of cryptographic coprocessor

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US4991081A (en) * 1984-10-31 1991-02-05 Texas Instruments Incorporated Cache memory addressable by both physical and virtual addresses
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Also Published As

Publication number Publication date
US8615637B2 (en) 2013-12-24
CN102576299A (en) 2012-07-11
JP2013504822A (en) 2013-02-07
JP6196445B2 (en) 2017-09-13
WO2011031969A1 (en) 2011-03-17
US20110060879A1 (en) 2011-03-10
EP2476051B1 (en) 2019-10-23
EP2476051A1 (en) 2012-07-18
KR20120060230A (en) 2012-06-11
CN102576299B (en) 2015-11-25
KR101593107B1 (en) 2016-02-11

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