IN2012DN00934A - - Google Patents

Info

Publication number
IN2012DN00934A
IN2012DN00934A IN934DEN2012A IN2012DN00934A IN 2012DN00934 A IN2012DN00934 A IN 2012DN00934A IN 934DEN2012 A IN934DEN2012 A IN 934DEN2012A IN 2012DN00934 A IN2012DN00934 A IN 2012DN00934A
Authority
IN
India
Prior art keywords
translation
page tables
guest
request
pointer
Prior art date
Application number
Other languages
English (en)
Inventor
Andrew G Kegel
Mark D Hummel
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of IN2012DN00934A publication Critical patent/IN2012DN00934A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1081—Address translation for peripheral access to main memory, e.g. direct memory access [DMA]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1009—Address translation using page tables, e.g. page table structures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1036—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] for multiple virtual address spaces, e.g. segmentation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/15—Use in a specific computing environment
    • G06F2212/151—Emulated environment, e.g. virtual machine

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
IN934DEN2012 2009-07-24 2010-07-24 IN2012DN00934A (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/508,882 US8386745B2 (en) 2009-07-24 2009-07-24 I/O memory management unit including multilevel address translation for I/O and computation offload
PCT/US2010/043169 WO2011011769A1 (fr) 2009-07-24 2010-07-24 Unité de gestion de mémoire d'entrée/sortie comprenant une transformation d'adresse à multiples niveaux pour une entrée/sortie et un transfert de charge de calcul

Publications (1)

Publication Number Publication Date
IN2012DN00934A true IN2012DN00934A (fr) 2015-04-03

Family

ID=43012690

Family Applications (1)

Application Number Title Priority Date Filing Date
IN934DEN2012 IN2012DN00934A (fr) 2009-07-24 2010-07-24

Country Status (7)

Country Link
US (1) US8386745B2 (fr)
EP (1) EP2457166B1 (fr)
JP (1) JP2013500525A (fr)
KR (1) KR101614865B1 (fr)
CN (1) CN102473139B (fr)
IN (1) IN2012DN00934A (fr)
WO (1) WO2011011769A1 (fr)

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Also Published As

Publication number Publication date
KR101614865B1 (ko) 2016-04-29
CN102473139B (zh) 2015-05-20
US8386745B2 (en) 2013-02-26
US20110023027A1 (en) 2011-01-27
EP2457166B1 (fr) 2018-08-22
WO2011011769A1 (fr) 2011-01-27
CN102473139A (zh) 2012-05-23
JP2013500525A (ja) 2013-01-07
EP2457166A1 (fr) 2012-05-30
KR20120044369A (ko) 2012-05-07

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