IN2012DN00929A - - Google Patents

Info

Publication number
IN2012DN00929A
IN2012DN00929A IN929DEN2012A IN2012DN00929A IN 2012DN00929 A IN2012DN00929 A IN 2012DN00929A IN 929DEN2012 A IN929DEN2012 A IN 929DEN2012A IN 2012DN00929 A IN2012DN00929 A IN 2012DN00929A
Authority
IN
India
Prior art keywords
threads
cpu
operating system
data
workgroups
Prior art date
Application number
Other languages
English (en)
Inventor
Laurent Morichetti
Benedict Gaster
Jayanth Gummaraju
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of IN2012DN00929A publication Critical patent/IN2012DN00929A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/3009—Thread control instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
    • G06F9/5044—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals considering hardware capabilities

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Devices For Executing Special Programs (AREA)
  • Advance Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
  • Debugging And Monitoring (AREA)
IN929DEN2012 2009-07-27 2010-07-23 IN2012DN00929A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/509,763 US9354944B2 (en) 2009-07-27 2009-07-27 Mapping processing logic having data-parallel threads across processors
PCT/US2010/043078 WO2011017026A1 (en) 2009-07-27 2010-07-23 Mapping processing logic having data parallel threads across processors

Publications (1)

Publication Number Publication Date
IN2012DN00929A true IN2012DN00929A (ko) 2015-04-03

Family

ID=42989500

Family Applications (1)

Application Number Title Priority Date Filing Date
IN929DEN2012 IN2012DN00929A (ko) 2009-07-27 2010-07-23

Country Status (8)

Country Link
US (1) US9354944B2 (ko)
EP (1) EP2460073B8 (ko)
JP (1) JP5934094B2 (ko)
KR (1) KR101759266B1 (ko)
CN (1) CN102576314B (ko)
IN (1) IN2012DN00929A (ko)
TW (1) TWI525540B (ko)
WO (1) WO2011017026A1 (ko)

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Also Published As

Publication number Publication date
KR101759266B1 (ko) 2017-07-18
KR20120054027A (ko) 2012-05-29
WO2011017026A1 (en) 2011-02-10
TWI525540B (zh) 2016-03-11
US9354944B2 (en) 2016-05-31
TW201112118A (en) 2011-04-01
JP2013500543A (ja) 2013-01-07
EP2460073B8 (en) 2018-05-16
EP2460073A1 (en) 2012-06-06
CN102576314B (zh) 2016-08-03
US20110022817A1 (en) 2011-01-27
CN102576314A (zh) 2012-07-11
EP2460073B1 (en) 2018-04-11
JP5934094B2 (ja) 2016-06-15

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