IL80038A - Raised mounting for leadless chip carrier - Google Patents

Description

RAISED MOUNTING FOR LEADLESS CHIP CARRIER q¾^¾3in 'ion q>- \» κη:> nay nnaain naam HUGHES AIRCRAFT COMPANY C:04315 RAISED MOUNTING FOR LEADLESS CHIP CARRIER FIELD OF THE INVENTION This invention is directed to the mounting of a leadless chip carrier on a printed circuit board wherein the printed circuit board is provided with raised mounting and connection pads. When the leadless chip carrier is secured thereon, it is raised above the surface of the printed circuit board to provide space for cleaning the surface of the printed circuit board below the leadless chip carrier.

BACKGROUND Integrated circuitry on semiconductor chips are housed in several varieties of carriers. These carriers provide protection for the semiconductor chips and. provide means by which the circuits of the semiconductor chip can be connected to external circuitry. One type of semiconductor holder and connector is the leadless chip carrier. This is a square or rectangular structure having gold connections around the external edges and tinning and extending underneath the carrier. These areas are for solder connection to a printed circuit board .

A printed circuit board is prepared having connecting pads thereon which are positioned to face the pads on the leadless chip carrier. The pads on the 80038/ 2 printed circuit board are plated with tin-lead solder, the leadless chip carrier is put in place and soldering between the pads is accomplished in a vapor phase soldering tank. Vapor phase soldering is a mass process approach and is preferred to minimize the time and temperature to which the semiconductor chip within the chip carrier is subjected. Flux is present during soldering to provide conditions under which the soldering is reliable.

U.S. Patent No. 3 , 429 , 040 discloses a method of joining a microminiature circuit component to a supporting dielectric substrate. According to the method, an electrically conductive pattern and conducting connecting areas are applied to a substrate. The connecting areas may be in the form of solder wettable dots applied to the conductive pattern or solder wettable connecting areas, to which solder is applied. Solder applied adheres only to the connecting areas, and not to the remaining portions of the conductive pattern. A microminiature component having solder ball contacts connected thereto is gently pushed onto the substrate and heated, so that a unified solder mass is formed by each solder ball together with the solder from the corresponding connecting area.

U.S. Patent No. 3 . 770 . 874 is concerned with a contact member for soldering electrical components. Each contact member is composed of a relatively inert, electrically conductive metal and comprises at least two generally equal geometric areas interconnected by a narrow bridge area. The contact member may be bonded to a non-conductive substrate so that upon application of a liquid solder, substantially identical, relatively thick solder domes or hemispheres form on each of the geometric areas and a relatively thin solder layer forms on the bridge area. An electrical component is positioned in working relation with a contact area and localized heat is applied to the corresponding solder dome to form a bond between the contact area and the solder. A particular feature of the device is the division of the contact member into a plurality of interconnected areas, which provides an effective control of heat applied to each such area.

U.S. Patent No. 3 . 781 . 596 discloses a chip carrier comprising a flexible polymeric film base with a conductor pattern formed thereon. Small raised pads are disposed on the inner ends of the conductor pattern to facilitate chip attachment thereto. The pads may be made of the same material as that of the conductor pattern and may be coated with a layer of another material such as copper, gold, nickel, or nickel/boron. Alternatively, the pads may be made of solder. Chips may be bonded to the chip carrier by ultrasonic or thermocompression methods .

U.S. Patent No. 4 , 413 , 309 discloses a printed circuit board having raised lands for leadless elements and lands with piercing holes for elements with leads. Each land for an element with leads is connected by means of a leader pattern to at least one land for a leadless element. Before permanently mounting elements onto the board, the leadless elements are temporarily 80038/1 mounted by means of an adhesive resin and the elements with leads are temporarily mounted by means of the lead wires which are inserted into the piercing holes. Through a solder dipping operation, melted solder is led from the land for an element with lead, where evaporated gas or air may escape through the piercing hole, through the leader pattern to a land for a leadless element, where the gas or air is apt to stay.

U.S. Patent No. 4,572,925 is concerned with a method of manufacturing a printed circuit board having a solderable plating finish. According to the method, a first layer of copper is coated on each of the two faces of a printed circuit board substrate. A second layer of copper is plated over each first layer and over the wall of each hole extending through the substrate. Then, by using a photo-resist pattern, discrete portions of the copper areas are plated with a thin nickel alloy layer. The portions of the copper layers not protected by the nickel alloy layer are etched away, thereby defining tracks and pads. The nickel alloy layer is then copper plated, and finally coated with a tin-lead alloy layer. The final copper layer provides improved solderability of areas of the circuit board to which elements are to be soldered.

U.S. Patent No. 3,699,011 discloses a method of producing thin film integrated circuits. According to the method, a metal layer, an insulator layer, and a metal layer are formed on an insulator substrate. The third and second layers may be partially removed by photoetching techniques to form a plurality of thin film elements. This method is, however, not suitable for mounting a chip carrier having bottom I/O attach pads thereon upon a printed circuit board.

U.S. Patent No. 4,220,810 discloses a printed wiring board which includes an insulator base board with a thin layer of solder resist coated thereon. The solder resist coats the entire surface of the board, except at a raised land to be printed or between adjacent lands to be soldered. A portion of the solder resist is raised so that a ridge is formed around the periphery of the land, the ridge being elevated above the land. The ridge prevents solder bridging that often takes place with conventional printed wiring boards.

U.S. Patent No. 4,081,601 is concerned with a conductive overlay for a circuit board which is to be solder-bonded to the contact finger of a circuit pattern. The overlay includes a copper base layer, onto one side of which is bonded a gold plated nickel layer, and onto the other side of which a solder layer bonds the overlay to the copper base of the contact finger.

French Patent No. 2,479.639 discloses a process for mounting an electronic component onto a substrate. According to the process, there is provided a substrate having circuit tracks or copper metallization printed thereon. An electronic component is supported in spaced relationship to the substrate by soldering -2a- 80038/1 its connector leads to appropriate bridges, secured in electrical contact with the copper tracks. The relevant portion of the substrate is covered with resist, the bridges are deposited, and the resist is then removed. A globule of paste or the like flexibly supports the middle of the component on the substrate and acts as a heat conductor. This mounting allows flexing and expansion/contraction of the substrate without damaging the component solder joints.

U.S. Patent No. 4,075.^16 discloses a method for making an electronic thin film circuit unit. According to the method, a valve metal layer is metallized on an insulating substrate by sputtering on two layers of copper separated by an intermediate layer of iron, nickel, or cobalt. The combined circuit and component pattern is etched out, the metallization over the resistance components of the circuit is selectively etched away, and electroless deposited nickel and gold layers are successively applied to the remaining metallization and a solder layer is then applied on top by contact with liquid solder.

A disadvantage of the processes of the prior art is that, after soldering between the pads is accomplished, the flux must be cleaned away because most flux is detrimental to the long life of the printed circuit board. Since the leadless chip carrier is secured down pad-to-pad on the printed circuit board, there is little space therebetween for the washing out of the flux therebetween. Thus, there is need for provision which can accomplish the cleaning of the space on the printed circuit board below the leadless chip carrier.

SUMMARY In order to aid in the understanding of this invention, it can be stated in essentially summary form that it is directed to a raised mounting for a leadless chip carrier on a printed circuit board. The raised mounting is accomplished by providing a series of raised pads at each of the contact points of the leadless chip carrier so that when the leadless chip carrier is soldered in place for mechanical security and electrical connection, there is sufficient space between the leadless chip carrier and the printed circuit board therebelow.

It is, thus, a purpose and advantage of the present invention to provide a method and apparatus for mounting a lead less chip carrier upon a printed circuit board in such a manner as to provide space therebetween for -2b- cleaning of the area between the leadless chip carrier and the printed circuit board.

It is a further purpose and advantage of this invention to provide non-wettable circuit traces so that solder is confined only to the attachment pads to prevent molten solder from flowing away from the attachment pad area down the circuit trace into the vias which would reduce the amount of solder available for attachment and fillet formation.

It is a further purpose and advantage of this invention to provide raised pads which are of an electrical conductor having a melting point higher than the solder by which the leadless chip carrier is secured and connected in place so that the pads hold the leadless chip carrier spaced from the printed circuit board.

Other purposes and advantages of this inven tion will become apparent from a study of the following portion of this specification, the claims and the attached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS FIGURE 1 is an isometric view of a leadless chip carrier positioned above a printed circuit board, of which parts are broken away, just prior to attachment of the printed circuit board.

FIGURE 2 is an enlarged section through a portion of the printed circuit board showing the first step in creating the circuit traces and raised mounting in accordance with this invention.

FIGURE 3 is a view similar to FIGURE 2 showing the second step in producing the circuit traces and raised mounting in accordance with this invention. 4 FIGURE 4 is a view similar to FIGURE 3 showing the third step in producing the circuit traces and raised mounting in accordance with this invention.

FIGURE 5 is an enlarged section taken generally along the line 5-5 showing the completed raised mounting and circuit traces in accordance with this invention.

FIGURE 6 is a view similar to FIGURE 5 and further showing the leadless chip carrier soldered in place on the raised mounting pad.

DESCRIPTION OF THE PREFERRED EMBODIMENT Leadless chip carrier 10 is shown in FIGURES 1 and 6. It is of the conventional rectangular solid shape. All four of the edges and the adjacent bottom surface carry I/O attach pads which are internally connected to the semiconductor chip positioned within and protected by the leadless chip carrier 10. The near edges 12 and 14 carry such I/O attach pads thereon. I/O attach pads 16 and 18 are illustrated in a series of such I/O attach pads on the edge 12, while I/O attach pads 20 and 22 are particularly pointed out in the series along edge 14. As is seen in dotted lines in FIGURE 1 and as is seen with respect to I/O attach pad 18 in FIGURE 6, the I/O attach pads extend for a short distance beneath the body of chip carrier 10, along the bottom surface 24. The I/O attach pads on the chip carrier 10 carry a solder coating thereon so that the solder can readily join with other solders to provide a secure mechanical and electrical joint.

Printed circuit board 26 carries a plurality of pads thereon. The pads on the printed circuit board are electroplated tin-lead pads which are positioned to be in exact alignment with the I/O attach pads on the bottom of chip carrier 10. As a particular example, . 80038/2 contact pads 28 and 30 are particularly indicated as being in alignment with I/O attach pads 16 and 18, and contact pads 32 and 34 are illustrated as being in alignment with the I/O attach pads 20 and 22. The contact pads on the printed circuit board are connected to supply voltage to or take signal from the leadless chip carrier 10, in accordance with the particular circuitry requirements. A circuit trace is formed on the printed circuit board for each contact pad, and some of these circuit traces are connected through the printed circuit board to internal circuitry traces or circuit traces on the other side thereof. For example, circuit . trace 36 connects pad 30 to a via 38 which extends through the board. The manner in which the contact pads, circuit traces and vias are built up is given by the example of pad 30, circuit trace 36 and via 38, which are shown in FIGURES 2 through 5.

FIGURE 2 shows the board 40 which is of dielectric material and is easily workable. A polyimide-f iberglass board has good temperature resistance and mechanical properties. Epoxy materials are also useful but are not preferable for best life. While the raised mounting system of this invention can be used on single- or double-sided boards, it is particularly useful where there -are many such chip carriers. More circuit traces are required to accomplish the desired multiple circuitry and, as a consequence, the raised mounting in accordance with this invention is used on a multilayered board.

Lamina 39 and 41 shown in FIGURE 2 represent intermediate levels of circuit traces within the multilayered board. Holes are formed in the board wherever through connections are desired between circuit traces on the several layers. Hole 42 is provided for that purpose. On the top and bottom of board 40 the first layer is copper layer 43 which is the original foil cladding on the board. Holes are drilled through the copper foil layer 43 and through the board 40, sometimes passing through connection pads on the interior circuit traces within the board, as indicated in FIGURE 2. The holes are desmeared, cleaned and the dielectric material is undercut to provide access to the interior contact pads. Copper is plated all over to provide copper-plated layer 44 which has a minimum copper thickness of 0.001 inch through the holes.

A conventional photoresist is applied to the surface on the overall copper-plated layer 44 and is exposed both top and bottom to define the connection pads and circuit traces. When the photoresist is properly exposed and developed, a nickel pattern image layer 46 is plated thereon. This nickel layer defines the circuit traces and pads shown in FIGURE 1. This stage of the production is shown in FIGURE 3. Nickel layer 46 also extends through the hole 42 to form via 38. The nickel layer 46 should be about 0.0005 inch to 0.001 inch in thickness. The nickel serves to protect the copper against oxidation acts as a copper etch resist image and provides a surface which is not wetted with conventional tin-lead solder.

After the nickel plating step, the structure is again -masked to leave exposed the connection pad areas and copper pad 48 is built up, in thickness and position to form pad 30. The copper layer 48 is about 0.002 to 0.003 inch thick, depending on clearance desired. Tin-lead is then deposited upon copper pad 48, preferably by electroplating or other application. Solder layer 50 is about 0.002 to 0.003 inch thick, depending on the solder needed in the joint. The solder is compatible with the solder wetting of the I/O attach pads on the leadless chip carrier. After deposition of the solder layer 50, the raised pad becomes attachment pad 30. 7 Thereupon, the built-up structure is masked in appropriate areas of the printed circuit board and all external copper which is not covered with nickel, solder or mask is etched away to define the individual traces. The copper foil layer 43 and copper plate layer 44 have been maintained up to this point to provide electrical continuity for the plating of the nickel layer, the copper pad layer, and the solder pad layer. The finished assembly is shown in FIGURE 5 where the mounting pads are raised and the circuit traces are electrically independent.

The next step is to attach the leadless chip carrier 10. The surfaces are cleaned and fluxed, and the leadless chip carrier is put in place with the I/O attach pads on the chip carrier in alignment with the raised mounting pads on the printed circuit board. Soldering is then accomplished by vapor-phased soldering. The solder layer 50 is melted and joins with the solder layer on the pads in the chip carrier. A fillet 52 is formed, see FIGURE 6. The relatively thick solder layer 50 accommodates for irregularities in height and provides sufficient material for forming a generous fillet 52 which aids in inspection and reliability.

It is significant to reliable attachment that the nickel connection trace 46 adjacent the raised pad is not wettable by solder. This means that all of the solder in pad 50 in FIGURES 4 and 5 goes into the fillet 52 in FIGURE 6. The nickel-covered circuit trace 36 is not wet by the solder, and thus the solder does not run down the circuit trace into the via 38.

The full fillet 52 permits inspection, so that long life attachment is assured.

The result is the positioning of the leadless chip carrier 10 above the top surface 54 of the printed circuit board and above the top surface of the circuit 8 traces thereon. This provides a space, illustrated in FIGURE 6, through which solvent can be flushed to wash flux out of that space under the leadless chip carrier and between adjacent nickel-plated circuit traces.

Thus, there is no hidden space underneath the leadless chip carrier which resists cleaning.

The same technique works for other types of attachment, although the solder layer 50 need not be as thick. When attaching leaded chip carriers, flat packs hybrids, resistors, capacitors, and gate arrays, by reflow soldering, a solder layer 50 need only be about 0.001 inch thick.

This invention has been described in its presently contemplated best mode, and it is clear that it is susceptible to numerous modifications, modes and embodiments within the ability of those skilled in the art and without the exercise of the inventive faculty. Accordingly, the scope of this invention is defined by the scope of the following claims. 80038/4

Claims (10)

1. The method of mounting a chip carrier having bottom I/O attach pads thereon upon a printed circuit board comprising the steps of: forming a pattern of circuit traces on the top surface of the printed circuit board, with the traces having pads thereon corresponding in position to the I/O attach pads on the chip carrier; depositing electrically conductive, solder-wettable, pad-raising material on the pads so that the top of the pad-raising material is above the level of the traces on the board; depositing attachment and connecting material including solder on the top of the pad-raising material so that a chip carrier can be placed thereon and secured and connected by the solder, the solder being of a lower melting point than the pad-raising material; attaching a chip carrier to the pads by joining the attachment material on the pads to at least some of the I/O attach pads on the bottom of the chip carrier; and cleaning the space between the chip carrier and printed circuit board by passing solvent through the space therebetween.

2. The method of claim 1 further including the subsequent step of securing and connecting a chip carrier to the printed circuit board with the bottom of the chip carrier spaced from the printed circuit board by spacing provided by the pad-raising material. 9 80038/3

3. The method of claim 1, wherein said attachment and connecting material includes: a layer of non-solder wettable material coated on the top of the circuit traces; and solder deposited on the top of the pads adjacent the traces; the chip carrier being secured and connected onto the pads by means of reflow soldering utilizing the solder coated on the pads, with the circuit traces rejecting the solder to prevent solder flow away from the pads along the circuit trace.

4. The method of claim 3. further including the intermediate step of depositing a layer of solder wettable material on the pads on the solder non-wettable material and prior to coating, solder onto the pads .

5. A printed circuit board for the mounting of a chip carrier thereon, with the chip carrier having I/O attach pads on the bottom thereof, said printed circuit board comprising: a dielectric board having a top surface; a plurality of circuit traces patterned on said top surface, said circuit traces having pads connected thereto which correspond in position to the I/O attach pads on the bottom of the chip carrier; solder-wettable , pad-raising material on the top of said pads and extending above the level of said patterned circuit traces on said top surface of said board so that when a chip carrier is soldered to said pad-raising material, the bottom of 10 80038/3 the chip carrier is above the circuit traces on said board; wherein there is a layer of solder deposited on said pad-raising material which is copper so that a chip carrier can be soldered thereto.

6. The printed circuit board of claim 5 wherein a layer of non-solder-wettable material is deposited over said circuit traces on the top of said printed circuit board and said pad-raising material is deposited on said pads above said non-solder-wettable material .

7. The printed circuit board of claim 5 further including an electrically connecting via through said printed circuit board.

8. The printed circuit board of claim 6 wherein there is a copper layer on said board beneath said non-solder-wettable circuit traces and there is a copper layer on said pads beneath said solder layer on said pads.

9. · The printed circuit board of claim 8 wherein said copper circuit trace layer and said non-solder-wettable circuit trace layer both extend under said copper pad layer.

10. The printed circuit board of claim 6 wherein said non-solder-wettable material contains nickel. For the Applicants , S Sanford T. Colb & Co. C: 0^315 11