IL50959A - Voltage adapting arrangements between switching units of switch circuit series and outer circuits - Google Patents

Description

Vw ain»D ηττπ' 7»a πηο ηοκηπ »·η*ιο D»»aTX»n o' ayDi ain»a nine Voltage adapting arrangements between switching units of switch circuit series and outer circuits SIEMENS AKTIENGESELLSCHAFT C. 48213 •This invention relates to a circuit arrangement for connecting switching units of switch circuit series, «. especially switch circuit series in TTL-technique , supplied by a first supply potential, with other circuits which are connected to a second supply potential of opposite polarity and, particularly, of greater magnitude than the first.

Furthermore, such a circuit arrangement can be utilized, for example, for switch circuits of switch circuit series in DTL-or LSL-technique (diodes-transistor-logic or slow interference protected logic) .

From pages 168 to 172 of the 1966 Siemens Journal it is already known how to provide a switch circuit system with adaptation circuits which produce the transition to external circuits. In part, these adaptation circuits are based on the fact that several supply voltages are available. In a contact monitoring input member provision is made for the contact to be joined to negative voltage.

However, there are applications in which one connection of switches provided for contact making purposes is connected to zero potential and their other connection is connected to negative supply voltage by way of a resistor.

Furthermore, it can occur that only one additional supply voltage is available apart from the supply voltage for-the TTL-switch circuits (transistor-transistor-logic circuits) . Moreover, it may become necessary to operate switches with the assistance of the output signals of TTL-swit.ch circuits which switch a load connected to the negative supply voltage to zero potential.

It is therefore the task of the invention to develop a circuit arrangement as described in detail above which allows for the simplest possible operation of TTL-switching circuits in connection with circuits which a supply potential of opposite polarity to that of the supply^ potential required for the switching circuits.

In accordance with the invention the circuit arrangement for solving this task is designed so that, at the transition from the TTL-switch unit to the circuit there is provided a level converter wherein the TTL-switch unit is connected to the base of a pnp-transistor whose emitter is connected to zero potential, by way of a series circuit of at least two diodes connected in pass direction, or by way of a zener diode of opposite polarity the base of said pnp-transistor being connected by way of a resistor_to _the_second supply .potential (-2 V) or some other supply potential of the same polarity, and the collector of said pnp-transistor also being connected by way of the ballast -resistance so the second supply potential. This measure results in a particularly easily realized method of safely performing the desired level adaptation.

In further development of the invention the circuit arrangement is designed so that there is provided at the transition from the circuit to the TTL-switching unit a further level converter in which there is arranged between the second supply potential and the first supply potential or another supply potential of the same polarity, a voltage divider consisting of three series-connected branches which is connected with its tap, arranged on the side of the first supply potential, to zero potential by way of a switch, and with its tap, arranged on the side of the first supply potential, to the base of an npn-transistor whose emitter is connected to zero potential, and with its collector to the following TTL-switching unit.

In further development of the invention the circuit arrangement is constructed so that the npn-transistor of the further level converter and the pnp-transistor of the level converter, whose emitters are connected with one another, are united to form a bistable tilting step due to the fact that the the npn-transistor is connected to the base of by way of the diodes, and that the base of the is connected to the collector of the pnp-transistor by way of the centre one of the three resistors of the voltage divider, and that the collector of the npn-transistor is connected by way of a resistor to the first supply potential or to some other positive supply potential. By this method there is provided in advantageous manner a bistable tilting step which can be provided simultaneously in particularly simple manner by way of one and the same line with control from a contact connected to zero potential, and with an indicating element which is connected to a negative supply voltage for the purpose of indicating the switch condition. Moreover, the switch condition can also be evaluated by a TTL- switch circuit arranged next on the output side. - In further development of the invention it is particularly simple to provide mutually balanced erasing inputs for the tilting step, in that there is joined to the point of connection of the two diodes at least one of the pnp-transistor .

Another development of the invention is ^ characterized by the arrangement of at least one bistable tilting step with simultaneously conducting or blocking complementary transistors in a circuit arrangement for storing and issuing signals wherein an electronic section and a combined control and indicating section are arranged in structural units which are physically separated from each other and which are connected with one another by connecting lines, especially for devices used for monitoring and/or controlling from a distance, · such, that the electronic section is furnished with at least one bistable tilting step wherein the collector of one transistor is linked by the connecting line to the terminal of an indicator element with a control impulse source, said terminal being situated in the control and indicating section. The control impulse source can be in the form of a non-engaging key or of an electronic contact. As a result of these measures there is created a circuit arrangement which permits construction of the electronic section for the largest possible number of signals and/or instructions, without creating difficulties in arranging the control lines which connect the control and indicating section with the electronic section. Furthermore, the amount of connecting lines required between the structural units of the remote control or remote monitoring device is greatly reduced,, so that a particularly compact construction represents a further advantage of the invention.

In further development of the invention the circuit arrangement is developed so that in at least two of the erasing signal transmitter. In this regard it is useful to employ an erasing signal transmitter in the form of a ^ transistor whose emitter is connected to the first supply voltage and, by way of a resistor, to the base which is, connected, by way of a further resistor and a control line joined thereto, to an eraser key joined to zero potential. These measures provide an advantageous means of carrying out a combined erasure of several tilt steps by way of one and the same control line.

In further development of the invention the circuit arrangement is designed so that a connection of the voltage divider is conducted from at least two of the tilt steps to the second supply potential by way of a common diode. These measures provide an advantageous means of preventing that a voltage failure in the electronic section results in an incorrect signal in the indicating field.

In addition it is possible to achieve a mutual blocking of two tilt steps in that a TTL-rswitch circuit on the output side is developed as a negating member and in that the output of at least one of the negating members is connected to one of the additional diodes of a tilt step other than that on the input side. This measure provides protection against storage of contradictory switch conditions when double instructions are being stored.

The invention is now described in detail with reference to the embodiments illustrated in Figures 1 to 4, wherein: Figure 1 is a TTL-switch circuit with a first level converter on the output side, Figure 2 is a TTL-switch circuit with a level converter on the input side, I Figure 3 is a bistable tilting step which is formed by level converters, Figure 4 is a circuit arrangement with two bistable tilting steps.

Figure 1 illustrates a circuit arrangement wherein the output of a TTL-switch circuit G2 controls with the aid of a second level converter a load which is connected to negative supply voltage. By using this type of circuit it is possible by means of TTL-switch circuits to connect external consumers, for example lamps, which are supplied with -24 V, for instance.

The output of TTL-switch circuit G2 is conducted to the base of the pnp-transistor Ts2 by way of diodes D1 , D2 which are arranged in series and poled in pass direction, the base of pnp-translstor Ts2 being connected with the second supply potential -24 V via resistor 5. The emitter of pnp-transistor Ts2 is connected directly to zero potential. The collector of transistor Ts2 is connected to the second supply potential -24 V by way of a consumer in the form of an indicator lamp L.

In the inoperative state log 1, i.e., positive potential, is available at the output of TTL-switch circuit G2. As a result, the current flowing by way of resistor R5 is conducted away via diodes Dl and D2, and the base of transistor Ts2 becomes positive to the extent that transistor Ts2 is blocked.

If TTL-switch circuit G2 switches its output to log 0, which corresponds to a voltage of 0 V or, respectively, to a voltage U^+0.4 V, then the current which flows via resistor R5 and which is the result of the threshold voltages of the two diodes can no longer flow from gate G2 or, respectively, the TTL-switch circuit, but must flow through the base of the pnp-transistor Ts2, thereby switching it into the pass positio^ Figure 2 represents a circuit arrangement in which it is possible with the aid of a first level converter to approach a TTL-switch circuit via a switch which is connected to zero potential or ground, and which may also be an electronic switch. It is possible with this type of circuit to evaluate with the aid of TTL-units which are supplied with +5 V, signals of sources, particularly pnp-transistors, which are waiting for a consuming device connected to -24 V.

Switch S of which one pole is connected to mass or zero potential, is connected to the second supply potential -24 V by way of resistor Rl. E identifies the contact point of switch S with resistor Rl and respresents the input of the level converter.

By way of resistor R2 and resistor R3» arranged in series to the former, input E is connected to the first supply potential +5 V, so that between the first and the second supply potential there is arranged a voltage divider consisting of 3 resistors. The tap of the voltage divider, or the point of connection of resistors R2 and R≥ respectively, is connected to the base of the npn-transistor Tsl whose emitter is directly connected to zero potential, while its collector is connected to the first supply potential +5 V via resistor R4 and also to the input of the TTL-switch circuit Gl. The tap of the voltage divider which is situated on the side of the second supply potential -24 V also forms the input E of the level converter.

The current branch with resistor R4 can be left out of the level converter if it is not opposed by the operating data of the switch circuit Gl. In the rest condition switch S - or, respectively, the pnp-transistor by which it is replaced in accordance with the circuit section drawn in broken line - is opened. This results in the formation of a negative voltage at input E of a little less than 24 V. Resistors R2 and R3 are dimensioned such that in this case the base of transistor Tsl^^ is negative to the extent of blocking transistor Tsl, and that, as a result, log 1 is available at the input of the following TTL-switch circuit.

When switch S is closed and ground potential is applied to input E, the potential at the base of transistor Tsl becomes positive to the extent that transistor Tsl becomes conducting and, as a result, log 0 becomes available at the input of the following TTL-switch circuit.

Figure 3 illustrates a circuit arrangement wherein the feedback connection of_a first and a second level converter is arranged so that the two level converters from a bistable tilting step. The emitter of the pnp-transistor Ts20 and the emitter of the npn-transistor TslO are both connected directly to mass. The collector of transistor TslO, which is connected to the first supply potential +5 V via resistor RIO, is connected with the base of transistor Ts20 by way of diodes D20 and DIO which are arranged in series and poled in pass direction. The base of said transistor Ts20 is connected to the second supply potential -24 V via resistor R9. The collector of transistor Ts20 is connected v res s or . e ase o transistor TslO is connected, on the one hand, to ground via capacitor C and, on the other, to potential +5 V via resistor R8. . \ The collector of transistor Ts20 forms an input El of the bistable tilting step which is applied to ground upon activation of switch T. In addition, the input to El, which also functions as output for the indicating element, is connected to potential -24 V via an indicator lamp L.

TTL-switch circui G3 which forms the other output A of the tilting step is connected to the collector of transistor TslO. The additional diodes D30 and D40 are connected at the point of contact of diodes DlO and D20 with such a polarity that they are switched in series in the same direction as diode DlO. The free connections of diodes D30 and D40 provide the erasing inputs E2 and E3 of the tilting step.

In the inoperative condition input E is connected to -24 V via lamp L and resistor R6; this produces a negative voltage E at the input which is somewhat less than 24 V. As a result of the dimensioning of resistors R7 and R8 the base of transistor Tsl is negative to the extent that transistor Tsl is blocked in this particular instance. A current then flows from the infeed of the first supply potential +5V to the infeed of the second supply potential -24 V via resistor RIO, diodes D20, DlO and resistor R9. The resistor RIO is dimensioned so that when considering all tolerances a voltage U = + 2.4 V is available at output A to secure log 1 for the following TTL-input . Thus, as a result of the additional flow via Diodes D20 and D10, the base of transistor Ts20 is posi ive to the degree necessary to ensure blocking of transistor Ts20.

If as a result of depressing key T zero potential or mass is made available at input El for a short period, then the potential at the base of transistor TslO becomes sufficiently positive to render transistor TslO conductive.

As a result , the voltage at output A jumps from U = +2.4 V to the value of 0 V or ^+ 0.4 V and conducts log O to the following TTL-input. In this particular instance, no further current can flow through diodes D20 and D10 because of the two threshold voltages of diodes D20 and D10. The current which flows via resistor R9 to the feed line of the second supply potential -24 V now comes from the base of transistor Ts20 and switches transistor Ts20 into pass position. As a result, the switch condition remains unaltered, i.e., transistors Tsl and Ts2 remain in the pass position even after the key has been released. The current for lamp L then flows via transistor Ts20.

The tilting step is erased by applying a positive voltage corresponding to a log 1 in the order from +2.4 V to + 5 V at one of the two erasure inputs E2 and E3. As a result the potential at the base of the transistor Ts2 becomes positive, transistor Ts2 is blocked, the voltage at input E becomes negative, transistor Tsl is also blocked, and the above described inoperative condition is re-established.

The switching arrangement is protected against interfering pulses by the low pass characteristic of the RC-member which is formed by resistor R7 and capacitor C and by a minimum operating current required for activating the input potential available at input El, said minimum "^- operating current being determined by resistors R7 and R8.

Figure 4 illustrates part of an arrangement for remote control or remote monitoring of telecommunication networks or such like. The electronic section of a remote control device and the control desk or, respectively, the controlling instruments are accommodated at a distance from each other and are interconnected by control lines.

TTL-circuits are employed within the device as shown by the exemplary- circuits Gil—G2i~r ~" Thus, the electronic section of a remote control centre can be accommodated in a rack, while the station, command and control keys Tl and T2 with the respective indicating lamps are arranged in a control desk. If one of the non-engaging keys Tl, T2 are operated then the input tilting step Kl or, respectively, K2 is adjusted in the electronic section, and the store condition is indicated in lamps LI, L2 which are coordinated to keys Tl, T2. Each key requires only a single line to adjust the tilting step and to signal back the condition of the store.

The remote control arrangement operates with double instructions requiring two instruction keys Tl, T2, namely one for switching on and one for switching off. It is expedient in this case that each two correlated input tilting steps should always mutually block each other.

The above described tilting step is arranged for connection to switching circuits in TTL-technique (transistor-transistor-logic). But, alternatively, it can be dimensioned so that it can be directly connected to switch circuits from other switch circuit series, for instance in DTL- (diodes- .

The Figure illustrates the circuit arrangement with two bistable tilting steps Kl and K2 which are assembled accordance with Figure 3.

The emitter of the pnp-transistor Tsl2 and the emitter of the npn-transistor Tsll are both directly connected to ground. The collector of transistor Tsll, which is connected to the first supply potential +5 via resistor Rl4, is connected to the base of transistor Tsl2 by way of the two diodes D12 and Dll which are arranged in series and poled in pass direction. The base of transistor Tsl2 is connected to the second supply" potent ial -24 V by way~~of resistor R15. The collector of transistor Tsl2 is connected to the potential -24 V via resistor Rll and diode Dx, and is conducted to the base of transistor Tsll via resistor R12, said base being connected via capacitor Cl to ground,on the one hand, and, on the other, to the potential +5 V via resistor R13 The collector of transistor Tsl2 forms an input Ell of the bistable tilting step Kl which, upon operation of switch Tl, is -connected to9round. in addition input Ell is connected to the potential -24 V via the indicating lamp Ll.

The TTL-switch circuit Gil is connected to the collector of transistor Tsll which forms the output of the tilting step Kl. At the point of connection of diodes Dll and D12 additional diodes D13 and D14, of a polarity which ensures their being arranged in series in the same direction with diode Dll, are connected.

At the tilting step Kl or, respectively, K2 a feedback connection of a first and second level converter is tilting step.

Ih a first level converter key Tl which is con- nected to groundor zero potential with one pole, is connect^ with the second supply potential -24 V via resistor Rll. ' The junction of key Tl and resistor Rll forms the input. Ell of the level converter.

The input Ell is connected to the first supply potential +5 V via resistor R12 and resistor R13, arranged in series to the former, so that there is arranged between the first and the second supply potential a voltage divider consisting of the three resistors Rll ... Rl3. The tap of the voltage divider which is situated on the side of the first supply potential +5 V is connected to the base of the npn-transistor Tsll whose emitter is directly connected to zero potential and whose collector is connected to the first supply potential +5 V by way of resistor R14 and also to the input of the TTL-switch circuit Gil. The tap which is situated on the side of the second supply potential -24V functions also as input Ell of the level converter.

If the key Tl is opened and the tilting step Kl is not steady a negative voltage of slightly less than 24V occurs at input Ell. Resistors Rl2 and R13 are dimensioned such that in this particular case the base of transistor Tsll is sufficiently negative to block transistor Tsll resulting in- the availability of log 1 at the input of the following TTL-switch circuit Gil.

If key Tl is closed, resulting in the application of groundat input Ell, then tilting step Kl becomes steady. The potential at the base of transistor Tsll then becomes sufficiently positive to render transistor Tsll as a result of which log 0 becomes available at the input of the following TTL-switch circuit.

The second level converter is arranged between the input of the TTL-switch circuit Gil and the lamp LI which is connected to the negative supply voltage -24V. The input of the TTL-switch circuit Gil is connected to the base of pnp-transistor Tsl2 via diodes D12, Dll which are arranged in series and poled in pass direction, and in turn, the base of -said transistor-is-connected^-with-the=second-supply- -potent al"- -24V via resistor R15. The emitter of pnp-transistor Tsl2 is directly connected with zero' potential . The collector of transistor Tsl2 is connected to the second supply potential -24V via indicating lamp 21.

Log 1, i.e. positive potential, is available at the input of the TTL-switch circuit Gil in the inoperative condition. As a result, the current flowing through resistor R15 is conducted away via the diodes D12 and Dll, and the base of transistor Tsl2 becomes sufficiently positive to block transistor Tsl2.

If log 0 is available at the input of the TTL- switch circuit Gil, which corresponds to a voltage of 0 V or, respectively, The following working method applies to the tilting step Kl: In the inoperative state the input Ell is connected to -24 V via lamp LI and resistor Rll. This results in the . , - of resistors R12 and R13, the base of transistor Tsll is sufficiently negative to block transistor Tsll. This causes a flow of current from the feed line of the first supply potential +5 V via resistor R14, diodes D12, Dll and resistor R15 to the feed line of the second supply potential -24 V. Resistor R14 is dimensioned such that, keeping in mind all tolerances, a voltage U = + 2.4 is available at the collector of transistor Tsll in order to ensure the availability of log 1 for the following TTL-input. As a result of this the base of transistor Tsl2 is, in addition, rendered sufficiently positive to ensure the blocking of transistor Tsl2.

When by depressing key Tl zero potential or, respectively .ground is briefly connected to input Ell, then the potential at the base of transistor Tsll becomes sufficiently positive to render transistor Tsll conductive. As a result, the voltage at the collector of transistor Tsll jumps from U = + 2.4 V to 0 V or, respectively, to ^+ 0.4 V and places log 0 at the following TTL-input. In this case, no more current can flow through diodes D12 and Dll because of the threshold voltages of these diodes. The current which flows to the supply line of the second supply potential -24 V via resistor R15 is now derived from the base of transistor Tsl2 which is connected through. As a- result, the switch condition is rendered self-holding, i.e., transistors Tsll and Tsl2 remain conductive even when key Tl is released. The current for lamp Ll then flows via transistor Tsl2.

The tilting step is erased by applying to one of the two diodes D13, D14 a positive voltage of the magnitude of + 2.4 V to + 5 V which is appro ima ely equal to log 1. ^ As a result, the potential at the base of transistor Tsl2 becomes positive, transistor Tsl2 is blocked, the voltage at input Ell becomes negative, transistor Tsll is also blocked' and the above described inoperative condition is re-established.

The switch arrangement is protected from interference pulses by the low pass quality of the RC-member which consists of the resistor R12 and the capacitor Cl, and by a minimum operating current, determined by resistors R12 and R13, which is required _t activate the input potential, which, is available at input a2.

Tilting step K2 is of the same structure as tilt step Kl. Corresponding switching components of the two tilt steps Kl and K2 are furnished with reference numerals in the drawings which only differ from each other by the first numeral - "1" in the first tilt step and "2" in the second tilt step.

The two keys Tl and T2 are provided for the instructions on/off. Provision is therefore made for the input tilt steps Kl and K2 of the electronic section to mutually block each other. The collector of transistor Tsll is connected to the diode 24 of the second tilt step K2 via negation member Gil. The collector of transistor Ts21 is connected to diode D14 via negation member G21. This arrangement results in a mutual blocking of the tilt steps Kl and K2.

Tilt steps Kl and K2 are blocked in the inoperative state. By depressing the instruction key Tl, which issues the instruction "on", the tilt step Kl is rendered conductive. By depressing the other instruction key T2, which issues the instruction "off", tilt step K2 is rendered conductive. As a G21 and provides log 1 at the output A2 of the circuit G21. This potential of U = + 2.4 V is connected by way of diodes D14 and Dll to the base of pnp-transistor Tsl2 of the tiult step Kl and blocks the latter.

When tilt step Kl is rendered conductive by depressing instruction key Tl, the output of switch circuit Gil jumps from 0 V to a potential U = + 2.4 V, blocking the tilt step K2 via diodes D 24, D21. Tilt step Kl is blocked in corresponding manner from the negating TTL-switch circuit G21 via diodes D14 and Dll, thereby resulting in a mutual blocking of the two tilt steps Kl and K2.

The circuit arrangement is also furnished with a common erasing circuit for all input tilt steps of the electronic section, of which only tilt steps Kl and K2 are illustrated in the drawing. Diodes D13 and D23 are connected to the collector of transistor Ts3. The emitter of transistor Ts3 is connected to the first supply potential +5 V". The base of transistor Ts3 is connected to the tap of the voltage divider formed by resistors R35 and R36, which is connected on one side to the first supply potential +5 V and, on the other side, via erasing key T3 to ground diring erasing . When transistor Ts3 is switched through all tilt steps Kl, K2 etc., are erased by the application of a positive voltage or, respectively, U = +5 V, through diodes D13, Dll and D23.

Resistors Rll and R21 are connected to a voltage rail which is connected to the second supply potential -24V through diode Dx which is poled in forward direction.

Diode Dx prevents the pnp-transistors Tsl2, Ts22 from becoming partly conductive and causing indicating lamps Ll, L2 to glow in the event of a voltage failure in the electronic section.

In the event of either lamps Ll or L2 burning out, resistors Rll and R21 ensure that no incorrect contact condition is simulated.

A suitable indicating lamp Ll, L2 is provided by a 24 V-type, for 25 mA or 50 mA, for instance. It is of advantage that it is not necessary when switching on Lamps Ll, L2 to be concerned about the effect of the current impulse when selecting h& type~of "transistor" re~qui"red~for transistor " Tsl2, Ts22, because the impulse flows via key Tl or, respectively, T2.

The circuit arrangement is particularly suited for telecontrol devices by means of which it is desired to transmit or indicate a large number of instructions and/or information. In devices of this type difficulties relating to their physical accommodation may result from the fact that the space required for the control lines, particularly for the connection between control desks and cabinet racks, is not always freely available. Frequently these difficulties are further increased when, by employing integrated switching circuit practice, a particularly high packing density is achieved in the electronic section, thereby further increasing the number of required connections. - -

Claims (1)

1. CLAIMS A circuit arrangement for connecting switching units of switch circuit series, especially switch circuit series in TTL-technique, supplied by a first supply potential with' other circuits which are connected to a second supply potential of opposite polarity and, particularly, of greater magnitude than the first, characterized in that where the transition is to be made from the TTL-switch unit to the circuit there is provided a second level converter wherein the TTL-switch unit is connected to the base of a pnp-transistor, whose emitter is connected to zero potential (ground) by way of . a series circuit of at least two diodes connected in pass direction, or by way of a zener diode of opposite polarity, the base of said pnp-transistor being connected by way of a resistor to the second supply potential or to some other supply potential of the same polarity, and the collector of said pnp-transistor also being connected by way of the ballast resistance to the second supply potential. A circuit arrangement according to claim 1, characterized in that where transition is to be made from the circuit to the TTL-switching unit there is provided a first level converter in which there is arranged between the second supply potential (-24 V) and the first supply potential (+5 V) or another supply potential of the same polarity, a voltage divider consisting of three series-connected branches which is connected with its tap, arranged on the side of the second supply potential, to zero (ground) by way of a switch, and with its tap, arranged on the side of the first supply potential, to the base of an npn-transistor whose emitter is connected to zero potential (grond), and whose collector is connected to the following TTL-switching unit. connected to a common erasing signal transmitter. ϋ 7. A circuit arrangement according to claim 6, characterized in that the erasing signal is formed by a transistor whose emitter is connected to the first supply potential and, by way of a resistor to that base which, by way of a further resistor and, connected thereto, an additional control line, is linked to an erasing key which establishes the connection to zero potential. Θ. A circuit arrangement according to any one of the preceding claims, characterized in that one terminal of the voltage divider is conducted, by way of a common diode, from at least two of the. tilt steps to the second supply potential. 9. A circuit arrangement according to any one of claims 3 to 7, ~" characterized in that a TTL-switching circuit on the output side is designed as a negation member and that the output of at least one of the negation members is connected to one of the additional diodes of a tilt step other than the one on the input side.