IL320127A - Region identifier based on instruction fetch address - Google Patents

Region identifier based on instruction fetch address

Info

Publication number
IL320127A
IL320127A IL320127A IL32012725A IL320127A IL 320127 A IL320127 A IL 320127A IL 320127 A IL320127 A IL 320127A IL 32012725 A IL32012725 A IL 32012725A IL 320127 A IL320127 A IL 320127A
Authority
IL
Israel
Prior art keywords
instruction fetch
identifier based
fetch address
region identifier
region
Prior art date
Application number
IL320127A
Other languages
Hebrew (he)
Inventor
Alexander Donald Charles Chadwick
Original Assignee
Advanced Risc Mach Ltd
Alexander Donald Charles Chadwick
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Risc Mach Ltd, Alexander Donald Charles Chadwick filed Critical Advanced Risc Mach Ltd
Publication of IL320127A publication Critical patent/IL320127A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G06F12/1416—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights
    • G06F12/1425—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being physical, e.g. cell, word, block
    • G06F12/1441—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being physical, e.g. cell, word, block for a range
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1009—Address translation using page tables, e.g. page table structures
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/062—Securing storage systems
    • G06F3/0622—Securing storage systems in relation to access
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1052—Security improvement

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Security & Cryptography (AREA)
  • Human Computer Interaction (AREA)
  • Storage Device Security (AREA)
  • Executing Machine-Instructions (AREA)
IL320127A 2022-11-02 2023-09-27 Region identifier based on instruction fetch address IL320127A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB2216292.9A GB2623986B (en) 2022-11-02 2022-11-02 Region identifier based on instruction fetch address
PCT/GB2023/052503 WO2024094956A1 (en) 2022-11-02 2023-09-27 Region identifier based on instruction fetch address

Publications (1)

Publication Number Publication Date
IL320127A true IL320127A (en) 2025-06-01

Family

ID=84369814

Family Applications (1)

Application Number Title Priority Date Filing Date
IL320127A IL320127A (en) 2022-11-02 2023-09-27 Region identifier based on instruction fetch address

Country Status (8)

Country Link
EP (1) EP4612585A1 (en)
JP (1) JP2025538937A (en)
KR (1) KR20250100654A (en)
CN (1) CN120077368A (en)
GB (1) GB2623986B (en)
IL (1) IL320127A (en)
TW (1) TW202420076A (en)
WO (1) WO2024094956A1 (en)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7111145B1 (en) * 2003-03-25 2006-09-19 Vmware, Inc. TLB miss fault handler and method for accessing multiple page tables
GB2569358B (en) * 2017-12-15 2020-01-29 Advanced Risc Mach Ltd Code realms
GB2570474B (en) * 2018-01-26 2020-04-15 Advanced Risc Mach Ltd Region fusing
GB2578135B (en) * 2018-10-18 2020-10-21 Advanced Risc Mach Ltd Range checking instruction

Also Published As

Publication number Publication date
CN120077368A (en) 2025-05-30
EP4612585A1 (en) 2025-09-10
GB202216292D0 (en) 2022-12-14
TW202420076A (en) 2024-05-16
KR20250100654A (en) 2025-07-03
JP2025538937A (en) 2025-12-03
GB2623986B (en) 2024-10-30
GB2623986A (en) 2024-05-08
WO2024094956A1 (en) 2024-05-10

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