IL314882A - Sub-vector-supporting instruction for scalable vector instruction set architecture - Google Patents

Sub-vector-supporting instruction for scalable vector instruction set architecture

Info

Publication number
IL314882A
IL314882A IL314882A IL31488224A IL314882A IL 314882 A IL314882 A IL 314882A IL 314882 A IL314882 A IL 314882A IL 31488224 A IL31488224 A IL 31488224A IL 314882 A IL314882 A IL 314882A
Authority
IL
Israel
Prior art keywords
vector
instruction
resizable
sub
system structure
Prior art date
Application number
IL314882A
Other languages
English (en)
Hebrew (he)
Inventor
Vicente Alejandro Martinez
Peng Sun
Original Assignee
Advanced Risc Mach Ltd
Vicente Alejandro Martinez
Peng Sun
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Risc Mach Ltd, Vicente Alejandro Martinez, Peng Sun filed Critical Advanced Risc Mach Ltd
Publication of IL314882A publication Critical patent/IL314882A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G06F9/30038—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations using a mask
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30105—Register structure
    • G06F9/30109—Register structure having multiple operands in a single register
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3887—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple data lanes [SIMD]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3887—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple data lanes [SIMD]
    • G06F9/38873—Iterative single instructions for multiple data lanes [SIMD]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3887—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple data lanes [SIMD]
    • G06F9/38873—Iterative single instructions for multiple data lanes [SIMD]
    • G06F9/38875—Iterative single instructions for multiple data lanes [SIMD] for adaptable or variable architectural vector length

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Devices For Executing Special Programs (AREA)
  • Complex Calculations (AREA)
  • Advance Control (AREA)
IL314882A 2022-03-11 2022-12-15 Sub-vector-supporting instruction for scalable vector instruction set architecture IL314882A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB2203431.8A GB2616601B (en) 2022-03-11 2022-03-11 Sub-vector-supporting instruction for scalable vector instruction set architecture
PCT/GB2022/053244 WO2023170373A1 (en) 2022-03-11 2022-12-15 Sub-vector-supporting instruction for scalable vector instruction set architecture

Publications (1)

Publication Number Publication Date
IL314882A true IL314882A (en) 2024-10-01

Family

ID=81254804

Family Applications (1)

Application Number Title Priority Date Filing Date
IL314882A IL314882A (en) 2022-03-11 2022-12-15 Sub-vector-supporting instruction for scalable vector instruction set architecture

Country Status (9)

Country Link
US (1) US20250156184A1 (https=)
EP (1) EP4490612A1 (https=)
JP (1) JP2025507837A (https=)
KR (1) KR20240159595A (https=)
CN (1) CN118829969A (https=)
GB (1) GB2616601B (https=)
IL (1) IL314882A (https=)
TW (1) TW202403546A (https=)
WO (1) WO2023170373A1 (https=)

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4745547A (en) * 1985-06-17 1988-05-17 International Business Machines Corp. Vector processing
US9557995B2 (en) * 2014-02-07 2017-01-31 Arm Limited Data processing apparatus and method for performing segmented operations
EP3125108A1 (en) * 2015-07-31 2017-02-01 ARM Limited Vector processing using loops of dynamic vector length
GB2540939B (en) * 2015-07-31 2019-01-23 Advanced Risc Mach Ltd An apparatus and method for performing a splice operation
US10108581B1 (en) * 2017-04-03 2018-10-23 Google Llc Vector reduction processor

Also Published As

Publication number Publication date
US20250156184A1 (en) 2025-05-15
EP4490612A1 (en) 2025-01-15
JP2025507837A (ja) 2025-03-21
GB2616601B (en) 2024-05-08
WO2023170373A1 (en) 2023-09-14
TW202403546A (zh) 2024-01-16
GB202203431D0 (en) 2022-04-27
KR20240159595A (ko) 2024-11-05
CN118829969A (zh) 2024-10-22
GB2616601A (en) 2023-09-20

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