IL314882A - Sub-vector-supporting instruction for scalable vector instruction set architecture - Google Patents
Sub-vector-supporting instruction for scalable vector instruction set architectureInfo
- Publication number
- IL314882A IL314882A IL314882A IL31488224A IL314882A IL 314882 A IL314882 A IL 314882A IL 314882 A IL314882 A IL 314882A IL 31488224 A IL31488224 A IL 31488224A IL 314882 A IL314882 A IL 314882A
- Authority
- IL
- Israel
- Prior art keywords
- vector
- instruction
- resizable
- sub
- system structure
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/3001—Arithmetic instructions
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
- G06F9/30038—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations using a mask
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
- G06F9/30043—LOAD or STORE instructions; Clear instruction
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/30105—Register structure
- G06F9/30109—Register structure having multiple operands in a single register
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
- G06F9/3887—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple data lanes [SIMD]
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
- G06F9/3887—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple data lanes [SIMD]
- G06F9/38873—Iterative single instructions for multiple data lanes [SIMD]
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
- G06F9/3887—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple data lanes [SIMD]
- G06F9/38873—Iterative single instructions for multiple data lanes [SIMD]
- G06F9/38875—Iterative single instructions for multiple data lanes [SIMD] for adaptable or variable architectural vector length
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Computational Mathematics (AREA)
- Devices For Executing Special Programs (AREA)
- Complex Calculations (AREA)
- Advance Control (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB2203431.8A GB2616601B (en) | 2022-03-11 | 2022-03-11 | Sub-vector-supporting instruction for scalable vector instruction set architecture |
| PCT/GB2022/053244 WO2023170373A1 (en) | 2022-03-11 | 2022-12-15 | Sub-vector-supporting instruction for scalable vector instruction set architecture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| IL314882A true IL314882A (en) | 2024-10-01 |
Family
ID=81254804
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| IL314882A IL314882A (en) | 2022-03-11 | 2022-12-15 | Sub-vector-supporting instruction for scalable vector instruction set architecture |
Country Status (9)
| Country | Link |
|---|---|
| US (1) | US20250156184A1 (cg-RX-API-DMAC7.html) |
| EP (1) | EP4490612A1 (cg-RX-API-DMAC7.html) |
| JP (1) | JP2025507837A (cg-RX-API-DMAC7.html) |
| KR (1) | KR20240159595A (cg-RX-API-DMAC7.html) |
| CN (1) | CN118829969A (cg-RX-API-DMAC7.html) |
| GB (1) | GB2616601B (cg-RX-API-DMAC7.html) |
| IL (1) | IL314882A (cg-RX-API-DMAC7.html) |
| TW (1) | TW202403546A (cg-RX-API-DMAC7.html) |
| WO (1) | WO2023170373A1 (cg-RX-API-DMAC7.html) |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4745547A (en) * | 1985-06-17 | 1988-05-17 | International Business Machines Corp. | Vector processing |
| US9557995B2 (en) * | 2014-02-07 | 2017-01-31 | Arm Limited | Data processing apparatus and method for performing segmented operations |
| EP3125108A1 (en) * | 2015-07-31 | 2017-02-01 | ARM Limited | Vector processing using loops of dynamic vector length |
| GB2540939B (en) * | 2015-07-31 | 2019-01-23 | Advanced Risc Mach Ltd | An apparatus and method for performing a splice operation |
| US10108581B1 (en) * | 2017-04-03 | 2018-10-23 | Google Llc | Vector reduction processor |
-
2022
- 2022-03-11 GB GB2203431.8A patent/GB2616601B/en active Active
- 2022-12-15 EP EP22826607.8A patent/EP4490612A1/en active Pending
- 2022-12-15 JP JP2024551945A patent/JP2025507837A/ja active Pending
- 2022-12-15 US US18/844,296 patent/US20250156184A1/en active Pending
- 2022-12-15 IL IL314882A patent/IL314882A/en unknown
- 2022-12-15 KR KR1020247033147A patent/KR20240159595A/ko active Pending
- 2022-12-15 CN CN202280093265.3A patent/CN118829969A/zh active Pending
- 2022-12-15 WO PCT/GB2022/053244 patent/WO2023170373A1/en not_active Ceased
-
2023
- 2023-02-14 TW TW112105151A patent/TW202403546A/zh unknown
Also Published As
| Publication number | Publication date |
|---|---|
| GB202203431D0 (en) | 2022-04-27 |
| WO2023170373A1 (en) | 2023-09-14 |
| TW202403546A (zh) | 2024-01-16 |
| KR20240159595A (ko) | 2024-11-05 |
| GB2616601B (en) | 2024-05-08 |
| GB2616601A (en) | 2023-09-20 |
| CN118829969A (zh) | 2024-10-22 |
| JP2025507837A (ja) | 2025-03-21 |
| EP4490612A1 (en) | 2025-01-15 |
| US20250156184A1 (en) | 2025-05-15 |
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