IL276809B2 - A target branch's version of a branch with a link instruction - Google Patents
A target branch's version of a branch with a link instructionInfo
- Publication number
- IL276809B2 IL276809B2 IL276809A IL27680920A IL276809B2 IL 276809 B2 IL276809 B2 IL 276809B2 IL 276809 A IL276809 A IL 276809A IL 27680920 A IL27680920 A IL 27680920A IL 276809 B2 IL276809 B2 IL 276809B2
- Authority
- IL
- Israel
- Prior art keywords
- branch
- instruction
- target
- link
- variant
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
- G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
- G06F9/323—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for indirect branch instructions
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
- G06F21/52—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity ; Preventing unwanted data erasure; Buffer overflow
- G06F21/54—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity ; Preventing unwanted data erasure; Buffer overflow by adding security routines or objects to programs
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3802—Instruction prefetching
- G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
- G06F9/3806—Instruction prefetching for branches, e.g. hedging, branch folding using address prediction, e.g. return stack, branch history buffer
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/445—Program loading or initiating
- G06F9/44521—Dynamic linking or loading; Link editing at or after load time, e.g. Java class loading
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Security & Cryptography (AREA)
- Computer Hardware Design (AREA)
- Executing Machine-Instructions (AREA)
- Advance Control (AREA)
- Medicines That Contain Protein Lipid Enzymes And Other Medicines (AREA)
Claims (13)
1. / CLAIMS 1. An apparatus comprising: an instruction decoder to decode instructions; and processing circuitry to perform data processing in response to instructions decoded by the instruction decoder; in which: in response to a branch instruction, the instruction decoder is configured to control the processing circuitry to trigger a non-sequential change of program flow to an instruction at a target address; when the non-sequential change of program flow is triggered in response to a branch-with-link instruction, the instruction decoder is configured to control the processing circuitry to set a return address for a subsequent return of program flow; when the non-sequential change of program flow is triggered in response to at least one target-checking type of branch instruction, the instruction decoder is configured to control the processing circuitry to trigger an error handling response when the instruction at the target address is an instruction other than at least one permitted type of branch target instruction; and for at least a subset of said at least one target-checking type of branch instruction, said at least one permitted type of branch target instruction includes a branch target variant of the branch-with-link instruction; and in response to the branch target variant of the branch-with-link instruction, the processing circuitry is configured to set the return address to an address of the branch target variant of the branch-with-link instruction.
2. The apparatus according to claim 1, in which: in response to a branch-with-link instruction other than the branch target variant, the processing circuitry is configured to set the return address to an address of a next instruction sequentially following the branch-with-link instruction.
3. The apparatus according to any preceding claim, in which: the processing circuitry is configured to suppress a non-sequential change of 276809/ program flow associated with the branch target variant of the branch-with-link instruction, when program flow passes non-sequentially from a branch instruction of said at least one target-checking type to the branch target variant of the branch-with-link instruction.
4. The apparatus according to any preceding claim, in which: for a first target-checking type of branch instruction, the branch target variant of the branch-with-link instruction is one of said at least one permitted type of branch target instruction; and for a second target-checking type of branch instruction, the branch target variant of the branch-with-link instruction is not one of said at least one permitted type of branch target instruction.
5. The apparatus according to any preceding claim, in which: a first branch target variant of the branch-with-link instruction is one of said at least one permitted type of branch target instruction for a first subset of one or more target checking types of branch instruction; and a second branch target variant of the branch-with-link instruction is one of said at least one permitted type of branch target instruction for a second subset of one or more target-checking types of branch instruction different to the first subset.
6. The apparatus according to any preceding claim, in which the branch target variant of the branch-with-link instruction has a different encoding to another variant of the branch-with-link instruction which is not one of said at least one permitted type of branch target instruction.
7. The apparatus according to any of claims 1 to 5, in which the branch target variant of the branch-with-link instruction has a same encoding as another variant of the branch-with link instruction which is not one of said at least one permitted type of branch target instruction. 276809/
8. The apparatus according to any of claims 1 to 5 and 7, in which at least one of the instruction decoder and the processing circuitry is configured to determine the variant of a given branch-with-link instruction based on at least one parameter other than the instruction encoding of the given branch-with-link instruction.
9. The apparatus according to claim 8, in which said at least one parameter comprises a configuration parameter stored in a configuration register.
10. The apparatus according to any of claims 8 and 9, in which said at least one parameter comprises an instruction address of the given branch-with-link instruction.
11. The apparatus according to any of claims 8 to 10, in which, when program flow passes non-sequentially from a given target-checking type of branch instruction to a given branch-with-link instruction, said at least one parameter comprises an instruction address of said given target-checking type of branch instruction.
12. The apparatus according to claim 11, in which in response to an exception taken between the given target-checking type of branch instruction and the given branch-with-link instruction, the processing circuitry is configured to record information for determining the variant of the given branch-with-link instruction.
13. A data processing method comprising: in response to a branch instruction, triggering a non-sequential change of program flow to an instruction at a target address; when the non-sequential change of program flow is triggered in response to a branch-with-link instruction, setting a return address for a subsequent return of program flow; and when the non-sequential change of program flow is triggered in response to at least one target-checking type of branch instruction, triggering an error handling response when the instruction at the target address is an instruction other than at least one permitted type of branch target instruction; 276809/ wherein for at least a subset of said at least one target-checking type of branch instruction, said at least one permitted type of branch target instruction includes a branch target variant of the branch-with-link instruction; and in response to the branch target variant of the branch-with-link instruction the return address is set to an address of the branch target variant of the branch-with-link instruction.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB1804231.7A GB2571996B (en) | 2018-03-16 | 2018-03-16 | Branch target variant of branch-with-link instruction |
| PCT/GB2019/050379 WO2019175530A1 (en) | 2018-03-16 | 2019-02-13 | Branch target variant of branch-with-link instruction |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| IL276809A IL276809A (en) | 2020-10-29 |
| IL276809B1 IL276809B1 (en) | 2023-11-01 |
| IL276809B2 true IL276809B2 (en) | 2024-03-01 |
Family
ID=62017690
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| IL276809A IL276809B2 (en) | 2018-03-16 | 2019-02-13 | A target branch's version of a branch with a link instruction |
Country Status (9)
| Country | Link |
|---|---|
| US (1) | US11307856B2 (en) |
| EP (1) | EP3765957B1 (en) |
| JP (1) | JP7377807B2 (en) |
| KR (1) | KR102773321B1 (en) |
| CN (1) | CN111771188B (en) |
| GB (1) | GB2571996B (en) |
| IL (1) | IL276809B2 (en) |
| TW (1) | TWI801505B (en) |
| WO (1) | WO2019175530A1 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112363779A (en) * | 2020-11-25 | 2021-02-12 | 王志平 | Safety control method for dynamic link program |
| CN114528025B (en) * | 2022-02-25 | 2022-11-15 | 深圳市航顺芯片技术研发有限公司 | Instruction processing method and device, microcontroller and readable storage medium |
| US20230418608A1 (en) * | 2022-06-23 | 2023-12-28 | Intel Corporation | Implicit memory corruption detection for conditional data types |
Family Cites Families (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0729097A1 (en) * | 1995-02-07 | 1996-08-28 | Sun Microsystems, Inc. | Method and apparatus for run-time memory access checking and memory leak detection of a multi-threaded program |
| JP2002259118A (en) * | 2000-12-28 | 2002-09-13 | Matsushita Electric Ind Co Ltd | Microprocessor and instruction sequence converter |
| US6874081B2 (en) * | 2001-05-17 | 2005-03-29 | Broadcom Corporation | Selection of link and fall-through address using a bit in a branch address for the selection |
| US7290179B2 (en) * | 2003-12-01 | 2007-10-30 | Intel Corporation | System and method for soft error handling |
| US9176737B2 (en) * | 2011-02-07 | 2015-11-03 | Arm Limited | Controlling the execution of adjacent instructions that are dependent upon a same data condition |
| US20130024676A1 (en) * | 2011-07-19 | 2013-01-24 | Glew Andrew F | Control flow integrity |
| US9798873B2 (en) * | 2011-08-04 | 2017-10-24 | Elwha Llc | Processor operable to ensure code integrity |
| US10210349B2 (en) * | 2012-02-08 | 2019-02-19 | Arm Limited | Data processing apparatus and method using secure domain and less secure domain |
| US20130318332A1 (en) * | 2012-05-22 | 2013-11-28 | Jeffry E. Gonion | Branch misprediction behavior suppression using a branch optional instruction |
| US9448796B2 (en) * | 2012-06-15 | 2016-09-20 | International Business Machines Corporation | Restricted instructions in transactional execution |
| US9384001B2 (en) * | 2012-08-15 | 2016-07-05 | Nvidia Corporation | Custom chaining stubs for instruction code translation |
| US9411590B2 (en) * | 2013-03-15 | 2016-08-09 | Qualcomm Incorporated | Method to improve speed of executing return branch instructions in a processor |
| US9305167B2 (en) * | 2014-05-21 | 2016-04-05 | Bitdefender IPR Management Ltd. | Hardware-enabled prevention of code reuse attacks |
| GB2535514B (en) * | 2015-02-19 | 2021-09-22 | Advanced Risc Mach Ltd | Processor exception handling |
| GB2541714B (en) * | 2015-08-27 | 2018-02-14 | Advanced Risc Mach Ltd | An apparatus and method for controlling instruction execution behaviour |
| GB2542831B (en) * | 2015-09-30 | 2018-05-30 | Imagination Tech Ltd | Fetch unit for predicting target for subroutine return instructions |
| US10423777B2 (en) | 2016-04-14 | 2019-09-24 | Endgame, Inc. | Preventing execution of malicious instructions based on address specified in a branch instruction |
| GB2564130B (en) * | 2017-07-04 | 2020-10-07 | Advanced Risc Mach Ltd | An apparatus and method for controlling execution of instructions |
-
2018
- 2018-03-16 GB GB1804231.7A patent/GB2571996B/en active Active
-
2019
- 2019-02-13 US US16/971,755 patent/US11307856B2/en active Active
- 2019-02-13 CN CN201980015441.XA patent/CN111771188B/en active Active
- 2019-02-13 IL IL276809A patent/IL276809B2/en unknown
- 2019-02-13 EP EP19707065.9A patent/EP3765957B1/en active Active
- 2019-02-13 JP JP2020546090A patent/JP7377807B2/en active Active
- 2019-02-13 KR KR1020207028590A patent/KR102773321B1/en active Active
- 2019-02-13 WO PCT/GB2019/050379 patent/WO2019175530A1/en not_active Ceased
- 2019-02-21 TW TW108105733A patent/TWI801505B/en active
Also Published As
| Publication number | Publication date |
|---|---|
| KR102773321B1 (en) | 2025-02-27 |
| WO2019175530A1 (en) | 2019-09-19 |
| GB2571996A (en) | 2019-09-18 |
| GB201804231D0 (en) | 2018-05-02 |
| IL276809B1 (en) | 2023-11-01 |
| TWI801505B (en) | 2023-05-11 |
| US11307856B2 (en) | 2022-04-19 |
| JP2021517293A (en) | 2021-07-15 |
| KR20200128720A (en) | 2020-11-16 |
| US20210109755A1 (en) | 2021-04-15 |
| CN111771188B (en) | 2024-09-24 |
| EP3765957B1 (en) | 2024-05-08 |
| EP3765957A1 (en) | 2021-01-20 |
| IL276809A (en) | 2020-10-29 |
| CN111771188A (en) | 2020-10-13 |
| GB2571996B (en) | 2020-09-09 |
| JP7377807B2 (en) | 2023-11-10 |
| TW201939272A (en) | 2019-10-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9280351B2 (en) | Second-level branch target buffer bulk transfer filtering | |
| US9507598B1 (en) | Auxiliary branch prediction with usefulness tracking | |
| EP2628074B1 (en) | Decoding instructions from multiple instruction sets | |
| FI3779681T3 (en) | Accelerator for sparse-dense matrix multiplication | |
| JP4950186B2 (en) | Method and apparatus for predicting branch instructions | |
| IL276809B1 (en) | Branch target variant of branch-with-link instruction | |
| JP6290303B2 (en) | Circuit and method for testing error correction capability | |
| US9946595B2 (en) | Reducing uncorrectable errors based on a history of correctable errors | |
| JP2019057276A5 (en) | ||
| EP3644179A3 (en) | Apparatus and method for tile gather and tile scatter | |
| IL276897B2 (en) | A label randomization instruction for a label-reserved memory system | |
| JP2018537800A5 (en) | ||
| JP2015133126A (en) | Method and system for accelerating a procedure return sequence | |
| US10102064B1 (en) | Two layer quad bit error correction | |
| CN107924356A (en) | Zero-overhead code coverage is analyzed | |
| JP2016517092A (en) | Method for improving the speed of executing a return branch instruction in a processor | |
| US9135012B2 (en) | Instruction filtering | |
| IL275873B2 (en) | Checking a memory access visitor guard tag | |
| JP2018527657A (en) | Suppressing conditional loading | |
| JP2019519858A5 (en) | ||
| JP2015535634A5 (en) | ||
| DE602006007825D1 (en) | Fault-tolerant control system | |
| JP7049275B2 (en) | Diagnostic data capture | |
| IL273130B1 (en) | Transaction nesting depth test instruction | |
| JP5882800B2 (en) | Information processing device having list command verification function, list command verification method, and program for list command verification |