IL243056A - Digital to analog converter implemented on an integrated circuit - Google Patents

Abstract

Digital-to-analog converter for generating analog output signal respective of digital input signal. A first circuit portion of an integrated circuit operable as a lookup table receives digital input having bit-width of "n", and produces a corresponding bitstream representing a vector of bit-length "2n+m", where "m" is a positive integer representing marginal vector values of lookup table. The total number of ones in the bitstream is equal to "y" being a positive integer proportional to the digital input signal value. A serial interface of the integrated circuit receives the bitstream from the first circuit portion and produces a corresponding serial bitstream at a higher bit rate. A second circuit portion operable as a low pass filter converts the serial bitstream into a voltage signal. The voltage signal level corresponds to the equation: "y/2n+m", representing the ratio between: the total number of ones in the bitstream, and the bit-length of the bitstream. [WO2017103915A1]

Description

FIELD OF THE INVENTION The present invention relates to electronic circuits in general, and to digital to analog converters in particular.

BACKGROUND OF THE INVENTION A field-programmable gate array (FPGA) is a type of integrated circuit generally composed of a large collection of logic blocks and memory elements configured to implement complex digital computations. An FPGA can be reprogrammed to alter its functionality or application, providing particular advantages over an application specific integrated circuit (ASIC) which is custom manufactured for a specific task. While some FGPAs include certain analog features, they are primarily digital components that produce digital output signals. A "mixed signal" FPGA includes both analog and digital circuitry, such as integrated analog-to-digital converters (ADCs) or digital-to-analog converters (DACs).

Reference is now made to Figure 1 , which is a schematic illustration of an electronic circuit, generally referenced 50, of an exemplary peripheral N-bit digital-to-analog converter (DAC), which is known in the art. DAC circuit 50 includes a group of elements that collectively make up a delta sigma modulator, referenced 54, and further includes a low pass filter, referenced 56. Delta sigma modulator 54 receives the "N"-bit digital input signal and produces a bitstream which represents the input signal level. Low pass filter 56 receives the bitstream from delta sigma modulator 54 and produces a bitstream average value to generate the analog output signal.

DAC circuit 50 is a relative simple and straightforward circuit, but is unable to be implemented within an FPGA. Accordingly, DAC circuit 50 represents a separate external or peripheral component that cannot be embedded as part of the FPGA. The need for a separate external component to implement the DAC functionality serves to increase the overall size, the power requirements, and the cost of the complete product. An additional drawback of an external DAC is reduced flexibility and reliability, such as due to the possibility of malfunctioning or damaging of the external component.

An FPGA typically includes a unit known as a Serializer/Deserializer (SerDes) to transmit and receive data over a serial differential interface rather than a parallel single-ended signal bus, providing a much higher data transmission rate and minimizing the number of required input/output (I/O) pins. The SerDes includes two main functional blocks: one to convert a parallel bus input into a serial data stream on the transmitter end, and another to convert the serial data stream back to a parallel data output on the receiver end. The functional blocks may be implemented in various architectures and circuitry designs, such as using a phase-locked loop (PLL) driven by a reference clock input to produce the high-speed clock for the serial transmission. A serial bus can usually operate at a much higher data rate than a parallel bus in a comparable environment, since there is no separate clock signal in a serial interface which eliminates timing skew between clock and data, and there is no need to compensate for delays between the different inputs/outputs of the bus. At higher frequency rates, faster-switching parallel buses consume substantially more power, and are more difficult to route given the lowered timing tolerances. The SerDes thereby enables high speed data transmission over the serial interface, while reducing complexity, cost, power and board space usage associated with needing to implement wide bit-width parallel buses.

U.S. Patent No. 8,164,499 to Booth et al., entitled: “Shared-array multiple-output digital-to-analog converter”, is directed to an integrated circuit having two or more different digital-to-analog converter (DAC) functions. The integrated circuit includes a current mirror array that is shared by the different DAC functions. The DAC functions may be at least two current DAC (IDAC) functions, configured to receive respective non-zero IDAC input signals and to generate respective non-zero IDAC output signals at the same time. The shared current mirror array may be part of a decision feedback equalizer (DFE) configured to use the shared current mirror array to generate two or more IDAC current signals used to generate an equalized data signal. The DFE equalizer may be part of a serializer-deserializer (SerDes) receiver. The DFE equalizer may include an initial amplifier stage to generate an initial current signal, and a summation node to combine the initial current signal and the IDAC current signals to generate the equalize data signal.

U.S. Patent Application Publication No. 2013/0201041 to Roze et al, entitled “Digital-to-analog converter (DAC) with common mode tracking and analog-to-digital converter (ADC) functionality to measure DAC common mode voltage”, discloses a DAC with common mode tracking and ADC functionality that can be implemented in a SERDES. A first circuit portion is operable as a DAC for generating a DAC common mode voltage signal ("outp"). A second circuit portion has a comparator for comparing the DAC common mode voltage signal ("outp") against a received signal common mode voltage ("vsumdc"), where the comparator provides a single-bit output. A single-bit register receives the single-bit output of the comparator and is used to control a feedback circuit, which controls the DAC common mode voltage signal.

SUMMARY OF THE INVENTION In accordance with one aspect of the present invention, there is thus provided a digital-to-analog converter (DAC) for generating an analog output signal respective of a digital input signal. The DAC includes a first circuit portion of an integrated circuit operable as a lookup table (LUT), a serial interface of the integrated circuit, and a second circuit portion operable as a low pass filter. The first circuit portion is configured to receive the digital input signal having a bit-width of where "/?" is a positive integer greater than 1 , and to produce a corresponding bitstream representing a vector of bit-length "2? + m", where "m" is a positive integer representing marginal vector values of the LUT, and where the total number of ones in the bitstream is equal to "y" being a positive integer proportional to the value of the digital input signal. The serial interface is configured to receive the bitstream from the first circuit portion and to produce a corresponding serial bitstream at a higher bit rate. The second circuit portion is configured to convert the serial bitstream into a voltage signal, such that the voltage level of the voltage signal corresponds to the equation: "y / 2? + m", representing the ratio between: the total number of ones in the bitstream, and the bit-length of the bitstream. The frequency of the serial bitstream is a factor of ( 2? + m) times the parallel clock frequency of the parallel bus of the serial interface.

The integrated circuit may be a field-programmable gate array (FPGA). The serial interface may be a serial interface of a serializer/deserializer (SerDes).

In accordance with another aspect of the present invention, there is thus provided a method for generating an analog output signal respective of a digital input signal, with a digital-to-analog converter (DAC). The method includes the procedure of receiving the digital input signal having a bit-width of where "n" is a positive integer greater than 1, at a first circuit portion of an integrated circuit (IC) operable as a lookup table (LUT), and producing a corresponding bitstream representing a vector of bit-length "2? + m", where "m" is a positive integer representing marginal vector values of the LUT, and where the total number of ones in the bitstream is equal to "y" being a positive integer proportional to the value of the digital input signal. The method further includes the procedure of receiving the bitstream at a serial interface of the integrated circuit and producing a corresponding serial bitstream at a higher bit rate. The method further includes the procedure of converting the serial bitstream into a voltage signal with a second circuit portion operable as a low-pass filter (LPF), such that the voltage level of the voltage signal corresponds to the equation: "y / 2? + m", representing the ratio between the total number of ones in the bitstream, and the bit-length of the bitstream. The frequency of the serial bitstream is a factor of (2n + m) times the parallel clock frequency of the parallel bus of the serial interface.

BRIEF DESCRIPTION OF THE DRAWINGS The present invention will be understood and appreciated more fully from the following detailed description taken in conjunction with the drawings in which: Figure 1 is a schematic illustration of an electronic circuit for an exemplary peripheral N-bit digital-to-analog converter (DAC), which is known in the art; Figure 2 is a schematic illustration of a digital-to-analog converter (DAC) that is primarily implemented on a field-programmable gate array (FPGA), constructed and operative in accordance with an embodiment of the present invention; Figure 3 is a schematic illustration of the conversion of an exemplary digital input signal into an analog voltage signal using the DAC of Figure 2, operative in accordance with an embodiment of the present invention; and Figure 4 is a screenshot image of an oscilloscope measurement of a DAC signal conversion of an example prototype operative in accordance with an embodiment of the present invention.

DETAILED DESCRIPTION OF THE EMBODIMENTS The present invention overcomes the disadvantages of the prior art by providing an integrated circuit, such as a field-programmable gate array (FPGA), with an embedded digital-to-analog converter (DAC) that exploits the internal high speed serial interface inherent in the circuit, such as the Serializer/Deserializer (SerDes). The internal DAC includes circuitry for at least a look-up table (LUT) and a low-pass filter (LPF). The LUT receives a digital input signal having a bit-width of "/?" and produces a corresponding bitstream representing a vector of bit-length "2n" or "2? + m" (where "m" is a positive integer representing marginal vector values of the LUT, as will be discussed further hereinbelow). The total number of ones in the resultant bitstream is proportional to the digital input signal value. The SerDes serially outputs the bitstream at a higher bit rate. The LPF converts the serial bitstream into a voltage signal, such that the voltage signal level is proportional to the ratio between the total number of ones in the bitstream and the bit-length of the bitstream.

Reference is now made to Figure 2, which is a schematic illustration of a digital-to-analog converter (DAC), generally referenced 100, that is implemented on a field-programmable gate array (FPGA), constructed and operative in accordance with an embodiment of the present invention. The embodiment of Figure 2 is depicted as an FPGA for exemplary purposes only, and it will be appreciated that the present invention is equally applicable to other types of integrated circuits, including but not limited to: application specific integrated circuits (ASIC); programmable system on chips (PSoCs); programmable logic device (PLDs); digital ICs; mixed ICs; and the like.

FPGA 110 includes a Serializer/Deserializer (SerDes) 124, of which DAC 100 utilizes the serial interface (serializer) portion, as will be discussed hereinbelow. In general, the DAC circuit of the present invention may be implemented on any type of serial interface configured to serialize parallel input data so as to enable high speed data transmission (e.g., above approximately 1 GHz).

DAC 100 includes a look-up table (LUT) circuit 122, SerDes 124, and a low-pass filter (LPF) circuit 126. LUT 122 is implemented on FPGA 110, while LPF 126 is external to FPGA 110 but on the printed circuit board (PCB). A LUT is used to quickly realize a complex function in digital logic, where the address is the function input, and the value at that address is the function output. LUT 122 stores an array of values representing vectors which represent different amplitudes (in the form of voltages). In particular, LUT 122 is configured to store a total of 2? values, where each value is a vector having a bit-length (size) of 2n, and where each ^-bit vector represents one n-bit digital input word, as will be elaborated upon further below (Fig. 3). LUT 122 may be implemented using digital logic design techniques known in the art, such as being embodied by a series of RAM or ROM cells in an array.

LPF 126 receives an input (serial) bitstream and produces a voltage signal, by passing through signal frequencies lower than the LPF cutoff frequency while attenuating signal frequencies above the LPF cutoff frequency. The voltage signal is constant as long as the repeatedly transmitted bitstream remains constant (i.e., the vector value remains the same). The output voltage level is proportional to the ratio between ones and zeros in the input bitstream (and in the initial digital input signal), as will be elaborated upon further below (Fig. 3). LPF 126 may be implemented using passive and/or active components based on design techniques known in the art (usually involving an operational amplifier, resistors and capacitors).

Reference is now made to Figure 3, which is a schematic illustration of the conversion of an exemplary digital input signal into an analog voltage signal using the DAC of Figure 2, operative in accordance with an embodiment of the present invention. A 4-bit input signal, referenced 132, is fed into LUT 122. More generally, the input data signal may be any binary number of bit-width In this example, input signal 132 is the binary number "0100" (n= 4) which represents the decimal number value "4". LUT 122 outputs a bitstream, referenced 134. The length of the output bitstream is "2”". The number of ones (1s) in the output bitstream is equal to the integer "y", where "y" is proportional to the input value. In this example, bitstream 134 corresponds to the following bit sequence: "0100010001000100", such that y = 4 (i.e., a total of 4 bits out of 16 are "1s"), and the bitstream length is: 24 = 16. SerDes 124 receives (parallel) bitstream 134 from LUT 122 and serially outputs an identical bitstream 136 at a higher bit rate. If the parallel data frequency is represented by '7W (i.e., the internal parallel clock of the parallel bus of SerDes 124), then the serial data frequency (i.e., the effective data frequency of the serial transmission line of SerDes 124) would correspond to: 2? * Pcik- For example, if pdk = 200MHz, then the serial data frequency (or bit rate) of bitstream 136 would be: 16 * 200MHz = 3.2GHz.

Serial bitstream 136 is then fed into LPF 126, which outputs an analog voltage signal, referenced 138. The voltage level of the output voltage signal 138 corresponds to the ratio between the number of "1s" in the bitstream (134 or 136) and the size of the bitstream, i.e., "y/ 2n". In this example, the voltage level of voltage signal 138 corresponds to: V = [(y = 4) / {2? = 16)] = 0.25 Vcc (i.e., since a quarter of the total number of bits in bitstream 134 are "T's). If, for example, the output voltage is established to range between 0V and 500mV (i.e., such that Vcc = 500mV), then the final output voltage level would be 0.25 * 500mV = 125mV.

For another example, if the input data signal represents the binary number "10010" (n=5) corresponding to the decimal number "18", then the bitstream output from LUT 122 would have a size of: 25 = 32 bits, and would have a total of 18 "1s". Accordingly, the bitstream vector may be represented by the following sequence: "01110010101101010111001010110101". Subsequently, the voltage signal output from LPF 126 would have a voltage level of 18/32 = 0.5625 * Vcc (e.g., = 0.5625 * 500mV = 281 .3mV). The voltage levels (Vcc) may be any suitable value, since the implementation of LPF 126 may include amplification of the signal.

According to an embodiment of the present invention, the size of the bitstream vector provided by LUT 122 may be a general integer value that is not an exact power of two. For example, a bitstream of size 280 can represent 256 different values (= 28), by ignoring a total of 24 values, such as by ignoring all vectors with 12 or less ones (1s) and 12 or less zeros (0s). It is noted that such a configuration may also result in a reduction of circuit noise, since those margins (i.e., 12 or less ones and 12 or less zeros) typically suffer from higher noise in the analog filter portion. In general, the parallel bus width of SerDes 124 may be used as the multiplication factor of the bitstream (i.e., SerDes frequency = bus-width * Pcik). For example, a SerDes that transmits a 40-bit bus with a parallel clock of 200MHz can reach a data rate of 8GHz (= 40 * pcik). To obtain 8-bit resolution would require at least 28 = 256 different values (of the input data). Thus, one approach would be to transmit 7 different sequences of 40 bits each, which would result in (7 * 40 =) 280 bit-length bitstream and a parallel data frequency of 28.57MHz (= pdk / 7).

Accordingly, the bitstream size may be more generally expressed by the equation: 2? + m, where "m" represents the margins or the vector values that are ignored in look-up table 122 (e.g., m = 0 when the bitstream vector size is an exact power of two). The bitstream size is typically determined by two factors: the DAC resolution and the physical properties of the SerDes. The DAC resolution refers to the number of different levels which correspond to the number of bitstream vectors. The SerDes physical properties refer to the multiplication factor of SerDes 124, or the number of bits that SerDes 124 can transmit on each clock cycle (usually 40). Increasing the DAC resolution would require sending longer bitstreams, which results in a decrease in the DAC maximum frequency.

It is noted that the bitstream frequency represents the SerDes input (parallel) bus width (usually 40) multiplied by the parallel data input frequency. Since multiple cycles of the parallel data clock are used (depending on the required resolution), the parallel frequency should be divided by the number of cycles to reach the input signal maximum frequency, where 2? is the minimal bitstream length. More generally, the minimal bitstream length would be represented by: + m.

Reference is now made to Figure 4, which is a screenshot image of an oscilloscope measurement of a DAC signal conversion of an example prototype, operative in accordance with an embodiment of the present invention. In an example prototype, a 6.579MHz signal is produced from a 1GHz bitstream (serial data frequency) using a prototype DAC in accordance with the present invention. The bitstream size is 80-bits, produced from a 53.12MHz clock (parallel clock frequency), where each clock cycle 20-bits are transmitted. As a result, a frequency of 13.28MHz [= 53.12MHz / (80 bits / 20bits)] is introduced. After reducing the bandwidth to NTSC bandwidth of 4.5MHz, a 170mV noise level was reached.

A DAC implemented primarily on an FPGA in accordance with the present invention can be used in various applications. One such application is as an analog video encoder. For example, the DAC can be used to generate different types of video signals, such as: component RGB video signals, Y/C video signals, composite video signals, and the like. The DAC of the present invention may similarly be used to generate different types of audio signals.

Considering, for example, the following video decoder implementation (in a specific FPGA): a composite video signal where the full video is 130.8 IRE (e.g., composed of 123.3 IRE for active video, 7.5 IRE for pedestal and 40 IRE for SYNC). The SerDes can serialize a 40-bit bus each clock cycle. Since 480 different values are used for composite video, each pixel transmission requires 12 clock cycles, so the minimal parallel clock frequency (pc¾) is 162 MHz. Assuming 8-bit resolution is used and 256 bit-length bitstream, this results in a SerDes bitrate of 6480 (since the active video is around 70% of the full signal, the DAC should support more than 256 levels for 8-bit resolution (354). The parallel clock is derived from the pixel clock by multiplying by twelve (12), such that for each pixel, twelve 40-bit vectors can be transmitted. These vectors produce the representation of a single pixel. The pixel clock is derived from the parallel clock using a phase-locked loop (PLL), where the parallel clock is a multiple of the pixel clock: 162 - 13.5 * 12. Both subcarrier frequency and horizontal frequency (i.e., "video line frequency") are derived from the pixel clock. The subcarrier frequency is generated from the pixel clock using a discrete time oscillator (DTO). The LPF then averages the bitstream to the desired frequency.

In general, the DAC of the present invention may be used as part of any suitable device or applications in order to convert a digital signal into any analog signal within the available constraints (e.g., bandwidth, resolution and noise), such as the analog conversion stage of a video or audio signal generator.

It will be appreciated that the disclosed DAC of the present invention, which is primarily implemented within the FPGA (or other IC) and exploits the inherent high speed serial interface present in the FPGA, enables the generated analog signal to be transmitted directly from the FPGA and thus does not required a dedicated external DAC. This alleviates the design complexity and other limitations associated with an external DAC, and provides greater flexibility in the analog signal generation, a shorter development time, and improved reliability. Additional outcomes may include reduced price, diminished power consumption, and less board space occupied on the PCB.

In accordance with the present invention, there is provided a method for generating an analog signal respective of a digital input signal with a DAC. The method includes the procedure of receiving the digital input signal having a bit-width of where "n" is a positive integer greater than 1 , at a first circuit portion of an integrated circuit operable as a lookup table (LUT), and producing a corresponding bitstream representing a

Claims (6)

1. A digital-to-analog converter (DAC) for generating an analog output signal respective of a digital input signal, said DAC comprising: a first circuit portion of an integrated circuit (IC), said first circuit portion operable as a lookup table (LUT), configured to receive said digital input signal having a bit-width wherein "/?" is a positive integer greater than 1, and to produce a corresponding bitstream representing a vector of bit-length "2? + m", wherein "m" is a positive integer representing marginal vector values of said lookup table, and wherein the total number of ones in said bitstream is equal to "y" being a positive integer proportional to the value of said digital input signal; a serial interface of said integrated circuit, said serial interface configured to receive said bitstream from said first circuit portion and to produce a corresponding serial bitstream at a higher bit rate; and a second circuit portion operable as a low-pass filter (LPF), configured to convert said serial bitstream into a voltage signal, such that the voltage level of said voltage signal corresponds to the equation: "y / 2? + m", representing the ratio between: the total number of ones in said bitstream; and the bit-length of said bitstream.

2. The DAC of claim 1 , wherein the frequency of said serial bitstream is a factor of (2" + m) times the parallel clock frequency of the parallel bus of said serial interface.

3. The DAC of claim 1 , wherein said IC comprises a field-programmable gate array (FPGA).

4. The DAC of claim 1 , wherein said serial interface comprises a serial interface of a serializer/deserializer (SerDes).

5. The DAC of claim 1 , wherein said output voltage signal comprises an analog signal selected from the list consisting of: an RGB video signal; a Y/C video signal; a composite video signal; and any combination of the above.

6. A method for generating an analog output signal respective of a digital input signal, with a digital-to-analog converter (DAC), the method comprising the procedures of: receiving said digital input signal having a bit-width of wherein "/?" is a positive integer greater than 1 , at a first circuit portion of an integrated circuit (IC) operable as a lookup table (LUT), and producing a corresponding bitstream representing a vector of bit-length "2? + m", wherein "m" is a positive integer representing marginal vector values of said LUT, and wherein the total number of ones in said bitstream is equal to "y" being a positive integer proportional to the value of said digital input signal; receiving said bitstream at a serial interface of said integrated circuit and producing a corresponding serial bitstream at a higher bit rate; and converting said serial bitstream into a voltage signal with a second circuit portion operable as a low-pass filter (LPF), such that the voltage level of said voltage signal corresponds to the equation: "y l 2? + m", representing the ratio between the total number of ones in said bitstream; and the bit-length of said bitstream.