IL197544A - Moving image sensor by successive integration and summation, with active cmos pixels - Google Patents

Description

Ο' 'ορκ CMOS ' op'o ov .Q-S'in ατιι airn niyxnjo nw η.ιητι \w>n r^v^tl^l0R BY SUCCESSIVE INTEGRATION AND SUMMATION, WITH AO 1 IVb CMOS PIXELS E2V SEMICONDUCTORS C: 68002 MOVING IMAGE SENSOR BY SUCCESSIVE INTEGRATION AND SUMMATION, WITH ACTIVE CMOS PIXELS The invention relates to traveling and signal- integrating type linear image sensors (or TDI sensors, standing for: "Time Delay Integration Linear Sensors"), in which an image of a line of points of an observed scene is reconstituted by adding together successive images taken by several photosensitive lines successively observing one and the same line of the scene as the scene travels past the sensor perpendicularly to the lines.

These sensors are used for example in satellite- based Earth observation sensors. They comprise several parallel lines of photosensitive pixels; the sequencing of the control circuits for the various lines (control of time of exposure and then of readout of the photogenerated charges) is synchronized with respect to the relative travel of the scene and of the sensor, in such a manner that all the lines of the sensor see a single line of the observed scene. The signals generated by each line are thereafter added together point-by-point for each point of the observed line.

The theoretical signal/noise ratio is improved in the ratio of the square root of the number N of lines of the sensor. This number N can be for example 16 or 32 for industrial control applications or applications of Earth observation from space, or even from 60 to 100 lines for medical applications (dentistry, mammography, etc . ) .

In charge transfer image sensors (CCD sensors), the addition of the signals point by point was done naturally and with no readout noise by draining in a line of pixels the charges generated and accumulated in the previous line of pixels, in synchronism with the relative displacement of the scene and the sensor. The last line of pixels, having accumulated N times the charges generated by the observed line of the scene, was thereafter able to be transferred to an output register and converted, during a readout phase, into electrical voltage or current.

Image sensor technology has thereafter evolved towards sensors with active pixels with transistors, that hereinafter will be called CMOS sensors for simplicity since they are generally produced using CMOS (complementary-metal-oxide-semiconductor} technology; in these CMOS sensors there is no longer any transfer of charges from pixel to pixel to a readout register but there are active pixels with transistors which gather photogenerated electrical charges and convert them directly into a voltage or current . The various lines of the sensor therefore successively provide voltages or currents representing the illumination received by the line. These currents or voltages cannot easily be added up; it is therefore difficult to produce a traveling and charge-integrating sensor.

Attempts have however been made to produce CMOS traveling and charge-integrating sensors.

The use has been tried in particular of switched capacitors in which successive currents received are integrated, thus accumulating on one and the same capacitor charges received from several pixels columnwise .

The systems thus tried are complex and it would be desirable to find alternative solutions.

According to the invention, it is proposed to convert into digital values the signals arising from a line of pixels, to sum the digital value corresponding to the pixel of rank j of the line in an accumulator register of rank j which already contains the sum of i accumulated digital values corresponding to the pixels of like rank j of i successive lines, and to extract the content of the accumulator register only after N accumulation steps, that is to say when it contains the sum of N accumulated digital values corresponding to the N lines of pixels of the sensor. There is therefore a transfer matrix composed of N lines of accumulator registers; a line of registers receives, so as to accumulate it with the previous content of the registers, the successive contents of the various lines of the sensor, according to a circular permutation; the content of the registers is extracted after N accumulations, according to a circular permutation. When the content of a line of registers has been extracted, this line of registers is reset to zero, and it is available thereafter to receive the content of the first line of pixels of the sensor. To each new exposure period there corresponds a phase of extracting a line of registers; and at each new exposure period the digital values of a determined line of pixels are accumulated with the contents of a different line of registers, according to a circular permutation.

Thus, the digital values of the first line of pixels of the sensor are stored firstly in a line of registers whose contents are at zero, then successively at each new exposure, according to a circular permutation, in the other lines of registers where they are accumulated with the already present contents; the same holds for the other lines of photosensitive pixels: they are stored successively in the various lines of registers, each time in a new line of registers .

The invention therefore relates to a method of image capture, of the traveling and signal-summing type, for the synchronized readout of one and the same image line successively by N lines of P photosensitive pixels and the pixel by pixel summation of the signals read out by the various lines, characterized in that: - on completion of each integration period of a series of charge integration periods, the signals arising from the N lines of pixels are digitized by an analog-digital converter, the digitized signals of a line of pixels are accumulated in a chosen line of a transfer matrix which comprises N lines of P accumulator registers, doing so for the N lines of pixels and the N lines of the transfer matrix, while modifying at each integration period the correspondence between the chosen line of the transfer matrix and the line of pixels, in synchronism with the traveling of the image past the sensor in such a manner that a line of registers of the transfer matrix receives and accumulates successively in the course of N integration periods the digitized signals of N lines of pixels having seen one and the same image line, - after N integration periods the content of a determined line of registers, representing an observed image line, is extracted and the registers of this line are reset to zero, - at each following integration period it is the content of another line of registers, according to a circular permutation of the N lines, which is extracted and reset to zero, the line extracted and reset to zero being, on completion of each integration period, that which has undergone N accumulations after a reset to zero .

More precisely, a pixel of rank j in a line is made up of a circuit with MOS transistors comprising an output linked to a column conductor of rank j common to the N pixels of rank j of the various lines, and the method comprises the following operations: - simultaneous integration of charges in the NxP pixels, repeated during successive integration periods; - successive addressing of each of the N lines of pixels at the end of an ith integration period so as to apply to the column conductors on completion of the ith integration period successively for each addressed line P analog signals corresponding to the integration of charges in the P pixels of the addressed line; - analog-digital conversion so as to digitize the P analog signals present on the column conductors in the course of each line addressing, and provide P digital values corresponding to an addressed line of rank m; - accumulation of the digital value corresponding to the pixel of rank j of an addressed line, in an accumulator register of rank j of a line of registers of a matrix of N lines of P accumulator registers, - in the course of the (i+l)th integration period, accumulation in this same accumulator register of a digital value corresponding to a pixel of rank j of another line of pixels, in correspondence with the traveling of the image past the N lines of pixels, - on completion of the (i+l)th integration period, selection of one line from among N, the selected line being a line which has undergone N successive accumulations after a reset to zero of the content of the accumulator registers of this line, extraction of the digital values accumulated in the registers of this line, representing an observed image line, and resetting to zero of the registers of this line with a view to a new series of N integration periods for this line, circular permutation of the order of the register lines which are selected for an extraction and a resetting to zero on completion of the successive integration periods.

If the rank of the line addressed in the course of the ith integration period is called m, then the other line accumulated with the latter in the course of the (i+l}th integration period will in principle be an adjacent line of rank m+l such that the accumulation in one and the same line of accumulator registers originates from a succession of lines of pixels ordered according to a circular permutation; if the assumption is made that the first line of pixels has been stored in a first line of accumulator registers in the course of a first integration period, then at the second integration period it is the second line of pixels which is accumulated in the first line of registers, and so on and so forth according to a circular permutation: at the Nh integration period, it is the Nth line of pixels which is accumulated in the first line of registers; the value stored in the first line of registers is then extracted; it represents a first line of the observed image; this first line of registers is reset to zero, ready to receive new digital values, again originating from the first line of pixels, on completion of the (N+l)th integration period; and on completion of this (N+l)th integration period, the value stored in the second line of accumulator registers is extracted; it represents a second line of the observed image; then it is reset to zero. Henceforth, after 2N integration periods the digital information stored in the first line of registers, representing an (N+l)th line of the observed image, is again extracted.

In addition to the method which has just been defined, the invention also relates to an image sensor, of the traveling and summing type, allowing the synchronized readout of one and the same image line successively by N lines of P photosensitive pixels and the pixel by pixel summation of the signals read out by the various lines, a pixel of rank j in a line being made up of a circuit with MOS transistors comprising an output linked to a column conductor of rank j common to the N pixels of rank j of the various lines, the sensor being characterized in that it comprises: - a successive addressing circuit for each of the N lines of pixels for applying to the column conductors P analog signals corresponding to the integration of charges, during an integration period Ti, of the P pixels of the addressed line; at least one analog-digital converter for digitizing the signals provided by the column conductors for each addressed line, on completion of the integration period Ti, - N lines of P digital accumulator registers, an accumulator register of rank j in a line being able to accumulate N digital signals obtained during N successive integration periods and corresponding to the N pixels of like rank j of the various lines, in correspondence with the traveling of the linear image past the N lines of pixels during the N integration periods , - a circuit for extracting the digital values stored in a line of P registers having undergone N successive accumulations, these values representing an observed image line, - a sequencer able to successively apply to a line of P accumulator registers, during a series of N successive integration periods and in correspondence with the travel of the linear image, the digitized signals arising from each of the N lines of pixels, doing so for each of the lines of P registers, and able to reset to zero the content of the registers of the line whose content has been extracted, the order of succession of the lines whose content is extracted and then reset to zero in the course of the successive integration periods being a circular permutation.

The accumulator registers preferably comprise an output memory for containing the accumulated value of several signals corresponding to different lines, and an adder for adding the content of the output of the analog-digital converter to the content of the output memory and placing the result of the addition in this same memory. If the analog-digital conversion is done on B bits, the memory must have a sufficient number of bits to allow the accumulation, without saturation, of N times the maximum value (2B-1) of the conversion. For example, if N=32, the memory must comprise at least B+5 bits. Consequently provision may be made, this being advantageous, for the analog-digital converter to have a dynamic range several bits (preferably log2(N)) lower than the dynamic range of the digital signals that are extracted from the sensor: it is not necessary to convert the signals with a high-resolution converter.

The resolution will be obtained on account of the accumulation of N signals for each observed image line.

There are preferably P analog-digital converters, that is to say one per column conductor.

Other characteristics and advantages of the invention will become apparent on reading the detailed description which follows given with reference to the appended drawings in which: - Figure 1 represents an exemplary make-up of a pixel in CMOS technology; Figure 2 represents the structure of the electronic circuitry associated with a column conductor of the sensor.

- Figure 3 represents the general organization of the sensor according to the invention.

Figure 1 represents the structure of a CMOS technology active pixel comprising five transistors Tl to T5 and a photodiode PD; this pixel is of known type and can be used in the present invention. Within a matrix of N lines of P pixels, the pixel represented is assumed to be a pixel of rank j in the line of pixels of rank m. The structure and the manner of operation of the pixel are given by way of example to illustrate the inventio .

The photodiode is connected in series with the transistor Tl between ground and a reference power supply voltage Vref. The transistor can be turned on briefly, for a reset to zero of the charges of the photodiode, by a general reset to zero signal GSH acting simultaneously on all the pixels of the matrix before the start of an integration time.

Node Nl linking the photodiode and the transistor Tl accumulates charges in the course of the integration time. This node Nl can be linked briefly to a charge storage node N2 by the transistor T2, at the end of an integration time, by a transfer control signal GTRA acting simultaneously on all the pixels of the matrix.

The storage node N2 can be reset to the reference potential Vref (draining of the charges of node N2 ) by the transistor T3 which receives a brief control signal LRESm common to all the pixels of the line of rank m. The signals LRESm corresponding to the various lines (m = 1 to N) are emitted successively for the N lines on completion of an integration period Ti and while a following integration period is beginning.

Node N2 is additionally linked to the gate of the follower transistor T4 whose drain is at the potential Vref and whose source copies over (to within a gate source voltage drop) the potential taken by the gate, that is to say the potential of the storage node N2. The source of the transistor T4 is linked, by way of a line selection transistor T5, to a column conductor CCj common to all the pixels of one and the same column of rank j . The transistor T5 is turned on by a signal LSELm which is a signal for addressing the line of rank m and which is therefore common to all the pixels of one and the same line. The addressing signals LSELm for the various lines (m=l to N} are emitted successively on completion of an integration period Ti and while a following integration period is beginning.

The pixel operates in the following manner: after the end of an integration period Ti, the photodiodes have accumulated charges in a quantity proportional to the illumination that they have received. A general charge transfer signal GTRA is emitted briefly to transfer these charges from node Nl to node N2 where they remain stored for at least the time necessary for their readout.

Then a general signal GSH for defining the exposure time is briefly emitted. This signal resets to zero the charges stored in the photodiodes by bringing the latter to the potential Vref, and the integration of charges may begin only at the end of the signal GSH. These two signals GTRA and GSH relate to all the pixels of the matrix at once. Thereafter signals are emitted for reading out charges, line by line.

The first line receives a line selection signal which links the transistor T4 of the pixel to the corresponding column conductor CCj during the time required for readout and which then disconnects it with a view to reading out the charges of the following lines; all the lines are read out successively during the new integration period. Readout consists of a transmission to the column conductor of a potential copying over the potential of node N2. This readout is preferably done by double sampling in the following manner: the potential of the useful signal representing the photogenerated charges is firstly applied to the column conductor {and will be placed in memory in a first capacitor as will be seen further on); then the storage node N2 is drained of its charges by a brief signal LRESm for turning on the transistor T3 and the other transistors T3 of the same line, and the potential then taken by node N2, representing a black level potential, is copied over onto the column conductor CCj (and will be placed in memory in a second capacitor) .

The measurement of the charges photogenerated in a pixel of the first line is done by analog-digital conversion of the difference of the potentials of the useful signal and of the black level.

The second line is thereafter read out in the same manner, and so on and so forth, the N lines are read out during the charge integration period which terminates on the emission of a new transfer signal GTRA.

Figure 2 explains the operation of the invention and the case (not compulsory) where the charge readout is done by double sampling has been taken as an example .

The circuit of Figure 2 is the circuit which is associated with a column conductor CCj of rank j such - li ¬ as that which may be seen in Figure 1. The column conductor CCj is linked alternately, by respective on/off switches lj and K2j, to two storage capacitors Clj and C2j , which will store respectively the useful signal level and the black level. The on/off switches Klj and 2j are actuated at two successive instants separated by the duration of resetting to zero of the charges stored on node N2. The actuation signal for Klj is a signal SHR and the actuation signal for K2j is a signal SHS.

The storage capacitors Clj and C2j are linked between ground and each of the two inputs of an analog- digital converter ADCj . There is preferably one converter per column. For the duration of addressing of the line considered, the potential of node N2 of the pixel is copied over onto the column conductor CCj . At the start of this duration, the voltage level present on the column conductor is the useful level representing the charges photogenerated in the pixel of rank j of the addressed line. This voltage is applied to the capacitor Clj for a brief instant defined by the signal SHS (emitted successively for each of the addressed lines and common to all the columns) , after which the capacitor keeps this voltage. Then the signal LRESm is emitted so as to drain the charges of node N2 of the pixels of the line (specific signal for the addressed line) . The column conductor then takes a potential which defines the black level; then, for a brief instant defined by the signal SHR (emitted successively for each of the addressed lines and common to all the columns) this black level present on the column conductor is applied to the storage capacitor C2j which keeps it thereafter.

The capacitors Clj and C2j thereafter store, for the duration of an analog-digital conversion, the useful level and the black level corresponding to the addressed line. The analog-digital conversion which transforms the difference of the voltages present on the capacitors Clj and C2j into a digital value is performed. The converter executes the conversion betwee a start-of-conversion instant, postdating the signal SHR, and an end-of-conversion instant. A start- of-conversion signal START_CONV is therefore used to activate the converter, and an end-of-conversion signal END_CONV is used to trigger the storage in a memory MEMlj of the result of the conversion. The signals START_CONV and END_CONV, common to all the columns, are renewed at each new line readout.

The content stored in the memory MEMlj during the addressing of the line of pixels of rank m is therefore the result of the analog-digital conversion for column j and for the line of rank m.

The result of the conversion is accumulated, in a line of accumulator registers, with i-1 analogous digital values already added in this line of accumulator registers. Specifically, after i-1 successive integration periods following a reset to zero of the line of accumulator registers, this line contains the sum of the i-1 values corresponding to the observation of one and the same line of a scene by i-1 successive lines of pixels. At the ith integration period the content of the memories MEMlj (j=l to P) which represents the value of an ith line of pixels which has also observed the same line of a scene is added in the line of accumulator registers.

There are N lines of accumulator registers and the content of a pixel line addressed at a given instant after the end of the ith integration period is added to that of the lines of accumulator registers (and not another line) which has already received i-1 accumulated values after a reset to zero. The next line of pixels which is thereafter addressed, still following the ith integration period, is added to the next line of registers, and so on and so forth according to a circular permutation of the lines of registers. Circular permutation is understood to mean the fact that if the line of registers is the last line (the Nth line), then the next line is the first line. Likewise, if the addressed line of pixels is the Nth line of pixels, then the next line which is addressed is the first line of pixels.

In the continuous regime, among the N lines of accumulator registers, there is one and only one which has accumulated N-l successive values at the end of the ith integration period without having been reset to zero. This line then receives, at the end of the ith integration period, an Nth value originating from a line of pixels. This line of accumulator registers is then read out. It represents the digital value of the pixels of a line of the observed scene accumulated over the set of N lines in tandem with the synchronized relative displacement of the scene and of the sensor. After this readout, this line of registers is reset to zero. The other lines of accumulator registers continue their accumulation function until N values have been stored. At the (i+l)th integration period it is the next line of registers which is read out and reset to zero, and so on and so forth according to a circular permutation.

An accumulator register essentially comprises two elements which are an adder element ADDkj and a memory slot EM2kj; the index k denotes the rank of the line of accumulator registers (k varies from 1 to N) and the index j further denotes the rank in the line; in the line of registers there are therefore P adder elements ADDkj and P memory slots MEM2kj . In the whole set of N lines of registers, there are NxP adder elements and NxP memory slots.

The inputs of an adder element ADDkj receive the content of the memory MEMlj and the content of the memory MEM2kj respectively; the output of the adder element provides a new content to be stored in the memory slot MEM2kj .

The circuitry for accumulating the analog-digital conversion results comprises sequencing and addressing circuits, not represented in Figure 2, for performing the circular permutations indicated above. These circuits select the line of accumulator registers of rank k in which will be accumulated the values of a line of pixels of rank m addressed and converted at a given moment, at the end of an ith integration period. They therefore steer the content of the memory MEMl to the line of accumulator registers of rank k at this moment, and to a following register line at the end of a following integration period, and they activate the operations of addition and storage in the selected line of accumulator registers.

These sequencing circuits also designate which one of the lines of registers has to be read out at a given moment (that one which has undergone N accumulations after a reset to zero) and has to be reset to zero immediately after readout. They transmit to a general output of the matrix of accumulator registers the output of the memory slots of this line of registers thus selected. A value is thus output at each integration period Ti and the periodicity of selection of one and the same line of registers so as to provide an output value is N elementary integration periods.

The capacity (in number of bits) of each memory slot MEM2kj is such that it is possible to accumulate in this slot the sum of N digital values corresponding to a pixel. Assuming that the dynamic range of the analog-digital converter is B bits, the capacity of the memory MEMl is B bits, but the capacity of the accumulator registers is greater and is at least B+b bits where b {an integer) is such that 2 _1 Figure 3 represents the general architecture of the image sensor according to the invention. Depicted therein are the matrix MC of N lines of P photosensitive active pixels, addressable by a line decoder DLC, the analog-digital converter ADC which comprises, for each column, an elementary converter such as that which is represented at the top of Figure 2 (on/off switches, capacitors Clj, C2j, converter ADCj , memory MEMlj) .

Also depicted therein are the matrix MT of N lines of P accumulator registers such as that which is represented at the bottom of Figure 2 (adder ADDkj and memory MEM2kj } .

A first line decoder DLRl makes it possible to select a line of accumulator registers of rank k in correspondence with a line of pixels of rank m, the correspondence being the circular permutation explained above. This selection by the decoder DLRl acts so as to apply to the register the content of the memories MEMlj which constitute the output of the converter ADC. The decoder DLRl selects N successive lines on completion of an integration period, during the addressing of the N lines of pixels.

A second line decoder DLR2 acts so as to select that one of the lines of accumulator registers which has terminated N successive accumulations after a reset to zero. The content of the registers of the line thus selected by the decoder DLR2 is extracted and constitutes the sensor output signal. The extraction is done for example by placing the content of the registers of the selected line in an output register RS which will thereafter be read out. The extraction is done, as indicated above, after the Nth step of accumulation in the selected line, and it is followed by a reset to zero of the content of the accumulator registers of the selected line. The order of selection of the lines is a circular permutation, as indicated above .

The whole set of line decoders and the readout register is controlled by a sequencer SEQ which establishes the circular permutations. The sequencer also produces all the control signals required for the lines of pixels and for the converter ADC.

Claims (6)

1. A method of image capture, of the traveling and signal-summing type, for the synchronized readout of one and the same image line successively by N lines of P photosensitive pixels and the pixel by pixel summation of the signals read out by the various lines, characterized in that: - on completion of each integration period of a series of charge integration periods, the signals arising from the N lines of pixels are digitized by an analog-digital converter (ADC) , the digitized signals of a line of pixels are accumulated in a chosen line of a transfer matrix (MT) which comprises N lines of P accumulator registers, doing so for the N lines of pixels and the N lines of the transfer matrix, while modifying at each integration period the correspondence between the chosen line of the transfer matrix and the line of pixels, in synchronism with the traveling of the image past the sensor in such a manner that a line of registers of the transfer matrix receives and accumulates successively in the course of N integration periods the digitized signals of N lines of pixels having seen one and the same image line, - after N integration periods the content of a determined line of registers, representing an observed image line, is extracted and the registers of this line are reset to zero, - at each following integration period it is the content of another line of registers, according to a circular permutation of the N lines, which is extracted and reset to zero, the line extracted and reset to zero being, on completion of each integration period, that which has undergone N accumulations after a reset to zero .

2. The method of image capture as claimed in claim 1, in which a pixel of rank j in a line is made up of a circuit with MOS transistors comprising an output linked to a column conductor (CCj) of rank j common to the N pixels of rank j of the various lines, characterized by the following operations: - simultaneous integration of charges in the NxP pixels, repeated during successive integration periods; - successive addressing of each of the N lines of pixels at the end of an ith integration period so as to apply to the column conductors on completion of the ith integration period successively for each addressed line P analog signals corresponding to the integration of charges in the P pixels of the addressed line; - analog-digital conversion so as to digitize the P analog signals present on the column conductors in the course of each line addressing, and provide P digital values corresponding to an addressed line of rank m; - accumulation of the digital value corresponding to the pixel of rank j of an addressed line, in an accumulator register (ME 2kj ) of rank j of a line of registers of a matrix (MT) of N lines of P accumulator registers, - in the course of the (i+l)th integration period, accumulation in this same accumulator register (MEM2kj) of a digital value corresponding to a pixel of rank j of another line of pixels, in correspondence with the traveling of the linear image past the N lines of pixels, - on completion of the (i+l)th integration period, selection of one line from among N, the selected line being a line which has undergone N successive accumulations after a reset to zero of the content of the accumulator registers of this line, extraction of the digital values accumulated in the registers of this line, representing an observed image line, and resetting to zero of the registers of this line with a view to a new series of N integration periods for this line, circular permutation of the order of the register lines which are selected for an extraction and a resetting to zero on completion of the successive integration periods.

3. An image sensor, of the traveling and summing type, allowing the synchronized readout of one and the same image line successively by N lines of P photosensitive pixels and the pixel by pixel summation of the signals read out by the various lines, a pixel of rank j in a line being made up of a circuit with MOS transistors comprising an output linked to a column conductor (CCj) of rank j common to the N pixels of rank j of the various lines, the sensor being characterized in that it comprises: - a successive addressing circuit for each of the N lines of pixels for applying to the column conductors P analog signals corresponding to the integration of charges, during an integration period Ti, of the P pixels of the addressed line; at least one analog-digital converter for digitizing the signals provided by the column conductors for each addressed line, on completion of the integration period Ti, - N lines of P digital accumulator registers, an accumulator register of rank j in a line being able to accumulate N digital signals obtained during N successive integration periods and corresponding to the N pixels of like rank j of the various lines, in correspondence with the traveling of the linear image past the N lines of pixels during the N integration periods, - a circuit (DLR2, RS) for extracting the digital values stored in a line of P registers having undergone N successive accumulations, these values representing an observed image line, - a sequencer (SEQ) able to successively apply to a line of P accumulator registers, during a series of N successive integration periods and in correspondence with the travel of the linear image, the digitized signals arising from each of the N lines of pixels, doing so for each of the lines of P registers, and able to reset to zero the content of the registers of the line whose content has been extracted, the order of succession of the lines whose content is extracted and then reset to zero in the course of the successive integration periods being a circular permutation.

4. The image sensor as claimed in claim 3, characterized in that the accumulator registers comprise an output memory (MEM2kj) for containing the accumulated value of several signals corresponding to different lines, and an adder (ADDkj) for adding the content of the output of the analog-digital converter (MEMlj, ADC) to the content of the output memory and. placing the result of the addition in this memory.

5. The image sensor as claimed in claim 4, characterized in that the analog-digital conversion is done on B bits, and the memory (MEM2kj) has a sufficient number of bits to allow the accumulation, without saturation, of N times the maximum output value 2B-1 of the converter.

6. The linear image sensor as claimed in claim 5, characterized in that the memory has a dynamic range of at least B+b bits where b, an integer, lies between logjtN-l) and log2(N). For the Applicant, C: 68002