JPH0530430A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To surely reduce output noise including high frequency noise of an output amplifier for the solid-state image pickup element. CONSTITUTION:A noise signal outputted from the solid-state image pickup element for a feed-through period is accumulated by an adder 5 and a buffer memory 7 and the signal for the signal period outputted from the solid-state image pickup element is accumulated by the adder 5 and the buffer memory 7 and the accumulated noise signal and the accumulated signal are subjected to subtraction processing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device, and more particularly to a solid-state image pickup device for performing a CDS process for reducing output noise of a solid-state image pickup device.

[0002]

2. Description of the Related Art A conventional means for reducing output noise of a solid-state image pickup device in a solid-state image pickup device such as an electronic still camera will be described below.

First, the structure and operation of an electronic still camera, which is an example of a solid-state image pickup device, will be described. Figure 4
2 is a block diagram of an electronic still camera, in which 201 is a lens, 202 is a diaphragm, 203 is a shutter, and 204 is a shutter diaphragm drive circuit. Reference numeral 101 is a solid-state image sensor for converting an image into an electric signal, 205 is a solid-state image sensor drive circuit, and 206 is a clock generation circuit. A signal processing circuit 207 obtains a luminance signal and a color-difference line-sequential signal by performing signal processing on the output obtained from the solid-state imaging device 101. Reference numeral 208 denotes an FM modulation circuit that FM-modulates the luminance signal and the color difference line sequential signal. A REC amplifier 209 amplifies the FM-modulated signal so that it can be magnetically recorded. 210 is a magnetic head, and 211 is a magnetic sheet that is a recording medium. 212
Is a motor for rotating the magnetic sheet 211, 213 is a motor servo circuit, and 214 is a system control circuit for controlling the operation of the entire system. Reference numeral 215 is a shutter release switch, and a series of still image capturing sequences is performed in synchronization with the operation of turning on the switch.

FIG. 5 shows an imaging sequence of an electronic still camera. In FIG. 5, at time T1, the unnecessary charges in the A field of the solid-state image sensor 101 are transferred and removed while the shutter 203 remains closed. Similarly, from time T2, B
Transfer and remove unnecessary charges in the field. Next time T3
The solid-state image sensor 1 with the shutter 203 opened between T4 and T4.
01 is exposed to accumulate signal charges. Next, the shutter 203 is closed, and the electric field of the A field is read out and the signal processed signal is recorded in the nth track of the magnetic sheet 211 between times T4 and T5. Next, between times T5 and T6, the electric field of the B field is read out and the signal processed is recorded on the (n + 1) th track of the magnetic sheet 211.

Next, the structure and operation of the solid-state image sensor used in the electronic still camera will be described.

FIG. 6 shows an interline CCD as an example of a solid-state image pickup device often used in electronic still cameras.
FIG. In FIG. 6, 101 is a solid-state image sensor that is an interline CCD, 102 is a photodiode that converts light into electric charge and accumulates, 103 is a vertical that vertically transfers the electric charge transferred from the photodiode 102 to 1H step by step. It is a CCD. V1 to V4 are vertical CCD 10
3 is a transfer electrode, and V1 also serves as a transfer gate for transferring the charges in the odd rows of the photodiodes to the vertical CCD 103. Similarly, V3 is a transfer gate corresponding to the photodiodes in even rows. Vertical CCD 103
Are driven by four-phase transfer pulses. 104 is a vertical CCD
It is a horizontal CCD that horizontally transfers the charges transferred from the 103 to 1H by one stage. H1 and H2 are horizontal CCD 104
, And is driven by a two-phase pulse. 105
Is an FDA (Floating Diffus) that converts electric charge into voltage and outputs it.
ion Amplifier). A floating diffusion layer (not shown) is provided at the final stage of the horizontal CCD 104, and the potential change at the final stage is detected by the output amplifier 105. Such a charge detection amplifier is called FDA. Vout is an output terminal. Reference numeral R is a reset gate electrode for removing the charges that have been read and resetting the output potential to the reference potential every clock cycle.

FIG. 7 is a diagram showing the read timing of the interline CCD of FIG.

At time t1, the vertical blanking period starts,
At time t2, V1 becomes high level and the transfer gate is opened, so that the charges in the odd rows of the photodiode 102 are transferred to the vertical CCD 103. Vertical CC from time t3
The charge of D103 is transferred toward the one-stage horizontal CCD 104 in one horizontal period. The charges transferred to the horizontal CCD 104 are transferred at high speed, converted into a voltage by the FDA 105, and output. The reading of charges from all odd-numbered lines ends at time t4. Next, at time t5 of the vertical blanking period, V3 becomes high level, and the charges of the photodiodes 102 on even lines are transferred to the vertical CCD 103. At time t6, the charges are transferred to the one-line horizontal CCD 104 for one horizontal period and similarly transferred at high speed. Is output.

Since the output amplifier of the solid-state image pickup device as described above generates a peculiar noise called reset noise, the noise is usually reduced by using a technique called CDS (Corelated Double Sampling).

FIG. 8 is a timing chart for reading charges from the horizontal CCD 104. As shown in FIG. 8C, the reset pulse R resets the output potential of the FDA 105 to the reference potential. When the reset pulse R becomes low level, the floating diffusion layer of the FDA 105 enters a floating state, and the output potential of the FDA 105 is maintained at a predetermined voltage determined by the capacitance division ratio of the floating capacitance of the floating diffusion layer. This period is called a feedthrough period.

Next, as shown in FIG. 8B, when the horizontal transfer pulse H2 becomes low level, the signal charge is transferred to the final stage having the floating diffusion layer and the signal charge is divided by the capacitance of the floating diffusion layer. The voltage change of is output from the FDA 105. However, the potential during the feedthrough period is affected by thermal noise during the reset period as shown in FIG.
It varies for each pixel period. Then, the potential of the signal period also varies accordingly. Such FDA-specific noise is called reset noise. This noise can be removed by taking the difference in potential between the signal period and the feedthrough period preceding it. Such a method is called CDS.

FIG. 9 is a diagram for explaining the configuration of a CDS circuit for performing CDS. As shown in FIG. 9A, the solid-state imaging device 10
The output signal of 1 is subjected to noise removal by the CDS circuit 301 and then sent to the subsequent stage. The configuration of FIG. 9B or 9C is often used for the configuration of the CDS circuit 301. In FIG. 9B, the CDS circuit 301 is composed of a clamp circuit 302 and a sample hold circuit 303.
The pulse of P1 is used for clamping and the pulse of P2 is used for sampling and holding.
8 (e) and 8 (f). First, the potential in the feedthrough period is clamped by the clamp circuit 302 with the pulse P1, the potential is fixed to a predetermined potential to eliminate the influence of reset noise, and then the potential in the signal period is sampled and held by the sample hold circuit 303 with the pulse P2. To get a noise free signal.

In FIG. 9C, the CSD circuit 301 comprises a first sample hold circuit 304, a second sample hold circuit 305, a third sample hold circuit 306, and a subtraction circuit 307. A pulse P2 is applied to the first sample hold circuit 304 and the third sample hold circuit 306. A pulse P1 is applied to the second sample hold circuit 305. P1, P
The timing of No. 2 is shown in FIGS. First, the potential in the feed-through period is sampled and held by the second sample and hold circuit 305 by the pulse P1 and delayed. Next, the potential of the signal period and the potential of the delayed feed-through period are sampled and held by the first sample hold circuit 304 and the third sample hold circuit 306 at the timing of the pulse P2, and the subtraction circuit 30 is performed.
The reset noise component is removed by subtracting at 7.

[0014]

CCD in principle
Although the CDS is supposed to be able to completely remove the noise, the noise of the solid-state image sensor cannot be completely removed.
The first cause is that the number of pixels in the recent solid-state imaging device is large and the reading frequency is high, so that the feed-through period and the signal period are very short, and it is difficult to perform clamp and sample hold accurately. The second cause is that noise in a high band other than reset noise is added by the FDA, so that the clamp circuit or the sample hold circuit clamps or holds the noise added uncorrelated with the reset noise. Will occur.

[0015]

A solid-state image pickup device of the present invention cumulatively adds noise signals in a feedthrough period output from a solid-state image pickup device and cumulatively adds signals in a signal period output from the solid-state image pickup device. Then, the cumulative addition value of the noise signal and the cumulative addition value of the signal are subtracted.

[0016]

[Operation] According to the present invention, by cumulatively adding the electric potentials of the feedthrough period of the solid-state imaging device and the signal period,
High frequency noise is averaged and reduced, and low frequency noise such as reset noise is removed by subtracting the cumulative addition value of the noise signal and the cumulative addition value of the signal.

[0017]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. In FIG. 1, 1 is an A / D conversion circuit for converting the output of the solid-state image sensor into a digital value, 2 is an improved CDS circuit, a sign inverter 3, a switch 4, an adder 5, a switch 6, a buffer memory 7, It is composed of a latch circuit 8.

FIG. 2 is an operation timing chart of the embodiment shown in FIG. The operation of this embodiment will be described below with reference to FIGS. 1 and 2. During the feedthrough period, as shown in Fig. 2 (c),
The code switching timing pulse goes low, and the switch 4 is switched to the A side. The input of the buffer memory 7 is switched to the D side. Therefore, the signal of the feedthrough period whose sign is inverted is input to the adder 5, and the output of the adder 5 is input to the buffer memory 7. The output of the buffer memory 7 is always connected to the other input of the adder 5. In this state, the feedthrough level inverted in synchronization with the write timing pulse is written to the buffer memory 7 N times, but the output of the buffer memory 7 is input to the adder 5 so that it is inverted at the end of the feedthrough period. The cumulative addition value of the feedthrough level is stored in the buffer memory 7.

Before the next signaling period begins, FIG.
As shown in (c), the code switching timing pulse becomes high level and the switch 4 is switched to the B side. The signal level that is not inverted this time in synchronization with the write timing pulse N times in the signal period is the buffer memory 7
Is cumulatively added to. In this state, the output of the buffer memory 7 is latched by the latch circuit 8 with the latch timing pulse, so that the difference between the cumulative addition value of the signal level and the feedthrough level, that is, the signal from which the reset noise is removed is latched. FDA high-frequency noise is averaged by cumulative addition, so its effect is 1 / square root of N.
Is reduced to.

The value of the buffer memory 7 is reset to zero before the start of the next feedthrough period. That is, first, the input of the buffer memory 7 is switched to C by the switch 6 in synchronization with the buffer memory input switching pulse. Data zero is set in C. Next, zero is written in the buffer memory 7 and reset in synchronization with the write timing pulse. Prior to the start of the next feedthrough period, the input of the buffer memory is switched to D by the switch 6 and is again connected to the output of the adder 5. The operation of the next signal period is repeated as described above.

The output latched in the latch 8 is again D / A
It may be converted or digitally processed as it is. Further, by inverting the polarity of the code switching timing pulse, the polarity of the output signal can be inverted.

Note that in still video, it is not necessary to read the output of the solid-state image pickup device at high speed, and the operation of the above-described embodiment is performed at low speed, so that the low-speed A / D
Even if a converter or a memory is used, noise can be surely removed.

FIG. 3 shows an example of timing for lowering the horizontal transfer frequency of the solid-state image pickup device. For comparison, FIG.
(A) to (d) show conventional timing examples. A signal is output in synchronization with the horizontal transfer pulse H2 ′ of FIG. 3 (e), which has a shorter cycle than the horizontal transfer pulse H2, but the reset period does not necessarily need to be long, so the reset pulse R ′ (see FIG. 3 (f) (high level period) is not changed. Therefore, the feedthrough period and the signal period can be made sufficiently long. The output signal of the solid-state image sensor of FIG. 3 (g) becomes an output signal in which high frequency noise and reset noise as shown in FIG. 3 (h) are reduced and removed by the present invention. The result latched by the latch circuit 8 is stored in a frame memory (not shown), and after the digital signal processing, the time axis is restored to the video rate and recorded on the magnetic sheet 211. In the case of a card camera or the like, it is not necessary to restore the time axis to the video rate, and digital data may be stored in the memory card as it is.

[0025]

As described in detail above, according to the present invention, the output noise including the high frequency noise of the output amplifier of the solid-state image pickup device is surely reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is an operation timing chart of the embodiment of FIG.

FIG. 3 is an example of timing for lowering the horizontal transfer frequency of the solid-state image sensor.

FIG. 4 is a block diagram of an electronic still camera.

FIG. 5 is an imaging sequence of an electronic still camera.

FIG. 6 is an explanatory diagram of an interline CCD as an example of a solid-state image sensor often used in an electronic still camera.

FIG. 7 is a diagram showing the read timing of the interline CCD of FIG.

FIG. 8 is a timing chart for reading charges from the horizontal CCD 104.

FIG. 9 is a diagram illustrating a configuration of a CDS circuit that performs CDS.

[Explanation of symbols]

1 AD conversion circuit for converting output of solid-state imaging device into digital value 2 Improved CDS circuit 3 Sign inverter 4 switch 5 adder 6 switch 7 buffer memory 8 latch circuit

Claims (1)

Claim: What is claimed is: 1. A noise signal output from a solid-state imaging device is cumulatively added, and a noise signal output from the solid-state imaging device is cumulatively added to obtain a noise signal. A solid-state imaging device that performs subtraction processing on an addition value and a cumulative addition value of signals.