IL134362A0 - Data processing unit with digital signal processing capabilities - Google Patents

Data processing unit with digital signal processing capabilities

Info

Publication number
IL134362A0
IL134362A0 IL13436298A IL13436298A IL134362A0 IL 134362 A0 IL134362 A0 IL 134362A0 IL 13436298 A IL13436298 A IL 13436298A IL 13436298 A IL13436298 A IL 13436298A IL 134362 A0 IL134362 A0 IL 134362A0
Authority
IL
Israel
Prior art keywords
digital signal
processing unit
data processing
signal processing
capabilities
Prior art date
Application number
IL13436298A
Other languages
English (en)
Original Assignee
Infineon Technologies Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Corp filed Critical Infineon Technologies Corp
Publication of IL134362A0 publication Critical patent/IL134362A0/xx

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/60—Memory management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30105—Register structure
    • G06F9/30112—Register structure comprising data of variable length
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G06F9/30123—Organisation of register space, e.g. banked or distributed register file according to context, e.g. thread buffers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/345—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes of multiple operands or results
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3816—Instruction alignment, e.g. cache line crossing

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Executing Machine-Instructions (AREA)
IL13436298A 1997-09-12 1998-09-04 Data processing unit with digital signal processing capabilities IL134362A0 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/928,764 US6260137B1 (en) 1997-09-12 1997-09-12 Data processing unit with digital signal processing capabilities
PCT/US1998/018574 WO1999014663A2 (en) 1997-09-12 1998-09-04 Data processing unit with digital signal processing capabilities

Publications (1)

Publication Number Publication Date
IL134362A0 true IL134362A0 (en) 2001-04-30

Family

ID=25456710

Family Applications (1)

Application Number Title Priority Date Filing Date
IL13436298A IL134362A0 (en) 1997-09-12 1998-09-04 Data processing unit with digital signal processing capabilities

Country Status (7)

Country Link
US (1) US6260137B1 (ko)
EP (1) EP1019805B1 (ko)
JP (1) JP2001516916A (ko)
KR (1) KR20010030593A (ko)
DE (1) DE69824193T2 (ko)
IL (1) IL134362A0 (ko)
WO (1) WO1999014663A2 (ko)

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US6690419B1 (en) 1997-07-15 2004-02-10 Silverbrook Research Pty Ltd Utilising eye detection methods for image processing in a digital image camera
US6948794B2 (en) 1997-07-15 2005-09-27 Silverbrook Reserach Pty Ltd Printhead re-capping assembly for a print and demand digital camera system
AUPO802797A0 (en) 1997-07-15 1997-08-07 Silverbrook Research Pty Ltd Image processing method and apparatus (ART54)
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US7724282B2 (en) 1997-07-15 2010-05-25 Silverbrook Research Pty Ltd Method of processing digital image to correct for flash effects
US7110024B1 (en) 1997-07-15 2006-09-19 Silverbrook Research Pty Ltd Digital camera system having motion deblurring means
US6624848B1 (en) 1997-07-15 2003-09-23 Silverbrook Research Pty Ltd Cascading image modification using multiple digital cameras incorporating image processing
US6985207B2 (en) 1997-07-15 2006-01-10 Silverbrook Research Pty Ltd Photographic prints having magnetically recordable media
US6879341B1 (en) 1997-07-15 2005-04-12 Silverbrook Research Pty Ltd Digital camera system containing a VLIW vector processor
US6230257B1 (en) 1998-03-31 2001-05-08 Intel Corporation Method and apparatus for staggering execution of a single packed data instruction using the same circuit
US6230253B1 (en) * 1998-03-31 2001-05-08 Intel Corporation Executing partial-width packed data instructions
AUPP702098A0 (en) 1998-11-09 1998-12-03 Silverbrook Research Pty Ltd Image creation method and apparatus (ART73)
US7107302B1 (en) * 1999-05-12 2006-09-12 Analog Devices, Inc. Finite impulse response filter algorithm for implementation on digital signal processor having dual execution units
US6820189B1 (en) 1999-05-12 2004-11-16 Analog Devices, Inc. Computation core executing multiple operation DSP instructions and micro-controller instructions of shorter length without performing switch operation
US7111155B1 (en) 1999-05-12 2006-09-19 Analog Devices, Inc. Digital signal processor computation core with input operand selection from operand bus for dual operations
US6859872B1 (en) 1999-05-12 2005-02-22 Analog Devices, Inc. Digital signal processor computation core with pipeline having memory access stages and multiply accumulate stages positioned for efficient operation
EP2267596B1 (en) 1999-05-12 2018-08-15 Analog Devices, Inc. Processor core for processing instructions of different formats
AUPQ056099A0 (en) 1999-05-25 1999-06-17 Silverbrook Research Pty Ltd A method and apparatus (pprint01)
GB2352065B (en) * 1999-07-14 2004-03-03 Element 14 Ltd A memory access system
US6539467B1 (en) * 1999-11-15 2003-03-25 Texas Instruments Incorporated Microprocessor with non-aligned memory access
FR2802321A1 (fr) * 1999-12-09 2001-06-15 Ass Pour La Promotion De La Mi Processeur configurable par l'utilisateur
US6829696B1 (en) * 1999-12-30 2004-12-07 Texas Instruments Incorporated Data processing system with register store/load utilizing data packing/unpacking
US6453405B1 (en) * 2000-02-18 2002-09-17 Texas Instruments Incorporated Microprocessor with non-aligned circular addressing
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US7120781B1 (en) * 2000-06-30 2006-10-10 Intel Corporation General purpose register file architecture for aligned simd
US7430578B2 (en) * 2001-10-29 2008-09-30 Intel Corporation Method and apparatus for performing multiply-add operations on packed byte data
JP4624098B2 (ja) * 2002-05-24 2011-02-02 エヌエックスピー ビー ヴィ プロセッサのアドレス発生ユニット
JP3958662B2 (ja) * 2002-09-25 2007-08-15 松下電器産業株式会社 プロセッサ
EP1701249A1 (en) * 2005-03-11 2006-09-13 Interuniversitair Microelektronica Centrum Vzw Ultra low power ASIP (Application-Domain specific Instruction-set Processor) microcomputer
US7788420B2 (en) * 2005-09-22 2010-08-31 Lsi Corporation Address buffer mode switching for varying request sizes
US20100141668A1 (en) * 2006-10-26 2010-06-10 Nxp, B.V. Address calculation unit
JP5327432B2 (ja) * 2008-08-11 2013-10-30 セイコーエプソン株式会社 信号処理プロセッサ及び半導体装置
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Also Published As

Publication number Publication date
DE69824193D1 (de) 2004-07-01
EP1019805B1 (en) 2004-05-26
DE69824193T2 (de) 2005-05-19
US6260137B1 (en) 2001-07-10
EP1019805A2 (en) 2000-07-19
WO1999014663A3 (en) 1999-08-05
JP2001516916A (ja) 2001-10-02
KR20010030593A (ko) 2001-04-16
WO1999014663A2 (en) 1999-03-25

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