IL103382A - Line buffer for cache memory - Google Patents

Line buffer for cache memory

Info

Publication number
IL103382A
IL103382A IL10338292A IL10338292A IL103382A IL 103382 A IL103382 A IL 103382A IL 10338292 A IL10338292 A IL 10338292A IL 10338292 A IL10338292 A IL 10338292A IL 103382 A IL103382 A IL 103382A
Authority
IL
Israel
Prior art keywords
data
storage means
cache memory
fields
tag
Prior art date
Application number
IL10338292A
Other languages
English (en)
Hebrew (he)
Other versions
IL103382A0 (en
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of IL103382A0 publication Critical patent/IL103382A0/xx
Publication of IL103382A publication Critical patent/IL103382A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855—Overlapped cache accessing, e.g. pipeline
    • G06F12/0859—Overlapped cache accessing, e.g. pipeline with reload from main memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
IL10338292A 1991-10-11 1992-10-08 Line buffer for cache memory IL103382A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US77526591A 1991-10-11 1991-10-11

Publications (2)

Publication Number Publication Date
IL103382A0 IL103382A0 (en) 1993-03-15
IL103382A true IL103382A (en) 1995-03-15

Family

ID=25103861

Family Applications (1)

Application Number Title Priority Date Filing Date
IL10338292A IL103382A (en) 1991-10-11 1992-10-08 Line buffer for cache memory

Country Status (5)

Country Link
US (1) US5367660A (fr)
JP (1) JPH05216756A (fr)
FR (1) FR2682506B1 (fr)
GB (1) GB2260628A (fr)
IL (1) IL103382A (fr)

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US5737550A (en) * 1995-03-28 1998-04-07 Advanced Micro Devices, Inc. Cache memory to processor bus interface and method thereof
DE19527592C2 (de) * 1995-07-28 2003-07-17 Ibm Cache-Anordnung für einen Prozessor und Verfahren zur Eingabe von Daten in einen Cachespeicher
US5918247A (en) * 1995-10-27 1999-06-29 Motorola, Inc. Method for canceling partial line fetch for cache when new data is requested during current fetch and invalidating portion of previously fetched data
US6065108A (en) * 1996-01-24 2000-05-16 Sun Microsystems Inc Non-quick instruction accelerator including instruction identifier and data set storage and method of implementing same
JP3429948B2 (ja) * 1996-04-10 2003-07-28 株式会社日立製作所 組込み型ｃｐｕ用制御装置
US5765190A (en) * 1996-04-12 1998-06-09 Motorola Inc. Cache memory in a data processing system
US5822763A (en) * 1996-04-19 1998-10-13 Ibm Corporation Cache coherence protocol for reducing the effects of false sharing in non-bus-based shared-memory multiprocessors
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US5835929A (en) * 1996-05-20 1998-11-10 Integrated Device Technology, Inc. Method and apparatus for sub cache line access and storage allowing access to sub cache lines before completion of a line fill
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US6523095B1 (en) * 1996-07-22 2003-02-18 Motorola, Inc. Method and data processing system for using quick decode instructions
US6212605B1 (en) * 1997-03-31 2001-04-03 International Business Machines Corporation Eviction override for larx-reserved addresses
US5974497A (en) * 1997-05-22 1999-10-26 Dell Computer Corporation Computer with cache-line buffers for storing prefetched data for a misaligned memory access
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US6209068B1 (en) * 1997-12-29 2001-03-27 Intel Corporation Read line buffer and signaling protocol for processor
US6321303B1 (en) 1999-03-18 2001-11-20 International Business Machines Corporation Dynamically modifying queued transactions in a cache memory system
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US6311254B1 (en) 1999-03-18 2001-10-30 International Business Machines Corporation Multiple store miss handling in a cache memory memory system
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US6782452B2 (en) * 2001-12-11 2004-08-24 Arm Limited Apparatus and method for processing data using a merging cache line fill to allow access to cache entries before a line fill is completed
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Also Published As

Publication number Publication date
GB2260628A (en) 1993-04-21
GB9214921D0 (en) 1992-08-26
JPH05216756A (ja) 1993-08-27
FR2682506A1 (fr) 1993-04-16
FR2682506B1 (fr) 1997-03-14
IL103382A0 (en) 1993-03-15
US5367660A (en) 1994-11-22

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