IES970827A2 - Manufacture of interface circuits - Google Patents

Manufacture of interface circuits

Info

Publication number
IES970827A2
IES970827A2 IE970827A IES970827A IES970827A2 IE S970827 A2 IES970827 A2 IE S970827A2 IE 970827 A IE970827 A IE 970827A IE S970827 A IES970827 A IE S970827A IE S970827 A2 IES970827 A2 IE S970827A2
Authority
IE
Ireland
Prior art keywords
test
board
pins
circuit
contact
Prior art date
Application number
IE970827A
Inventor
Michael Byrne
Michael Guinee
Peter Doyle
James Duignan
Original Assignee
E I Tech Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by E I Tech Ltd filed Critical E I Tech Ltd
Priority to IE970827A priority Critical patent/IES970827A2/en
Priority to GB9725173A priority patent/GB2331840A/en
Publication of IES78835B2 publication Critical patent/IES78835B2/en
Publication of IES970827A2 publication Critical patent/IES970827A2/en

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/10Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/12Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns
    • H05K3/1216Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns by screen printing or stencil printing
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2801Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
    • G01R31/281Specific types of tests or tests for a specific type of fault, e.g. thermal mapping, shorts testing
    • G01R31/2812Checking for open circuits or shorts, e.g. solder bridges; Testing conductivity, resistivity or impedance

Abstract

A manufacturing process for interface boards (60) involves screen printing (3) when the board is in position on a nest having a flat upper surface with vacuum holes and alignment is ensured by abutment with movable edge guides (33). There is reflow curing of solder paste at a gradient of less than 1.5°C per second. A test station (60) holds the circuit at a particular position at which lower and upper test pins come into contact with an edge connector (62). The signals are transmitted to a test controller via bridging pins (68,69) to ensure integrity of signal transmission from moveable probes. Shorting probes (55) are inserted into socket connectors (61) to ensure comprehensive continuity testing from conductors in the sockets (61) to the edge connectors (62).<Fig.1>

Description

The invention relates to manufacture of interface circuits which support interconnection of different systems, usually an associated system and an external system.
Such interface circuits differ from conventional circuits in that they have relatively few components and indeed those components which are part of the circuit are passive. However, the circuits include a number of connectors for interconnection of different systems such as edge connectors with gold-plated “fingers”, and sockets to receive plugs of external systems. These connectors are quite bulky and it is particularly difficult to detect faults which may lie underneath the bulk plastics casings of the connectors. Another aspect of interface circuits is that quality control is particularly important as a fault which arises can affect not only one system but all systems which the circuit interconnects.
Despite stringent quality control requirements, the commercial margins obtained for production of such circuits in a high volume are quite slim. It is therefore important that the manufacturing process provides both high efficiency and comprehensive quality control. At the same time it is not generally feasible to invest very heavily in dedicated quality control equipment because the design of the circuit changes frequently, and thus the equipment must be very flexible.
Heretofore, there have been many advances in production and testing of circuits generally and these are described, for example, in WO 95/12851, WO 93/23981, US 5405074, US 5260548, US 4690569, and WO 83/04315. All of these specifications describe various aspects of soldering and testing which generally improve upon the previous state of the art, however, little has been done to address the particular problems of producing interface circuits in an efficient manner with comprehensive quality control, with frequent design changes. The approach has generally been to invest heavily in expensive equipment which may include optical measuring systems. However, where there are frequent design changes and the volumes are vayiabl>j'«oueh systems'Bfcnot paiticulariy· OPBN TO PUBLIC INSPECTION UNDER ϋ arc ..lb. dta SECTION 28 AND RULE 23 JNL. No...1.1SA.....OF AS $97 08 2 Ί -2cost-effective and some faults may not be located under connectors. There is therefore a need for an improved manufacturing process for these situations.
According to the invention, there is provided a method of manufacturing an interface circuit comprising the steps of> at a screen printing station, mounting a support nest associated with a printed circuit board on a universal base, the nest comprising:a plate with a substantially flat upper surface, and movable edge guides mounted for movement into position alongside the upper surface to align a board for screen printing; conveying the board over the nest, detecting presence of the board, and conveying the board into contact with the edge guides; screen printing solder paste onto the board; placing components on the solder paste; curing the solder in a reflow oven to produce a soldered circuit; and testing the soldered circuit by placing it in a jig at an aligned position at which lower embedded test signal pins contact edge connector conductors and upper test signal pins descend to contact the conductors to complete a testing circuit, and a test controller directing short circuit, continuity, and component tests via said test signal pins.
In one embodiment, position of the board for screen printing is detected by a sensor mounted within the nest. 97082 7 -3Preferably, the flat upper surface of the nest is on an upper wall, and the nest also comprises a spaced-apart lower wall to which the sensor is connected.
In one embodiment, the solder is cured with a ramping temperature gradient of less than 1,5°C per second.
In another embodiment, the shorting test is performed by insertion of a shorting probe into socket connectors on the board to complete a test circuit between the probe and the lower and upper test signal pins in contact with the edge connector. Ideally, the shorting probe has passive circuit components connected to teeth for contact with conductors of the connector sockets.
In one embodiment, the test signals are transmitted to a test controller via mutually resilient bridging pins which move into contact with each other when the upper test signal pins are brought into contact with the edge connector.
Ideally, the bridging pins comprise movable bridging pins mounted on a carriage which also carries the upper test signal pins, and resilient pins which are mounted in a base of the testing station.
In one embodiment, the test station is diagnosed at regular intervals by insertion of a test board having a fully conductive surface and sockets in a similar arrangement to a circuit under test, transmitting a test signal to each test pin, and detecting a return signal at each of the other test pins.
The invention will be more clearly understood from the following description of some embodiments thereof, given by way of example only with reference to the accompanying drawings in which:Fig. 1 is a flow diagram illustrating an interface circuit manufacturing process of the invention; S87082 7 -4Fig. 2 is a perspective view from above showing a screen printing station used in the process; Figs. 3, 4, 5 are plan views illustrating various parts of the screen printing station; Figs. 6 and 7 are diagrammatic views showing screen printing; Fig. 8 is a diagram illustrating movement of a circuit board into position for screen printing; Figs. 9 and 10 are perspective views showing a testing station used in the process; Figs. 11 and 12 are diagrammatic side views illustrating movement of test probes into position in the testing station; and Fig. 13 is a plan view showing probes in more detail.
Referring to the drawings, and initially to Fig. 1, there is illustrated a manufacturing process 1 for production of interface circuits. A typical such interface circuit is indicated by the numeral 60 in Figs. 13. As is clear from this diagram the circuit is simple and includes a number of female connector sockets 61, an edge connector 62 with a number of gold-plated contact fingers, and a relatively small number of passive components 63. Such circuits are simple in design, however, they play an extremely important part in the computer systems in which they are connected. For example, they may be used as network interface cards and accordingly if a fault arises the fault affects not only a single microcomputer but possibly a large number in a local area network. Some faults can be difficult to identify because of the physical size of the connectors - the plastics bulk of the sockets 61 covering a large part of the board area. £97082 / -5 Referring initially to Fig. 1 in combination with Figs. 2 to 8 inclusive, in step 2 of the process an operator chooses a nest associated with a particular interface board. There is a particular nest associated with each board and this is used for support of the board during screen printing. It has been found that by achieving a particularly high level of quality at the screen printing stage, many down-stream quality problems are avoided for this type of circuit. As shown in the drawings, there is a screen printing station 20 having a conveyor 21 which moves circuit boards 22 into position over a board support 23. The support 23 comprises a H-shaped base 25 which is universal as it is used for all types of interface circuit. A nest 26 is mounted on the base 25 at the start of a run for a particular type of interface circuit.
As shown most clearly in Fig. 6, the nest 26 comprises a top plate 27 having a number of vacuum holes 28 and a sensor aperture 29. An optical sensor 30 is mounted on a lower plate 32 at the edge of an aperture 31. Finally, the nest 26 comprises a pair of movable edge guides 33 which are movable from an inoperative position spaced-apart from the edge of the top plate 27 to an operative position closer to the top plate 27 and protruding above the level of its surface. The guides 33 are movable under pneumatic control.
As shown particularly in Figs. 6 to 8, in step 3 the board (with no components at this stage) 22 is conveyed longitudinally over the support 23 and once it is detected by the sensor 30, it is reversed in synchronisation with upward and inward movement of the edge guides 33. This movement occurs until the edges abut, at which position a vacuum system is activated and the board is secured in position ready for screen printing. As shown in Figs. 6 and 7, the screen printing head 24 then descends and prints the board.
It has been found that by use of a dedicated nest 26 having a flat surface adapted to the particular shape and configuration of the board, the use of the edge guides 33 and the vacuum holes 28, a particularly high positioning accuracy is achieved for screen printing.
This has been found to be particularly important at achieving good quality from an early stage in the process. 5970827 -6In step 4 there is component placement followed by machine inspection in step 5. In step 6 there is solder reflow at which the temperature is increased from room temperature to 190°C in 2.3 to 2.8 minutes. A particularly preferred peak reflow temperature is 180°C and the temperature gradient is preferably kept below 1.5°C/s In step 7, there is final assembly with combined automatic and manual assembly of the components, including the sockets 61.
Referring now in particular to Figs. 9 to 13 inclusive, testing of the assembled circuit board is now described. The testing is performed at an integrated test station 50. The station 50 has a base 51 supporting an edge guide 52 which is used for alignment of a circuit 60. Signal connectors 53 are provided for transmission of signals from a test controller, not shown. These connectors are connected to a socket on the board 60. The station 50 also comprises a test head 54 and a number of manual shorting probes 55.
In more detail, the test head 54 comprises a frame 58 supporting vertical columns 59 on which a carriage slides in the vertical direction carrying various test signal pins. These include lower test signal pins 65 embedded in the station base 51, and upper test signal pins 66 which are carried on the moving carriage. The pins 66 are connected by a wiring loom 67 to upper bridging signal pins 68, which are for connection with lower bridging signal pins 69.
Finally, as shown in Fig. 13, each manual sorting probe 55 comprises a blade 70 and various discrete passive components 71 connected to edge connector fingers 72.
In operation, the board 60 is placed in position as shown in Figs. 9 and 10. The head 54 is then operated to move the carriage downwardly as shown in Figs. 11 and 12 until the upper test signal pins 66 contact the upper surfaces of the edge connector 62 in step 8. This completes a testing circuit from the lower test signal pins 65, through the edge connector 62, and into the upper test signal pins 66. The signals are conveyed to the test controller via the wiring loom 67, the upper bridging signal pins 68, and then through the S87 082 7 -7lower bridging signal pins 69 in step 9 as the latter two have come into contact at the same time as the test signal pins 65 and 66 make contact with the edge connector 62. It has been found that this is a particularly simple and effective way of taking signals from a moving set of probes. It must be appreciated that over time with a large number of testing cycles in a high volume production environment, there may be physical wear of wiring cables extending from movable probes. The bridging pins solve this problem in a very simple and effective manner, resilience in the lower bridging pins 69 compensating for any wear which may arise over time. Thus, reliability and integrity of the testing station is considerably enhanced. This position of the various test pins allows continuity tests to be conducted by the test controller, full continuity from the edge connector to the socket pins being tested. It also allows testing of component placement to ensure presence and orientation of all passive components.
In addition, the invention allows comprehensive testing of continuity from the edge connectors through to the internal conductors of the sockets 61 by insertion of an associated shorting probe 55 in step 10 as illustrated in Fig. 11. Each probe is specific to a particular type of connector and includes the correct physical dimensions and electrical activity of the contacts via some passive components. When the probes have been inserted into the home positions as shown in Fig. 12, they contact the internal conductors and allow signals to be supplied from signal cabling 75. This allows further and more comprehensive continuity tests to be carried out from the edge connector 62 to the conductors within the sockets 61. They also allow short-circuit tests within the sockets 61.
While this may appear to be a very simple testing method, it is a very effective way of ensuring both mechanical and electrical integrity of the sockets and the board surface area which they occupy. Indeed, it has been found that this method allows faults to be detected which could not be detected using optical measurement systems.
Another aspect of the testing which is carried out at the station 50 is detection of mechanical layout of the board. Some edge probes of the station are spring biased so that $97082 7 -8they extend into apertures of the circuit board. They are also constructed so that if they do not extend into the aperture and are pressed downwardly by the board, there is shorting via a microswitch to a lower terminal which conducts an error signal to the controller. This allows mechanical testing of the board layout simultaneously with electrical testing.
The testing station 50 itself may be inspected itself in a very simple manner by inserting a conductive plate in the shape of the relevant board, the conductive plate having the same socket and connector arrangement. The test controller is programmed to insert a signal on some of the pins, a return signal being detected on all of the others. This allows immediate identification of faults such as a faulty spring on a test pin. For example, a faulty spring in an upper test probe can be difficult to identify visually because the pins are suspended down to the full extent even with a faulty spring. Such a fault is difficult to identify visually. Again, this is a very simple feature which allows fast diagnostic testing of the test station 50 itself.
It will be appreciated that the invention provides a manufacturing process which allows efficient production of interface circuits in which quality control is achieved by use of various simple steps which are easy to follow. Indeed, it is relatively easy to train new operators and to ensure that these steps are correctly followed.
The invention is not limited to the embodiments hereinbefore described, but may be varied in construction and detail.

Claims (5)

Claims
1. A method of manufacturing an interface circuit comprising the steps of:at a screen printing station, mounting a support nest associated with a printed circuit board on a universal base, the nest comprising: a plate with a substantially flat upper surface, and movable edge guides mounted for movement into a position alongside the upper surface to align a board for screen printing; conveying the board over the nest, detecting presence of the board, and conveying the board into contact with the edge guides; screen printing solder paste onto the board; placing components on the solder paste; curing the solder in a reflow oven to produce a soldered circuit; and testing the soldered circuit by placing it in a jig at an aligned position at which lower embedded test signal pins contact edge connector conductors and upper test signal pins descend to contact the conductors to complete a testing circuit, and a test controller directing short circuit, continuity, and component tests via said test signal pins.
2. A method as claimed in claim 1, wherein position of the board for screen printing is detected by a sensor mounted within the nest, and wherein the flat upper surface of the nest is on an upper wall, and the nest also comprises a spaced-apart lower wall to which the sensor is connected, and wherein the solder is cured with 5970827 -10a ramping temperature gradient of less than 1.5 °C per second, and wherein the shorting test is performed by insertion of a shorting probe into socket connectors on the board to complete a test circuit between the probe and the lower and upper test signal pins in contact with the edge connector, and wherein the shorting probe has passive circuit components connected to teeth for contact with conductors of the connector sockets.
3. A method as claimed in any preceding claim, wherein the test signals are transmitted to a test controller via mutually resilient bridging pins which move into contact with each other when the upper test signal pins are brought into contact with the edge connector, and wherein the bridging pins comprise movable bridging pins mounted on a carriage which also carries the upper test signal pins, and resilient pins which are mounted in a base of the testing station, and wherein the test station is diagnosed at regular intervals by insertion of a test board having a fully conductive surface and sockets in a similar arrangement to a circuit under test, transmitting a test signal to each test pin, and detecting a return signal at each of the other test pins.
4. A method substantially as hereinbefore described, with reference to and as illustrated in the accompanying drawings.
5. An interface circuit whenever produced by method as claimed in any preceding claim.
IE970827A 1997-11-25 1997-11-25 Manufacture of interface circuits IES970827A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
IE970827A IES970827A2 (en) 1997-11-25 1997-11-25 Manufacture of interface circuits
GB9725173A GB2331840A (en) 1997-11-25 1997-11-27 Manufacture of interface boards

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
IE970827A IES970827A2 (en) 1997-11-25 1997-11-25 Manufacture of interface circuits
GB9725173A GB2331840A (en) 1997-11-25 1997-11-27 Manufacture of interface boards

Publications (2)

Publication Number Publication Date
IES78835B2 IES78835B2 (en) 1998-02-25
IES970827A2 true IES970827A2 (en) 1998-02-25

Family

ID=26312677

Family Applications (1)

Application Number Title Priority Date Filing Date
IE970827A IES970827A2 (en) 1997-11-25 1997-11-25 Manufacture of interface circuits

Country Status (2)

Country Link
GB (1) GB2331840A (en)
IE (1) IES970827A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2347021B (en) * 1998-12-01 2003-07-09 Dovatron Res & Dev Ltd A circuit board manufacturing apparatus

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4667403A (en) * 1984-05-16 1987-05-26 Siemens Aktiengesellschaft Method for manufacturing electronic card modules
GB2284368B (en) * 1993-12-02 1996-01-03 Calmwaters Limited A circuit board production process

Also Published As

Publication number Publication date
IES78835B2 (en) 1998-02-25
GB2331840A (en) 1999-06-02
GB9725173D0 (en) 1998-01-28

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