IES922948A2 - A high-speed bidirectional parallel interface circuit - Google Patents

Abstract

A high-speed bidirectional parallel interface circuit (1) for interfacing a computer with an external device, the interface circuit (1) comprises a computer interface module (2) and an external device interface module (4). The circuit (1) is operable in an output mode for transferring data from the computer to the external device and an input mode for transferring data froa the external device to the computer. A first-in-first-out unidirectional main buffer (8) stores the data being transferred and the data is buffered through input and output buffers (9) and (10) between the main buffer (8) and the computer interface module (2) under the control of a control module (6). Input and output state machines (14) and (15) respectively under the control of the control module (6) control the transfer of the data through input and ^CT output latches (11) and (12) between the main buffer (8) and the external device module (4).

Description

The present invention relates to an independently operable high-speed bidirectional parallel interface circuit for interfacing a computer with an external device.

The term computer in this specification is intended to include any computer type device, for example, a personal computer, a mini computer, a mainframe computer and the like.

In general, where one wishes to interface an external device with a computer, it is normal to connect the external device, such as, for example, a printer or the like directly to the computer. Unfortunately, this tends to slow down the operation of the computer since the computer is unable to carry out other operations while data is being transferred from the computer to the printer, or other external device, or alternatively, while data is being transferred from the external device to the computer.

There is therefore a need for an interface circuit which overcomes these problems.

IE 922948 The present invention is directed towards providing such an interface circuit.

According to the invention there is provided a highspeed bidirectional parallel interface circuit for interfacing a computer with an external device, the interface circuit comprising a computer interface means for interfacing the interface circuit with a computer for transferring data between the computer and the interface circuit, an external device interface means for interfacing the interface circuit with an external device for transferring data between the external device and the interface circuit, main buffer means for storing data being transferred between the computer and the external device, an output state-machine for reading data from the main buffer means to the external device, an input statemachine for writing data to the main buffer means from the external device, the input and output statemachines being coupled to each other so that only one of said state-machines is enabled at any one time and a disabled state-machine is only enabled on the other of said state-machines completing a data transfer cycle, and control means for controlling the statemachines, the control means being responsive to signals from the computer and the external device.

IE 922948 In one embodiment of the invention, the main buffer means comprises a first-in-first-out buffer. Advantageously, each state-machine is operable in eight states sequentially. Preferably, intermediate latch means are provided between the main buffer means and the external device interface means for latching data being transferred between the main buffer means and the external device interface means.

The invention will be more clearly understood from the 10 following description of a preferred embodiment thereof given by way of example only, with reference to the accompanying drawings, in which: Fig. 1 is a block representation of a high-speed bidirectional parallel interface circuit according to the invention, Fig. 2 is a block representation of portion of the interface circuit of Fig. 1 indicating the direction of flow of data through the interface circuit, Fig. 3 illustrates the operational sequence of an input state-machine of the interface circuit of Fig. 1, and IE 922948 Fig. 4 illustrates an operational sequence of an output state-machine of the interface circuit of Fig. 1.

Referring to the drawings there is illustrated in 5 block representation a circuit of a high-speed bidirectional parallel interface circuit according to the invention indicated generally by the reference numeral 1. In this embodiment of the invention the interface circuit 1 is suitable for interfacing a computer (not shown) with an external device (also not shown), such as, for example, a printer or the like for transferring data from the computer to the printer and vice versa. The interface circuit 1 is operable in two modes, namely, an output mode and an input mode. In the output mode, data and signals are transferred from the computer to the external device. In the input mode, data and signals are transferred from the external device to the computer. The interface circuit comprises a computer interface means, in this case, a computer interface module 2 illustrated in block representation in Fig. 1. The computer interface 2 is suitable for connecting to the I/O expansion bus of a computer and, in particular, a personal computer, and accepts data from the computer for transfer to the external device (not shown) as well as address and control signals when the interface IE 922948 circuit 1 is in the output mode. Data, address and control signals from the interface circuit 2 are transferred to the computer through the computer interface module 2 when the interface circuit 1 is in the input mode. In this embodiment of the invention the computer interface module 2 comprises a bidirectional buffer (not shown) for interfacing the computer I/O data bus with the interface circuit. Two unidirectional buffers (not shown), one for each direction of data transfer, deal with address and control signals. The construction and arrangement of such computer interface modules will be known to those skilled in the art.

An external device interface means, comprising an external device interface module 4 interfaces the interface circuit 1 with the external device and is suitable for connecting into the parallel port of the external device. The external device interface module 4 comprises a bidirectional buffer (not shown) for interfacing the data bus of the external device with the interface circuit. A pair of unidirectional buffers one for each direction of data transfer (also not shown) deal with control signals. This construction of external device interface module will be well known to those skilled in the art.

IE 922948 Control means for controlling the operation of the interface circuit 1 comprises a control module 6 which generates appropriate read and write and other signals for controlling the operation of the interface circuit in response to control and address signals received from the computer and the external device. PAL devices (not shown) in the control module 6 provide the appropriate read and write and control signals depending on the status signals received from the external device through the interface module 4, and depending on the address and control signals received through the interface module 2 from the computer. Control and status registers (not shown) in the control module 6 permit the computer to monitor the status of the interface circuit. A clock signal generator is provided in the control module 6 for generating clock signals.

Main buffer means for storing data to be transferred between the computer and the external device comprises a first-in-first-out unidirectional main buffer 8.

Data being transferred from the computer to the external device is transferred into the main buffer 8 through an intermediate input buffer 9 under the control of the control module 6. Data being transferred from the external device to the computer is transferred from the main buffer 8 to the computer fe922948 interface module 2 through an intermediate output buffer 10 under the control of the control circuit 6. Data being transferred between the computer and external device is transferred to and from the main buffer 8 through intermediate latch means, namely, an intermediate input latch 11 and an intermediate output latch 12, respectively. Arrows A and B in Fig. 2 indicate the direction of the flow of data through the interface circuit 1 when the circuit is in the output mode and the input mode, respectively.

A pair of state-machines, namely, an input statemachine 14 and an output state-machine 15 under the control of the control module 6 control the transfer of data and the direction of transfer between the main 15 buffer 8 and the external device. The input and output state-machines 14 and 15, respectively, are coupled together so that only one of the statemachines 14 and 15 is enabled at any one time, and a disabled state-machine 14 or 15 is only enabled by the other of the state-machines 14 and 15 having completed a data transfer cycle. The input state-machine 14 writes data from the external device into the main buffer 8 through the intermediate input latch 11 when the interface circuit 1 is in the input mode. The output state-machine 15 reads data from the main buffer 8 through the intermediate latch 12 when the IE 922948 interface circuit 1 is in the output mode. The input and output state-machines 14 and 15, respectively, are operable in eight states sequentially during a data transfer cycle. The states are indicated by the circles SO to S7 in Figs. 3 and 4.

Referring in particular to Fig. 4 the eight states SO to S7 in which the output state-machine 15 is operable will now be described. In the state SO the output state-machine 15 is in a reset state. The output state-machine 15 remains in the reset state as long as: 1. a reset signal is asserted from the control module 6, or 2. the input state-machine 14 has not yet finished its data transfer cycle, or 3. the interface circuit 1 is in input mode as controlled by the control module 6.

It is possible for the input state-machine 14 to have finished its data transfer cycle and the interface circuit may still be in input mode, in which case the output state-machine 15 remains in the reset state SO. In state SI the controller examines the main buffer 8 to determine if data is stored in the main buffer 8 and remains in a loop in state SI until data is stored in the main buffer 8. On the output state-machine 15 IE 922948 determining that there is data in the main buffer 8 the output state-machine 15 moves to state S2. In state S2 the output state-machine 15 examines the external device to determine if the external device is busy and remains in a loop in state S2 until the external device is no longer busy. On the external device being no longer busy the output state-machine 15 moves to state S3 and examines the external device to ascertain if the external device is finished its 10 current operation, and remains in a loop in state S3 until it is detennined that the external device is finished its current operation. On the output statemachine 15 having determined that the external device has finished its current operation the output state15 machine 15 moves to state S4. State S4 is used to guarantee a sufficient access time to the buffer 8 such that valid data is available to be read from the main buffer 8 and written to the intermediate output latch 12, at which stage the output state-machine 15 moves to state S5. In state S5 data is read from the main buffer 8 and written to the intermediate output latch 12 for transfer to the external device. State S6 is used to guarantee that the data remains valid at the input of the intermediate output latch 12 to satisfy data hold requirements of the latch 12. In state S7 which is a strobe state, data from the output latch 12 is strobed through the external device IE 922948 interface module 4 to the external device. The output state-machine 15 is then returned to state SO.

Referring now to Fig. 3, the eight states SO to S7 in which the input state-machine 14 is operational will now be described. In state SO the input state-machine 14 is in a reset state. The input state-machine 14 remains in the reset state SO as long as: 1. a reset signal is asserted from the module 6, or 2. the output state-machine 15 has not yet finished its data transfer cycle, or 3. the interface circuit 1 is in output mode as determined by the control module 6.

It is possible for the output state-machine 15 to have finished its data transfer cycle and the interface circuit 1 still to be in output mode whereupon the input state-machine 14 remains in the reset state SO. In state SI the input state-machine 14 outputs a clear busy signal to prime an external strobe input latch (not shown) in the external device interface module 4, and moves to state S2. In state S2 the controller of the input state-machine 14 waits for the capture of an incoming strobe signal from the external device by the external strobe input latch (not shown) and the presence of valid data in the intermediate input latch 11. On the capture of an incoming strobe signal and IE 922948 valid data being present in the intermediate input latch 11 the input state-machine 14 moves to state S3, and commences to write data into the main buffer 8 from the intermediate input latch 11 in a first-in5 first-out cycle. In state S4 the input state-machine 14 continues to write data into the main buffer 8 in a first-in-first-out cycle from the intermediate input latch 11, and moves to state S5. In state S5 the input state-machine 14 examines the state of the main buffer 8 to determine if there is room for further data and remains in a loop in state S5 until there is room for further data to be written into the main buffer 8, at which stage the input state-machine 14 moves to state S6. On entering state S6, the input state-machine 14 outputs a clear busy signal to prime the external strobe input latch (not shown) and ultimately removes the busy signal to the external device. While the clear busy signal is active, the busy signal to the external device is also active.

Should the control module 6 assert a hold busy signal, the input state-machine 14 remains in state S6 which causes the clear busy signal to be asserted continuously thereby extending the length of time for which the busy signal to the external device is asserted. This prevents the external device from sending any more data, and may be necessary in some cases to allow the computer time to interface to the ® «2948 interface circuit 1. Once the input state-machine 14 leaves state S6 either in normal operation or once the hold busy signal has been deasserted it moves to state S7 where it outputs the acknowledge signal to the external device to indicate completion of the current transfer. The input state-machine 14 then returns to the reset state SO.

In use, where data is to be downloaded from the computer to the external device, the interface circuit 1 is put into the output mode under the control of the control module 6. Data is downloaded from the computer through the computer interface module 2 and in turn through the intermediate input buffer 9 to the main buffer 8 under the control of the control module 6. The data is then transferred from the main buffer to the external device under the control of the output state-machine 15 as already described. Where data is to be transferred from the external device to the computer, the data is transferred from the external device into the main buffer 8 under the control of the input state-machine 14 as already described. The data is subsequently transferred from the main buffer 8 through the intermediate output buffer 10 under the control of the control module 6 to the computer through the computer interface module 2.

IE 922948 Accordingly, data can be down-loaded rapidly from the computer into the main buffer 8 for subsequent transfer to the external device, thereby minimizing the time required for the computer to transfer the data. The data can then be transferred to the external device at the appropriate rate when the external device is ready to receive the data.

Similarly the data from the external device may be retained in the main buffer 8 of the interface circuit until the computer is ready to receive the data thereby permitting the computer and the external device to operate independently of each other.

While the interface circuit has been described as being connected directly to a computer, the interface circuit may be connected indirectly to the computer.

It will also be appreciated that in all cases data may not be transferred from the external device to the computer, however, other signals may be transferred.

The invention is not limited to the embodiment hereinbefore described which may be varied in construction and detail.

Claims (5)

1. A high-speed bidirectional parallel interface circuit for interfacing a computer with an external device, the interface circuit comprising a computer 5 interface means for interfacing the interface circuit with a computer for transferring data between the computer and the interface circuit, an external device interface means for interfacing the interface circuit with an external device for transferring data between 10 the external device and the interface circuit, main buffer means for storing data being transferred between the computer and the external device, an output state-machine for reading data from the main buffer means to the external device, an input state15 machine for writing data to the main buffer means from the external device, the input and output statemachines being coupled to each other so that only one of said state-machines is enabled at any one time and a disabled state-machine is only enabled on the other 20 of said state-machines completing a data transfer cycle, and control means for controlling the statemachines , the control means being responsive to signals from the computer and the external device.

2. An interface circuit as claimed in Claim 1 in 25 which the main buffer means comprises a first-infirst-out buffer. ,E 922948

3. An interface circuit as claimed in Claim 1 or 2 in which each state-machine is operable in eight states sequentially.

4. An interface circuit as claimed in any preceding 5 claim in which intermediate latch means are provided between the main buffer means and the external device interface means for latching data being transferred between the main buffer means and the external device interface means. 10

5. An interface circuit substantially as described herein with reference to and as illustrated in the accompanying drawings.