IES81036B2 - A data acquisition circuit - Google Patents

Description

“A Data Acquisition Circuit” The invention relates to a data acquisition circuit for use in data acquisition systems suitable for harsh environments such as in the aerospace industry.

Typically, such circuits are used for processing analog signals from sensors such as accelerometers or strain gauges. The signals are converted to digital format and are sampled to deliver a digital data signal representative of the parameter being monitored. The application may involve real-time data acquisition or stand-alone data logging.

While technologies for such processing exist at present, major problems arise in harsh environments such as in the aerospace, automotive, and energy industries. The circuits must be mounted in very rugged housings. The material may, for example, be CNC milled aluminium plate. It is often a requirement that the housing also be quite compact because the space is restricted. Also, the circuits must withstand mechanical shock and vibration.

In such an environment it is typically the case that reliability is not what it should be because of heat dissipation by processors providing functions such as digital filtering.

Also, the circuits are often intolerant of power supply fluctuations, which can cause data corruption and difficulties in re-booting. A still further problem which arises is circuit damage arising from mechanical shock and vibration.

It is therefore an object of the invention to provide a data acquisition circuit which is tolerant of a harsh environment.

Another object is to provide such a circuit which is more compact than heretofore.

According to the invention, there is provided a data acquisition circuit comprising: -2a plurality of input analog channels, each comprising a signal conditioner and each having an independent sample rate and filter cut-off point, a digital filter comprising a state machine controlled by a counter for multiplexing the channels, performing digital filtering in cascaded stages at sampling rates which are successive binary sub-divisions of the preceding stage beginning with a primary sampling rate, and for selecting an output from one of the stages.

In one embodiment, the digital filter comprises an FPGA.

Preferably, there is a set of fixed multiplier coefficients for the digital filter multipliers.

In one embodiment, the coefficients are stored in a separate read only memory.

In another embodiment, the read only memory stores a look-up table of all possible multiplication results, the table being addressable with an input register value.

In a further embodiment, the counter comprises means for selecting which cascading filter stage provides the output for each channel. Preferably, the output is written to a register in the digital filter.

In another embodiment, the read only memory stores values for linearisation of the analog to digital converters and channel gain settings.

In a further embodiment, the counter controls the state machine via decoders.

In another embodiment, the decoders include a cascading stage decoder, a read pointer decoder, and a write pointer decoder.

Preferably, all logic blocks of the digital filter are in hardware. -3 The invention will be more clearly understood from the following description of some embodiments thereof, given by way of example only with reference to the accompanying drawings in which:5 Fig. 1 is a perspective view from above of a housing of a data acquisition system; Fig. 2 is a block diagram of a data acquisition circuit; Fig. 3 is a logical representation of a digital filter of the circuit; Fig. 4 is a logical representation of cascaded filtering by the circuit; Fig. 5 is a block diagram showing the major signal transfers of the circuit; and Fig. 6 is a block diagram showing signal transfers in more detail.

Referring to Fig. 1, there is shown a housing 1 for a data acquisition system of the invention. The housing is of AlMg material surface finished with electroless nickel plating. The plates are 4.0 mm thick. A top plate 2 comprises slots 3 for receiving connectors of circuits plugged into the housing 1 in a modular manner. These circuits include three data acquisition circuits in the three longer slots 3, a main control circuit in the next slot, and a power supply module in the last slot 3.

The circuits are connected in a modular manner to a general bus for control logic and data transfer. Apertures 4 in the top plate 2 are provided for fasteners which support the circuits. This arrangement provides mechanical support to minimise the effects of mechanical vibration and shock. Also, the housing provides protection from the environment generally, such as that around an aeroplane during testing. Sensors are connected directly to the circuit connectors in the slots 3. The sensors may be RTDs, strain gauges, or accelerometers, for example, or any combination. -4Referring now to Fig. 2 a data acquisition circuit 10 is illusted. There are eight analog input channels CHI, CH2, CH3, CH4, CH5, CH6, CH7, and CH8. Each channel relates to a separate sensed parameter. For example one may be an accelerometre and another a strain gauge. There is a signal conditioning circuit SC for each channel. These perform anit-aliasing functions by eliminating analog frequencies above certain levels such as 5 kHz for compliance with the Nyquist criterion that the digital sampling rate be at least double the incoming analog frequency. Each SC also amplifies or attenuates according to the amplitude of the incoming analog signal. For example, a strain gauge output may have a span of approximately lOmV. The SCs provide an output in the range - 10V to +10V, this signal being fed to the input of an analog to digital converter ADC. Each channel has an independent sample rate and filter cut-off point.

The ADCs are controlled by an FPGA digital filter 15, and it is only upon receipt of a clock signal from the filter 15 that output digital sample is delivered to the filter. The digital filter 15 is connected to an SRAM 16 and an EEPROM 17. An i/o buffer 18 is connected to the filter 15.

Fig. 3 is a logical representation of the structure of the digital filter. In this embodiment, a sample is delivered at the first input register 20 and is successively shifted across all thirty one registers 20. Thus, at any one time there are thirty-one samples in the registers. The value in each register is multiplied by a coefficient multiplier 25. The coefficients are identified by K0 to K.15. Each register 20 is 16-bits wide and so the register value can be at any binary value between 0 and 65,535. It is this value which is multiplied by the coefficient. The multiplier outputs are then added by an adder 30 to provide the output. Thus, the filter is a 31-tap, Finite Impulse Response (FIR), half-band digital filter. -5The logical structure of the digital filter is represented in Fig. 4, which in this embodiment illustrates sixteen cascade stages 0 to 15. Each stage generates an output which may be provided as the circuit output if so set.

Heretofore, such extensive digital filtering has required very extensive processing circuitry such as general purpose microprocessors or digital signal processors (DSPs). These have quite high power consumption and are quite intolerant of harsh electrical and mechanical environments. For example, a DSP typically has a power consumption of approximately 5W, and so a bank of five DSPs in a full system would generate considerable heat in the confined housing space.

As indicated generally in Fig. 2, this problem is addressed in the present invention by use of a field programmable gate array FPGA (alternatively called a PLD) device. Such a filter has a very low gate count and in this embodiment it is approximately 8,000 gates.

This has a much lower power consumption of approximately 0.25 W, and is also much smaller physically. Another advantage is that it can be made tolerant of power fluctuations or other conditions which cause power interruption. The design features of the digital filter which achieve these advantages are described in more detail below.

Referring to Figs. 5 and 6, the digital filter comprises an FPGA which comprises fixed decode and control logic 40, a counter 41, and an accumulator 42. As shown particularly in Fig. 6, the counter 41 drives a core state machine 46 via stage, read pointer, and write pointer decoders 47, 48, and 49 respectively. The core state machine 46 comprises logic gates for only one digital filter stage, and the counter 41 multiplexes on a time division basis to achieve a logical cascading operation of sixteen stages. This minimises the number of physical registers needed thus allowing use of an FPGA, which would otherwise not be possible. The counter 41 operates on a fast clock cycle and governs operation of the core state machine on a last state-input next state basis so that it is not permanently affected by power surges or outages of short duration. -6Another important aspect of the architecture in that the clock signals of the counter, as shown in Fig. 4 cause each cascading stage to sample at a binary division of the preceding stage. Thus, stage 0 has a sampling rate of a primary sampling frequency Fp. This is a multiple of that required at the output. Thus, the sampling frequency ranges from Fp for Stage 0 to Fp/32,768 for Stage 15. The output of each stage is available, but only one is set by the counter 41 for any particular setup. The chosen output is written to a dedicated register in the FPGA. It is because the channel sample rates are binary divisions that the state machine may be controlled by a single binary counter. If the output rate chosen is also Fp then for every sample of the ADC a new output is calculated. If the output rate chosen is half the primary sampling rate (Fp/2) then for every second sample of the ADC a new output is calculated and passed into the second stage FIFO. Every time a new sample enters the second stage FIFO a new output is generated. If the output rate is quarter the primary sampling rate (Fp/4) then for every' second sample of the ADC a new output is calculated and passed into the second stage FIFO. For every second sample entering the second stage FIFO a new output is generated and fed into the third. The number of calculations required is independent of the number of stages of filtering.

A further important aspect is that there is no need to perform multiplication at the multipliers. This is because a fixed frequency profile or filter characteristic is chosen for the particular output sampling rate. Thus, the coefficient values are fixed. There are therefore only 4096 possible multiplication results for each multiplier because there are only 4096 possible values in the input register. All of these values are stored in the EEPROM and are simply retrieved using the register value as an address. This dramatically reduces processing time and gate capacity required. Also, very importantly, the precision can be set to a very high level and is in this case 32 bit. The storage required provides little overhead because of the extent of space available in the EEPROM. -Ί The EEPROM is also used for linearisation of the ADC values and for storing filter coefficients and gain settings for each channel. The SRAM enables storage of many intermediate sample values used in calculation. This is very important because of the limited FPGA space.

In more detail, the state machine controls the ADCs, updates the values sent to the i/o, and reads the EEPROM to set the SC gains and other parameters. It also reads ADC parameter values from the EEPROM. The register banks shown in Fig. 3 are implemented using multiple FIFOs in the SRAM. Each cascaded filter stage requires its own FIFO, and each FIFO needs its own read and write pointer (typically a counter). The 128 read pointer and 128 write pointers are derived from a single counter, as in the channel and stage which is to be implemented next.

For the state machine to run, it needs to know:Ch[2:0] The channel being filtered.

Stage[3:0] The stage being filtered.

Rd_Pt[5:0] The read pointer pointing at last output from previous stage. Wr_Pt[5:0] The pointer pointing to where to write the output of this stage.

These values are derived from the counter 41.

The state machine also requires a value N inversely proportional to the primary sampling rate, which is read from EEPROM. The sequence of the state machine is as follows: State Do If stage = 0000 linearise ADC value using EEPROM look-up EEPROM address = CH[2:0] ADC[11:0] else read setup values from EEPROM such as gain etc. -82 If stage = 0000 write value from EEPROM look-up to SRAM address = CH[2:0] 0000 Rd_pt[5:0] Read SO (newest value) SRAM address = CH[2:0] {Stage[3:0]} {Rd_pt[5:0] - 0) Read S30 (oldest value) SRAM address = CH[2:0] {Stage[3:0]} {Rd_pt[5:0] - 31) Multiply the sum using EEPROM look-up EEPROM address = 0000 SUM(16:0] x Read Sy SRAM address = CH[2:0] {Stage[3:0]} {Rd_pt[5:0] + y) x+1 Read S30-y SRAM address = CH[2:0] {Stage[3:0]} {Rd_pt[5;0] - 31 + y) x+2 Multiply the sum using EEPROM look-up EEPROM address = y SUM[16:0] y Write result to SRAM SRAM address = CH[2:0] {Stage[3:0] + 1} {Wr_pt[5:0]) : Do nothing N N determines the primary sampling rate and is programmable At N increment main counter and reset the state machine to 1 The main counter is incremented every time a new output is generated from any stage of any channel. It is used to generate Ch[2:0], Stage[3:0], Rd_Pt[5:0] and Wr_Pt[5:0]. To generate these values the number of stages, Max[3:0], for each channel (i.e. the amount of decimation) must be read for each channel. These are the three least significant bits of the counter C[2:0]. If, for a given channel, the output is at one eighth the primary sample rate then the output to each stage is calculated as follows:C[6:3] Calculate the output of stage Note For Ο C3 = Ο For 1 C4 = Ο For 2 C5 = Ο -90000 ο 0001 1 0010 ο 0011 2 0100 ο 0101 1 0110 ο 0111 3 1000 ο 1001 1 1010 ο 1011 2 1100 ο 1101 1 1110 ο 1111 3 For 3 C6 = Ο For3C7 = 0, ΜΑΧ[3:0] = 0011 In general the stage number is derived using If C(3) = 0 then stage = 0000 elsif C(4) = 0 then stage = 0001 elsif C(3+n) = 0 then stage = n elsif end if. C(18) = 0 then stage = 15 Finally to ensure that the last stage is repeated the following check is used:If stage >=MAX[3:0] =0000 else stage = stage then stage = MAX[3:0] -10end if This requires a small combinatorial circuit.

The read pointer Rd_Pt[5:0] provides the offset value for reading the previous values.

The following code is used to generate the read pointer:- If stage = 0000 then Rd_Pt[5:0] = C[8:3] elsif stage = 0001 then Rd_Pt[5:0] = C[9:4] elsif stage = n then Rd_Pt[5:0] = C[8+n:3+n] elsif end if. stage = 15 then Rd_Pt[5:0] = C[23:18] This requires 5 x 16 to 1 multiplexers which can be implemented very efficiently in the FPGA.

The write pointer Rd_Pt[5:0] provides the location to which to write the output value from the filter. For the last stage this can be the same as the read pointer (Rd_Pt[5:0]) otherwise it will increment at half the rate.

The following code is used to generate the read pointer:If stage = 0000 then x = C9 elsif stage = 0001 then x = C10 elsif stage = n then x = C(9+n) - 11 elsif stage = 15 then x = C(2) end if.

This requires a 16 to 1 multiplexer which can be implemented very efficiently in the FPGA.

Then check if this is the last stage:If stage = max then Wr_Pt[5:0] = Rd_Pt[5:0] else Wr_Pt[5:0] = X Rd_Pt[5:1 ] end if It will be appreciated that the invention achieves a data acquisition circuit and system incorporating such a circuit which has the major advantages of:a very small size, low power consumption because for a given performance clock frequency and supply current are significantly lower than heretofore, low device count, leading to low cost, excellent reliability because of the absence of software, and because the architecture is immune to power-on-reset problems, short testing time because of absence of software and the state machine “works-once-work-always” characteristics, and scalability by potential use of higher density FPGA components.

These advantages are very important for harsh data acquisition environments. - 12 The invention is not limited io the embodiments described but may be varied in construction and detail within the scope of the claims.

Claims (4)

Claims

1. A data acquisition circuit comprising: a plurality of input analog channels, each comprising a signal conditioner and each having an independent sample rate and filter cut-off point, a digital filter comprising a state machine controlled by a counter for multiplexing the channels, performing digital filtering in cascaded stages at sampling rates which are successive binary sub-divisions of the preceding stage beginning with a primary sampling rate, and for selecting an output from one of the stages.

2. A circuit as claimed in claim 1, wherein the digital filter comprises an FPGA, and wherein there is a set of fixed multiplier coefficients for the digital filter multipliers, and wherein the coefficients are stored in a separate read only memory, and wherein the read only memory stores a look up table of all possible multiplication results, the table being addressable with an input register value.

3. A circuit as claimed in any preceding claim, wherein the counter comprises means for selecting which cascading filter stage provides the output for each channel, and wherein the output is written to a register in the digital filter, and wherein the read only memory stores values for linearisation of the analog to digital converters and channel gain settings, and wherein the counter controls the state machine via decoders, and wherein the decoders include a cascading stage decoder, a read pointer decoder, and a write pointer decoder, and wherein all logic blocks of the digital filter are in hardware.

4. A data acquisition circuit substantially as described with reference to the drawings. - 14A data acquisition system comprising a circuit as claimed in any preceding claim mounted in a rugged housing.