IES80899B2 - A control system for communicating a master with a plurality of slaves over a bus in a digital communications system - Google Patents

Abstract

A control system (1) controls communication between a host bus (3) and eight daughter cards (4) through a communications bus (5) under the control of a master (6) which is located in a host computer. The communications bus (5) is located on a mother board and the eight daughter cards (4) are connected in pairs to the mother board. Communication between the respective daughter cards (4) and the communications bus (5) is through corresponding slaves (8). The master (6) communicates independently with at least two slaves (8) simultaneously, the data being communicated in words each having a pre-determined number of bits, in this case 32 bits, and each word is separated into two sub-groups, each of 16 bits for reception by the respective slaves (8) with which the master (6) is simultaneously communicating so that each slave (8) receives a different sub-group. .

Description

A control system for communicating a master with a plurality of slaves over a bus in a digital communications system The present invention relates to a control system for communicating a master with a plurality of slaves over a bus in a digital communications system, and in particular, though not limited to a system for communicating a plurality of daughter cards through corresponding slaves with a master, such as a microprocessor of a host computer, or the like.

According to the invention there is provided a control system for communicating a master with a plurality of slaves over a bus in a digital communications system, wherein the master can communicate independently with at least two slaves simultaneously, the data being communicated in words, each having a predetermined number of bits, and a means is provided for separating each word into subgroups of bits for reception by the respective slaves with which the master is simultaneously communicating so that each slave receives a different sub-group.

In one embodiment of the invention each word is divided into N sub-groups where N is the number of slaves to be independently communicated with simultaneously, and N is an integer equal to or greater than 2. Preferably, the sub-groups of bits are of equal length.

Advantageously, the integer by which each word is to be divided is equal to 2n where n is an integer equal to or greater than 1.

In one embodiment of the invention each word contains at least 32 bits, and the integer by which the word is to be divided is equal to 2, thereby providing sub-groups of 15 bit length.

In another embodiment of the invention the means for separating each word into the respective sub-groups comprises a plurality of first temporary storing means for storing the respective subgroups of bits, the capacity of each first temporary storing means corresponding to the number of bits of the sub-group of bits which are to be stored in that first temporary storing means, the respective first temporary storing means being arranged so that each word is stored in the respective sub-groups in the respective first temporary storing means, and a means is provided for enabling each first temporary storing means and the slaves to be communicated with, so that each slave to be communicated with receives the sub-group of bits to be transmitted to it from the corresponding first temporary storing means. Preferably, N first temporary storing means are provided.

Preferably, the first temporary storing means are of similar capacity.

In one embodiment of the invention each first temporary storing means comprises a first register.

In one embodiment of the invention two first registers are provided for facilitating independent simultaneous communication between the master and two slaves.

In another embodiment of the invention the means for separating the bits into the sub-groups is responsive to an address issued by the master, and preferably, the address comprises an identification of the slave to which one of the sub-group of bits is to be transmitted, and preferably, the address comprises an address of an item on a device communicating with the slave, and preferably, the address is of a register on a daughter card associated with the slave.

In one embodiment of the invention the master identifies the slaves with which it wishes to simultaneously communicate in an address which is one word long. Preferably, the word is divided into a plurality of sub-groups of bits, the respective sub-groups comprising the identifications of the corresponding slaves. Preferably, the address issued by the master is divided into N sub-groups, where N is the number of slaves with which the master wishes to communicate, and preferably, the sub-groups are of equal length. Preferably, the respective sub-groups of bits in the address issued by the master identify the corresponding slaves by a number, and preferably, a predetermined number of bits are assigned for identifying the slaves. Advantageously, each subgroup of bits comprises an address of a device associated with the corresponding slave, and in one embodiment of the invention the address of the device identifies a register in a daughter card associated with the slave.

Preferably, a means for separating the sub-groups of bits of each address issued by the master is provided, and ideally, the means for separating the sub-groups comprises a plurality of the second temporary storing means. Ideally, N second temporary storing means are provided, one for each sub-group of bits of each address.

Ideally, the capacity of each second temporary storing means corresponds to the number of bits in the sub-group of bits which it is to store, and preferably, the capacity of the respective second temporary storing means is similar. Ideally, each second temporary storing means is provided by a second temporary register.

In one embodiment of the invention the control system is provided for communicating a host bus with a plurality of slaves, the master communicating with the host bus, and preferably, the slaves communicate with daughter cards. Ideally, the control means is provided on a mother board and ideally, the daughter cards are connected to the mother board, preferably, the daughter cards are connected to the mother board in pairs and preferably, in parallel pairs, ideally, an indicating means is provided for identifying the respective boards of each pair of parallel connected boards.

In one embodiment of the invention the control system is for communicating a VXIbus with a plurality of devices communicating with the slaves, in another embodiment of the invention the communicating system is for communicating a VMEbus with a plurality of devices communicating with the slaves, in another alternative embodiment of the invention the communicating system is for communicating a multibus with a plurality of devices communicating with the slaves, while in a still further embodiment of the invention the control system is for communicating a compact PCI bus with a plurality of devices communicating with the slaves.

The invention will be more clearly understood from the following description of an embodiment thereof which is given by way of example only with reference to the accompanying drawings, in which: Fig. 1 is a block representation of a control system according to the invention for communicating a plurality of daughter cards with a host bus over a bus in a digital communications system, Fig. 2 is a block representation of a controller for controlling the communications system, Fig. 3 is a graphical illustration of the transfer of a word between the host bus and the daughter cards, Fig. 4 is a graphical representation of the transfer of a block of data words from the host bus to the daughter cards, Fig. 5 is a graphical representation of the transfer of data words from the daughter cards to the host bus, Fig. 6 is a graphical representation of a simultaneous transfer of data words from two daughter cards to two other daughter cards, Fig. 7 is a functional block diagram of a master controller of the control system of Fig. 1, Fig. 8 is a functional block diagram of a slave of a daughter card of the system of Fig. 1, Fig. 9 is a diagrammatic representation of connections of daughter cards to a mother board, Fig. 10 is a circuit of a detail of the connection of the daughter cards to the mother board which is illustrated in Fig. 9, and Fig. 11 is a representation of an address word issued by the master of the control system of Fig. 1.

Referring to the drawings there is illustrated a control system according to the invention which is indicated generally by the reference numeral 1 for controlling communication between a host bus 3, for example, a VMEbus of a host computer (not shown) with a plurality of daughter cards 4. The control system 1 controls communication between the host bus 3 and the daughter cards 4 through a communications bus 5 under the control of a master 6 which is located in the host computer. The communications bus 5 is located on a mother board 7, see Fig. 9 and in this embodiment of the invention eight daughter cards 4 are provided, and they are connected in pairs to the mother board 7. The daughter cards of each pair are connected in parallel as will be described below with reference to Figs. 9 and 10. Each daughter card 4 communicates with the communications bus 5 through a corresponding slave 8, the eight slaves 8 being mounted on the mother board 7.

In this embodiment of the invention the master β comprises a 32 bit address and data bus for communicating with the conraunication bus 5, and each slave 8 comprises a 15 bit address and data bus for communicating with the communications bus 5.

The control system 1 is arranged so that the master 6 can simultaneously communicate with two daughter cards 4 independently of each other. This is achieved as follows. The data is transmitted by the master 6 in one or more 32 bit words. Each 32 bit word is divided into two sub-groups each of 15 bits. The respective 15 bit sub-groups are transmitted simultaneously to the two respective slaves 8 of the corresponding daughter cards 4 being addressed by the master 5. Data can also be read independently from two daughter cards 4 through their corresponding slaves 8 simultaneously by the master 5 in a similar fashion. Additionally, data can be read independently from two daughter cards 4 through their corresponding slaves 8 and simultaneously written to another two daughter cards 4 through their corresponding slaves 8. The master 5 can also address some or all of the daughter cards 4 simultaneously with the same data.

Addressing of the daughter cards 4 by the master 5 is substantially similar to data transfer in that each address which is generated by the master 5 is in the form of a 32 bit word which is divided into two sub-groups each of 16 bits, and the 16 bits sub-groups identify the respective daughter card 4 which are to be addressed, and a device on the daughter card 4 typically a register which is to be addressed. This will be described in detail below.

A control means for controlling communication in the communications bus 5 comprises a controller 10, see Fig 2, which operates under the control of the master 5 as will be described below. A first separating means for separating each 32 bit data word outputted from the master 5 for writing to two of the daughter cards 4 comprises two first temporary storing means, namely, a first upper register 11 and a first lower register 12.

In this embodiment of the invention the eight daughter cards 8 are arranged in two sets of four daughter cards each, and accordingly two identical first upper registers 11 and two identical first lower registers 12 are provided, a first upper and lower register 11 and 12 for each set of daughter cards 8. Each first upper register 11 receives the upper 16 bits of each 32 bit data word, while each first lower register 12 receives the lower bits of each 32 bit data word. Each 32 bit data word transmitted by the master card 6 is written into the respective pairs of registers 11 and 12, the upper 16 bits being read into the first upper registers 11, while the lower 16 bits are read into the first lower registers 12.

The two daughter cards 4 to which the data word or words are to be 10 sent are identified in an address from the master 6 which will be described below, and the controller 10 outputs trigger signals to the corresponding slaves 8 of the daughter cards 4 to which the data is to be written. The controller 10 also outputs an enable signal to the relevant first register 11 or 12 for enabling the sub-group of bits of the data word in the relevant first register 11 or 12 to be written to the daughter cards 4 to which the subgroups of bits of the data word are to be written.

The address issued by the master 6 for addressing the slaves 8 of the two daughter cards 4 is a 32 bit word, and is sub-divided into two 16 bit sub-groups. Each 16 bit sub-group identifies the slave 8 of one of the daughter cards 4 to which one of the sub-groups of 16 bits of data of the following data word or words are to be sent. A second separating means for separating each 32 bit address word comprises two second temporary storing means, namely, a second upper register 16 and a second lower register 17. The second upper register 16 receives the upper 16 bits of the one word address, and the second lower register 17 receives the lower 16 bits of the one word address.

As mentioned above, data can be read simultaneously by the master 6 from two daughter cards 4. The data to be read from the two daughter cards is transmitted in 16 bit words from the slaves 4 of the two daughter cards 8, and stored in the corresponding first upper and lower registers 11 and 12. The data is then read simultaneously from the two relevant first upper and lower registers 11 and 12 as a 32 bit word, and as will be understood, this is substantially the reverse of a data write procedure from the master to two slaves. Additionally, data can be read from two slaves 4 by the master 6 and written to two other slaves 4 by the master δ, simultaneously. The data can be written and read one word at a time, or can be written and read in blocks of words.

Referring now to Fig. 3, a single word transfer of data from the master to two slaves 4, or from two slaves 4 to the master 5 will now be described. The address and data are clocked through the communications bus 5 in this embodiment of the invention by a 40MHz clock signal. This is signal A of Fig. 3. An address strobe signal which is outputted by the controller 10 under the control of the master δ controls the transfer of the address. The address strobe signal is illustrated by the letter B in Fig. 3. A data strobe signal also outputted by the controller 10 under the control of the master δ controls the reading and writing of data. The data strobe signal is illustrated by the signal C in Fig. 3.

A read/write signal depending on whether data is to be read from the slaves 4 or written to the slaves 4 is also outputted by the controller 10 under the control of the master 6. The read/write signal is continuously high for a write instruction, and goes low for a read instruction. The read/write signal in the write form is illustrated by the high signal D in Fig. 3, while in the read form is illustrated by the signal F in Fig. 3.

The signal E in Fig. 3 illustrates the writing of a one word address and subsequently one word of data which is to be written from the master 6 to two slaves 8. Signal G illustrates reading of data by the master 6 from two of the slaves 8. In this embodiment of the invention, the address word is read on the falling edge of the strobe signal.

Fig. 4 illustrates a transfer of a block of data words which is written from the master to two addressed slaves 8. In this embodiment of the invention, similar timing is used for the transfer of the block of data words as is used for the transfer of a single data word as described with reference to Fig. 3.

However, the address strobe signal is kept low for the whole transfer cycle to signal the ongoing transfer.

Fig. 5 illustrates a transfer of a block of data words which is read by the master from two slaves 8. The timing of the transfer of the block of data words is similar to that described with reference to Fig. 3.

Fig. 6 illustrates a transfer of a block of data words in which two 15 bit subgroup are read by the master from two of the slaves 8 as a 32 bit word, and the respective 16 bit sub-groups are simultaneously written into two other slaves 8. The respective addresses of the two slaves 8 from which the data is to be read is issued in a one word address by the master 6, and this is followed by another one word address identifying the two slaves 8 to which the data is to be written. The block of the data words is then read one 32 bit word at a time, the 16 bit sub-groups being read from the two slaves 8 from which the data is to be read. Each 32 bit word is simultaneously written to the two slaves 8 to which it is to be written, one of the 16 bit sub-groups being written to one of the slaves 8 and the other 16 bit sub-group being written to the other slave 8. Which slave 8 receives which sub-group is determined by the second one word address, in other words the write address. Two additional strobes signals are required for this procedure, namely, an address strobe signal which is identified as AS-4 which causes the appropriate slaves to read the address, and a data strobe signal DS-4 which causes the read data to be written to the slaves to which the data is to be written.

Fig. 11 illustrates the composition of an address word. As discussed above, each address word is divided into an upper 16 bit sub-group and a lower 16 bit sub-group which identifies the two respective slaves 8 of the corresponding daughter cards 4 to be addressed. The first four bits of each 16 bit sub-group are not used. The next 4 bits of each 16 bit sub-group identify the slave 8 which corresponds to the daughter card 4 to be addressed. The identification of the slave 8 is provided as a binary number. The remaining 8 bits of each 16 bit sub-group contain an address of a device on the daughter card 4 to be addressed, typically a register or the like.

On a request from the host bus to write data to or to read data from a daughter card, the request is delivered to the master 6 which converts the request into request protocol of the control system. The request operation is divided into a sequence of separate steps which are represented in the electronics blocks illustrated in Fig. 7. An address decoder 30 receives addresses from the host bus which are detected within the address space of the master 6 and forwarded to a requester of the communication bus . A master bus controller 31 is responsible for the correct timing and error handling of the bus of the master 6 and depends on the standard of the host bus. A protocol generator 32 generates the protocol for the communications bus 5 after the master 6 had established a connection to the communications bus 5. Details of the protocol and its variance are set out in Table I. Address and data multiplexers 33 are controlled by the protocol generator 32 and provide the data buffering and multiplexing of the right address bus subset and data bus sub and superset. The details are dependent on the bus of the master 6. Address mapping is handled by a pattern and address register 34 which maps the addresses of the communications bus 5 to the internal addresses of the master, and this is dependent on the bus of the master 5.

The logic of the master 6 generates the signals set forth in Table II.

Referring now to Fig. 8 functional blocks of a controller of the slaves 8 are illustrated. A slave access 40 constantly monitors the address strobe request line and if the address strobe becomes active the addresses are stored and decoded. A request for activity is sent to the slave controller which is responsible for the daughter card to be addressed. An address decoder 41 stores the addresses received from the communications bus 5 and decodes the addresses for further use by the slave 8. A slave controller 42 controls all internal activities of the corresponding slave 8. The slave controller 42 generates the availability signal used by the controller 10 of the communications bus 5. A buffer 44 decouples the internal data path of the corresponding slave 8 from the communications bus. The slave functional block only requires a subset of the signals of the communication bus 5 and these are set forth in Table III.

Referring now to Figs. 9 and 10 the connection in parallel of each pair of daughter cards 4 to the mother board 7 will now be described. Each pair of daughter cards 4 are connected by two pins 20 and 21, and a third pin 22 engages the lower of the two daughter cards 4, namely, the daughter card 4A, the upper daughter card being identified as the daughter card 4B, The third pin 22 is an indicating pin 22 for indicating the daughter card 4A which is connected to the mother board 7 in the lower of the two positions. The indicator pin 22 which extends from the motor board 7 is held high until the lower daughter card 4A engages the indicator pin 22 at which stage the indicator pin 22 is pulled low. Electronic switches SO and SI are provided, and on the indicator pin 22 being pulled low, an input buffer BI relays the low signal to an output buffer B2 which inverts the signal to close the electronic switches SI and open the electronic switches SO. The following is a description of the operation of the circuit of Fig. 9. After power up and the internal configuration of the interfaces of the slaves 8, the potential on the indicator pin 22 is detected. In this embodiment of the invention, the slave interface is implemented in a field programmable gate array. The switches SO of the upper daughter card 4B are switched on, and the switches SI on the lower daughter card 4A are switched on.

The slave 8 then waits for the clock, which by default is switched off. After the reset pulse and the clock available signal, the internal logic is started while the availability signals are still inactive. The remaining logic of the field programmable gate array executes a self-test. If the self-test is passed as successful, the available signal is switched on via a three state buffer. At the same time, the logic for the interface buffer drivers become active. The daughter card is now accessible by the master for further initialisation. The availability signals can be read from the host controller to determine which daughter cards are available on the communications bus 5.

Table IV illustrates single word and block transfers which can be used in the following access types by the master.

It will be appreciated that many more than two daughter cards or two slaves may be addressed simultaneously by the master. The number of slaves which can be practically addressed by the master largely depends on the length of the data word issued by the master, and the length of the word which can be received by the slaves. This depends on the master bus and the slave buses. For example, should the master have a 64 bit bus, and each slave a 16 bit bus, then four slaves may be addressed simultaneously by forming four 16 bit sub-groups from the 64 bit data word issued by the master to be received by four slaves. The number of first temporary storing means, namely, first registers will depend on the number of sub-groups into which the data word is to be subdivided. Thus, where the data word is to be sub-divided into four sub-groups four first temporary storing means would be required. Thus, where N slaves are to be addressed by the master the data words issued by the master should be sub-divided into N subgroups, thereby, requiring N first temporary storing means.

Reading data from the slaves to the master is the inverse of writing, and the number of sub-groups of bits from the slaves which can be read simultaneously by the master will be similar to that described for writing to the slaves.

The invention is not limited to the embodiment hereinbefore described which mav be varied in construction and detail.

Claims (5)

1» A control system for communicating a master with a plurality of slaves over a bus in a digital communications system, wherein the master can communicate independently with at least two slaves simultaneously, the data being communicated in words, each having a predetermined number of bits, and a means is provided for separating each word into sub-groups of bits for reception by the respective slaves with which the master is simultaneously communicating so that each slave receives a different sub-group.

2. A control system as claimed in Claim 1 in which each word is divided into N sub-groups of equal length, where Ii is the number of slaves to be independently communicated with simultaneously, and is an integer equal to or greater than 2.

3. A control system as claimed in Claim 2 in which the integer N by which each word is to be sub-divided into sub-groups is equal to 2 n where n is an integer equal to or greater than 1.

4. A control system as claimed in Claim 2 or 3 in which the means for separating each word into the respective N sub-groups comprises Si first temporary storing means for storing the respective subgroups of bits, the capacity of each first temporary storing means corresponding to the number of bits of the sub-group of bits which are to be stored in that first temporary storing means, the respective first temporary storing means being arranged so that each word is stored in the respective sub-groups in the respective first temporary storing means, and a means is provided for enabling each first temporary storing means and the slaves to be communicated with, so that each slave to be communicated with receives the sub-group of bits to be transmitted 5. To it from the corresponding first temporary storing means.

5. A control system for communicating a master with a plurality of slaves over a bus in a digital communications system, the control system being substantially as described herein with reference to and as illustrated in the accompanying drawings.