IES70905B2 - Service channel bus for storage arrays - Google Patents

Abstract

The present invention relates to a storage array bus, in particular to a multidrop bus with attached service points, i.e. a "service channel" for use in data transfer and management of an array of storage devices, such as hard disks, optical disks, tape drives, etc., in a computer system.

Description

SERVICE CHANNEL BUS FOR STORAGE ARRAYS The present invention relates to a storage array bus, in particular to a multidrop bus with attached service points, i.e. a service channel for use in data transfer and management of an array of storage devices, such as hard disks, optical disks, tape drives, etc., in a computer system.

In order to address the problem of storage device failure and catastrophic loss of mission-critical data, it has been recognized that over-dependence on single hard disk data storage can be overcome to a large extent by using shared hard disks. Redundant Arrays of Inexpensive Disks (RAID) is a term used to describe present systems designed to replace a single large capacity disk drive with several smaller capacity disk drives, which may appear to the host system as a single device. Data is then shared or spread between the individual disk drives in the array, by various techniques including striping, mirroring, dual-copy, shadowing, or spanning, and an additional parity disk drive may be provided in the array for error-checking. Any one disk drive may fail, without catastrophic consequences, since full recovery is possible. Reconstruction and background regeneration of data on the array may be performed in a manner which is transparent to the host computer or network and operating system. It is also possible to replace a failed disk drive without shutting down the array, thus avoiding any downtime. Two or more disk drives in the array would have to fail simultaneously for data integrity to be compromised, and this is generally a very low probability, for example 500 X 10θ hours mean time between data loss. Increased levels of data protection and throughput are possible with the latest RAID systems which allow independent read and write operations to take place to separate disks in the array, and which store parity information on all disks, or even 570805 - 2 calculate parity on-the-fly. However, there can be a penalty to pay in slower input/output performance, in particular with some of the earlier RAID techniques, so that the choice of system (RAID-0 to RAID-10 standard) depends on the criteria for the level of data protection and input/output (1/0) performance requirements.

The individual disk drive devices in the array are stacked and mounted in a cabinet linked together by a Small Computer System Interface (SCSI) interface. A typical array comprises an array controller which manages and monitors a number of subsystems, including, for instance; a user 1/0 module a host connection a power supply unit bays for SCSI devices temperature probes and fans light-emitting diode (LED) indicator boards Each subsystem has individual status and control signals which need to be read or set/reset by the array controller. This results in two hardware design problems, namely; (a) the large number of interconnecting cables required between the array controller and the individual subsystems, and (b) that there is no common type of interface between the subsystem and the controller, i.e. caused by different signal types from power supply unit, temperature probes, fans, LEO boards, etc.

The present invention seeks to overcome these problems and to provide a storage array bus embodying a simple, more space-efficient * hardware design with a reduction in cabling requirements. The invention further seeks to provide a method of operating a data storage & array allowing a standard way for the array controller to manage the various status and control signals for a wide variety of subsystems and devices in a data storage array. - 3 Accordingly, the present invention provides a data storage array bus comprising a multidrop bus, and a plurality of attached service points each allowing an array controller to set or reset signals associated with a subsystem linked to a respective service point, and wherein access to the service points by the array controller is dependent upon a firmware-implemented protocol at the respective service point and a software algorithm implemented by the array controller.

The advantage of such a data storage array bus is that it provides a service channel and a standard way for the array controller to manage and communicate with various status and control signals for a wide variety of subsystem devices. A system will be described in which the service channel is embodied as one ten-strand multicore cable handling up to 192 subsystem signals, instead of employing individual cables for each subsystem.

Preferably, a data storage array bus in accordance with the invention comprises a service channel bus including a single data carrier or cable embodied as a 10-way flat ribbon cable, with N 10-way connections, where N represents the number of service points to be managed.

Each service point preferably comprises a service channel slave device appearing to the array controller as a set of read and write registers (for example, eight read and five write) on the service channel bus, and preferably having a hardwired service channel address (for example, up to eight addresses). A suitable slave device is an industry standard 16V8 or 20V8 PAL device. > The firmware-implemented protocol is preferably a two-stage protocol allowing up to 64x3 bit registers to be accessed with only 3 ·» address lines, equivalent to 192 read/write signals in an array allowing 2x192 signals to be multiplexed onto a 10-bit bus. - 4 The software algorithm preferably has three phases including device selection, register selection within a device (read/write) and device-device deselection.

A preferred embodiment of the invention will now be described with reference to the accompanying drawings, in which: Figure 1 is a schematic diagram of a host computer connected to a data storage array.

Figure 2 is a schematic diagram of a prior art array controller and subsystem model, omitting all status signal interconnections to the array controller, for clarity, and Figure 3 is a schematic diagram of a data storage array bus according to the present invention and associated array controller and subsystem devices connected thereto.

A storage array may for example be a set of five to seven disk drives mounted in a cabinet and linked together by a SCSI bus. The array appears to a host as one or more logical SCSI devices though it is made up of several physical devices connected together, as illustrated in Figure 1.

With reference to Figure 1, a typical data storage array comprises the following subsystems; an array controller board 1, a user I/O module including LED indication board 2, a host connection 3, a host computer system 4, .-t power modules 5, bays 6 for SCSI devices 7, t temperature probes 8, fans 9. - 5 The above list is not exhaustive but merely indicates the number of subsystems which a disk array controller board may have to manage and monitor. Each subsystem has individual status and control signals which need to be read or set/reset by the controller, as shown diagrammatically in Figure 2.

From Figure 2 it can be seen that the number of signals that need to be set/reset or whose status needs to be read can be large and the type of signal is not homogeneous but varies from Power Supply Units (PSUs) to fans/temperature probes, LED indication boards, etc. This means that there is a large number of interconnect cables between the array controller and each subsystem. Furthermore, there is no common type of interface to the array controller.

The present invention provides an improved data storage array bus 10 which provides a single service channel which is illustrated in Figure 3. The service channel is a multidrop bus with attached service points 11. Each service point allows the array controller 12 to set/reset signals or to read status signals on a particular subsystem 13. Access to the service points is by a firmware-implemented protocol at the service point and a software algorithm running on the array controller.

From the above it can be seen the service channel provides a standard way for the controller to manage the various status and control signals for a wide variety of devices.

The service channel comprises the following elements; - a service channel cabling and a header, - a service channel - a service channel bus, i.e. a data or signal carrier including slave device, algorithm. - 6 Service Channel Bus The following signals are used in the service channel; -a0,al,a2 ;address lines aO to a2 -dO,dl,d2 ;data lines dO to d2 -phO ;service channel cycle in progress -phi ;service channel cycle in progress -ck ;clock signal -gnd ;ground signal All transactions occur on the rising clock edge. The service channel cycle in progress is encoded in the phO and phi signals as follows; phO= 0 ph1=0 phO= 0 phl=l phO= 1 phl=O phO= 1 phl=l select a service point read a selected service point write a selected service point broadcast write to all service points The service channel cable is implemented using a 10-way flat ribbon cable with *N* 10-way IDC connectors where 'Ν' is the number of service points to be managed.

Service Slave Device A service channel slave device is a service point. The service point appears to the array controller as a set of read and write registers on the service channel bus. The service point is implemented as a small device integrating the required service channel protocol.

An industry standard 16V8 or 20V8 PAL device is sufficient for managing most subsystems. The small size and low cost of the above devices makes the service channel cost-effective. Each device has a hardwired service channel address which is used by the array controller during the selection phase in order to select the device. i? - 7 Service Slave Algorithm The service channel software algorithm has three phases; -device selection -register selection within a device (read/write) -device-device deselection Using a two stage protocol to access the service point registers allows up to 64x3 bit registers to be accessed with only 3 address lines, i.e. eight service points each having eight internal registers of three bits. This is equivalent to 192 read/write signals in an array. The service channel therefore allows up to 2x192 signals to be multiplexed onto a 10 bit bus. In terms of individual cables this allows 2x192 two core cables to be replaced by a single 10-way multidrop ribbon cable.

Service Channel Slave Read Algorithm Output service point address on aO to a2 and dO to d2, phO=O and ph 1=0 toggle ck signal => device is selected Output service point internal register address on aO to a2, phO=O and phl=l toggle ck signal => service point register data is output on dO to d2 Service Channel Slave Write Algorithm Output service point address on aO to a2 and dO to d2, phO=O and ph 1=0 toggle ck signal, => device is selected Output service point internal register address on aO to a2, phO=l and phl=O Output service point data on dO to d2, phO =1 and ph1=0 toggle ck signal => service point register is updated with data on dO

Claims (5)

1. A data storage array bus (10) comprising a multidrop bus, and a plurality of attached service points (11) each allowing an array controller (12) to set or reset signals associated with a subsystem (13) linked to a respective service point, and wherein access to the service points by the array controller is dependent upon a firmware-implemented protocol at the respective service point and a software algorithm implemented by the array controller.

2. A data storage array bus in accordance with claim 1, comprising a service channel bus including a single data carrier or cable embodied as a 10-way flat ribbon cable, with N 10-way connections, where N represents the number of service points to be managed.

3. A data storage array bus in accordance with claim 1 or claim 2, wherein each service point comprises a service channel slave device appearing to the array controller as a set of read and write registers on the service channel bus, preferably having a hardwired service channel address.

4. A data storage array bus in accordance with claim 2 or claim 3, wherein the firmware-implemented protocol is a two-stage protocol allowing up to 64x3 bit registers to be accessed with only 3 address lines, equivalent to 192 read/write signals in an array allowing 2x192 signals to be multiplexed onto a 10-bit bus, or wherein the software algorithm has three phases including device selection, register selection within a device (read/write) and device-device deselection.

5. A method of operating a data storage array allowing a standard way for the array controller to manage the various status and control signals for a wide variety of subsystem and device components in a data storage array, for example in a Redundant Array of Inexpensive Disks (RAID) system, substantially as herein described with reference to and as shown in Figure 3 of the accompanying drawings.