IES66230B2 - Microprocessor real time clock - Google Patents

Abstract

In a microprocessor real time clock first signals (Int#2) produced by dividing the output of a crystal oscillator are counted to determine nominal fractions of a second, and the nominal fractions of a second are counted to determine the time. Second signals (Int#4) derived from the mains are used to adjust the counting of the first signals or the counting of the nominal fractions of a second to compensate for drift in the crystal oscillator frequency.

Description

MICROPROCESSOR REAL TIME CLOCK This invention relates to a real time clock for a microprocessor based system, for example for a microprocessor based control panel for an alarm system.

Conventionally, a microprocessor real time clock is updated, by a timer interrupt routine triggered at nominally fixed intervals (for example, every 256us) by a tinier driven by the system's crystal. oscillator. Since such crystals have an inherent inaccuracy, often compounded by tolerances in the related circuitry, this can lead to a substantial loss or gain over long periods.

It is an object of the invention to provide a microprocessor real time clock having improved accuracy.

Accordingly the invention provides a microprocessor real time clock in which first signals produced by dividing the output of a crystal oscillator are counted to determine nominal fractions of a second, in which the nominal fractions of a second are counted to determine the time, and in which second signals derived from the mains are used to adjust the counting of the first signals or the counting of the nominal fractions of a second to compensate for drift in the crystal oscillator frequency.

An embodiment of the invention will now be described, by way of example, with reference to the accompanying drawings, in which: Figure 1 is a schematic block diagram of a microprocessor and various variables and interrupts relevant to the present embodiment, and Figures 2(a) to 2(d) are interrupt routines triggered by respective ones of the interrupts in figure 1.

S6623Q -2Referring to the drawings, a microprocessor 10 (which in this embodiment is assumed to control an alarm system) is responsive to interrupts #1 to #4 which occur at different frequencies FI to F4 and trigger the respective interrupt service routines whose flow diagrams are shown in figures 2(a) to 2(d). These interrupt routines update or reset a number of variables identified in figure 1 as CYCLE TIMER, TIMER REF, ALTJNT, 16THS CTR and SIXTNTHS. The values of 'these variables are held in dedicated registers or in RAM in a known manner.

Interrupt #1 is derived from the mains, which is assumed in this case to be at 50Hz, and therefore occurs every l/50th of a second (20ms). Interrupt #2 is derived from the crystal oscillator by dividing the frequency of the crystal by a constant. In this case the crystal has a nominal frequency of ISMhz which is divided by 7680 to provide interrupt #2 nominally every 512 microseconds (us). Interrupt #3 is also derived by division of the crystal oscillator frequency, and occurs approximately every S' milliseconds (ms). Finally, interrupt #4 occurs every second, and is derived by dividing the mains frequency by 50. These interrupts can be generated in a known manner.

Interrupt #1 simply resets the variable CYCLE TIMER every l/50th of a second, as seen in the flow diagram of figure 2(a), The significance of this will be described in relation to figure 2(b).

Referring now to figure 2(b), interrupt #2 occurs nominally every 512us. However, in the description which follows, and until stated otherwise, we will assume that interrupt #2 occurs precisely every 512us. Of course, the present invention is predicated on the fact that the crystal is not accurate, and that interrupt #2 does not occur precisely at 512us intervals, so ultimately a correction will have to be made for this. This is dealt with by the interrupt routine whose flow diagram is shown in figure 2(d). However, for tire time being we will assume that interrupt #2 does occur precisely at 512us intervals.

Interrupt #2 first increments CYCLE TIMER (step 20) following which the value of CYCLE TIMER is examined to see If it is greater than 44 (step -322). The purpose of this is to see if the mains is missing. Since 44 times 512us is greater than 22ms the value of CYCLE TIMER will not normally reach 44» since it is reset every 20ms by interrupt #1 as described above. However, if the mains is missing, CYCLE TIMER will not be reset and therefore a value greater than 44 indicates that the mains is missing. This is used to signal a fault detector (not shown) and the fault is logged.

Following the check on the value of CYCLE TIMER the value ALTJNT is incremented (step 24). Thus ALT_INT keeps a running count of 512us periods.

Next, step 26, the value of ALTJNT is compared with a reference value held in TIMER REF. The value of TIMER REF is established, as will be described with reference to figure 2(c), so that ALTJNT = TIMER REF after each nominal 1/16th second. When ALTJNT ~ TIMER REF the variables 16THS CTR and SDCTNIHS are incremented and ALTJNT is itself reset (step 28). Thus the variables 16THS CTR and SKTNTHS keep a running count of nominal l/16th seconds.

We use the expression nominal l/16ths second because 512us is not integrally dividable into l/16th second. Thus 122 x 512us periods equals 62.464ms which Is 36us short of a l/16th second, and 123 x 512us periods equals 62.976ms which is 476us longer than a 1/16th second. Thus if TIMER REF were fixed at 122 all the nominal l/16ths second counted by SDCTNTBS would be too short, whereas if TIMER REF were fixed at 123 all the nominal l/16tlas second counted by SEXTNTHS would be too long.

Accordingly, TIMER REF Is varied according to the following scheme. If we consider a cycle of 128 nominal l/16th seconds as determined by ALTJNT == TIMER at step 24: TIMER REF is set at 122 for the first 120 nominal l/16ths second.

TIMER REF is set at 123 for the next 7 nominal l/16ths second.

TIMER REF is set at 124 for the final 1 nominal l/16ths second. -4 The total duration of the cycle is thus given by: 120 x 122 x 512us = 7495680us x 123 x 512us = 440832ns 1 x 124 x 512us = 63488us TOTAL 8i US Thus, on the assumption made above that interrupt #2 occurs precisely at 512us intervals, after an 8 second period the 128 nominal l/10th seconds will exactly equal 8 seconds, even though during the course of the cycle none of the nominal l/16th seconds will align exactly with objective time. Nevertheless, after each cycle of 128 nominal l/16th seconds value of SDCTNTHS will be correct.

The above described setting of TIMER REF is accomplished by the interrupt routine whose flow diagram is shown in figure 2(c).

In response to each interrupt #3 the value of 16THS CTR is examined, step , it being recalled that 16THS CTR registers each nominal l/16th second detected at step 26, figure 2(b). If the value of 16THS CTR has changed step 32 detennines whether the present value is 120 and if so the TIMER REF value Is set to 123 at step 33. If the value of 16THS CTR is not 120 at step 32, step 34 determines whether the present value is 127 and if so the TIMER REF value is set to 124 at step 35. Finally, If the value of 16THS CTR is not 127 at step 34, step 36 detennines whether the present value is 128 and if so the TIMER REF value is set to 122 at step 37 and at the same time 16THS CTR Is reset to 122. The result is that during a cycle of 128 nominal l/16ths second TIMER REF Is set to 122 for 120 of the nominal l/16th seconds, to 123 for 7 of the nominal l/16th seconds, and to 124 for 1 of the nominal l/16th seconds. Naturally interrupt #3 has to occur sufficiently often to guarantee detecting each change in the value of I6THS CTR, and this Is satisfied by having interrupt #3 occur every 9ms. i.e. about 7 times the rate of change in the value of 16THS CTR.

A separate real time clock routine 38, figure 1, examines the value of the - 5 variable SIXTNTHS which, like the variable 16THS CTK, keeps a running count of nominal l/16th seconds, and by division by 16 determines when each second has passed and updates the real time clock accordingly. The time thus updated will only be accurate once every 8 seconds, but the very small deviations at each intermediate second are quite acceptable for all normal purposes.

The foregoing description assumes that interrupt #2 occurs precisely every 512us. Of course, in practice it will not run accurately, so that over a relatively long period of time the real time clock will drift fast or slow.

This is corrected by the interrupt routine shown in figure 2(d) which is triggered every second by the interrupt #4. if the crystal oscillator is running reasonably accurately so that interrupt #2 is produced almost precisely at 512us intervals, then at each successive second as determined by the occurrence of interrupt #4 the value of ALTJNT should 'be within a narrow range centered on the current value of TIMER REF, say within the range 90 to 30. This is because ALTJNT v/ill either have been reset a short time before (in. the case where TIMER REF = 122) or will be reset a short time afterwards (in the case where TIMER REF = 123 or 124). However, if ALT_INT is significantly outside this narrow range, then inaccuracy in the crystal is causing drift which has io be corrected.

Accordingly, steps 40 and 42 of figure 2(d) determine upon the occurrence of each interrupt #4 whether the current value of ALTJNT lies inside the range 60-90 or 30-60 respectively. If the former the crystal is running slow and the variable SIXTNTHS Is incremented by 1 at step 44, and if the latter the crystal is running fast and the variable ALTJNT is immediately reset at step 46. This will tend to correct for the drift, and bring ALTJNT within the desired range 90-30. Of course it will fee understood that the range 90=30 is quite arbitrary, and depends upon how much it is permissible to let the crystal timing drift without correction.

. Of course, if the mains is absent, as detected at step 22, figure 2(b), there will be no intermpt 4 so that the crystal timing will drift uncorrected. -6However, this is tolerable as mains is not usually out for more than a few hours at a time.

While the invention has been described in terms of a 50Hz mains and the 5 detection and counting of nominal l/16ths of a second, the invention is not limited to these particular values. Any mains signal can be divided by an integer to produce an interrupt every one second. Also, the crystal frequency can be divided by various constants so that, for example, the technique described above could detect drifts in lOths or lOOths of a secoxid intervals derived from a 10MHz crystal oscillator.

Claims (5)

1. A microprocssso;· real time clock in which first signals produced by dividing the output of a crystal oscillator are counted to determine nominal fractions of a second, in which the nominal fractions of a second are counted to determine the time, and in. which second signals derived from the mains are used to adjust the counting of the first signals or the counting of the nominal fractions of a second to compensate for drift in the crystal oscillator frequency.

2. A microprocessor real time clock as claimed in claim 1, in which each nominal fraction of a second is registered when the number of first signals reach a reference count, and in which die reference count varies cyclically such that at the end of each cycle the plurality of nominal fractions of a second will add up to an exact number of seconds in the absence of drift in the crystal oscillator frequency.

3. A microprocessor real time clock as claimed in claim 2, in which the first signals occur nominally every 512us, ‘the nominal fraction of a second is l/16th of a second, the cycle period is 128 nominal l/16ths of a second, and the reference count is 122 for 120 of the nominal l/16ths of a second, 123 for 7 of the nominal l/16ths of a second and 124 for one of the nominal l/16ths of a second.

4. A microprocessor real time clock as claimed in claim 1, 2 or 3, in which the said adjustment is made if the number of first signals counted lies outside a given range upon the occurrence of a second signal.

5. A microprocessor real time clock substantially as described herein with reference to the accompanying drawings.