IE792292L - Circuit arrangement - Google Patents

Circuit arrangement

Info

Publication number
IE792292L
IE792292L IE229279A IE229279A IE792292L IE 792292 L IE792292 L IE 792292L IE 229279 A IE229279 A IE 229279A IE 229279 A IE229279 A IE 229279A IE 792292 L IE792292 L IE 792292L
Authority
IE
Ireland
Prior art keywords
circuit arrangement
arrangement
circuit
Prior art date
Application number
IE229279A
Other versions
IE48664B1 (en
Original Assignee
Hasler Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hasler Ag filed Critical Hasler Ag
Publication of IE792292L publication Critical patent/IE792292L/en
Publication of IE48664B1 publication Critical patent/IE48664B1/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/06—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
    • H04L25/068—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection by sampling faster than the nominal bit rate

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Power Engineering (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
IE229279A 1978-12-05 1979-11-29 Circuit arrangement for regenerating an isochronous data signal IE48664B1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CH1239178A CH635965A5 (en) 1978-12-05 1978-12-05 DEVICE FOR REGENERATING AN ISOCHRONOUS DATA SIGNAL.

Publications (2)

Publication Number Publication Date
IE792292L true IE792292L (en) 1980-06-05
IE48664B1 IE48664B1 (en) 1985-04-03

Family

ID=4382562

Family Applications (1)

Application Number Title Priority Date Filing Date
IE229279A IE48664B1 (en) 1978-12-05 1979-11-29 Circuit arrangement for regenerating an isochronous data signal

Country Status (5)

Country Link
EP (1) EP0011746B1 (en)
CH (1) CH635965A5 (en)
DE (1) DE2964746D1 (en)
IE (1) IE48664B1 (en)
YU (1) YU296279A (en)

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3548309A (en) * 1967-09-14 1970-12-15 Bell Telephone Labor Inc Data rate converter
US3668315A (en) * 1970-05-15 1972-06-06 Hughes Aircraft Co Receiver timing and synchronization system
NL7111888A (en) * 1971-08-28 1973-03-02

Also Published As

Publication number Publication date
EP0011746A1 (en) 1980-06-11
DE2964746D1 (en) 1983-03-17
IE48664B1 (en) 1985-04-03
EP0011746B1 (en) 1983-02-09
YU296279A (en) 1982-06-30
CH635965A5 (en) 1983-04-29

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