IE48664B1 - Circuit arrangement for regenerating an isochronous data signal - Google Patents

Abstract

1. A circuit arrangement (8) for regenerating an isochronous data signal which consists of data (Fig. 3, signal a) and data timing (Fig. 3, signal b) having the timing frequency fD and which is scanned in a transmitter by a scanning signal (Fig. 3, signal c) which is plesichronous for same and which has a higher timing frequency fA , is transmitted by way of a line (4) as a sequence of scanning elements (Fig. 3, signal d) with this frequency (fA ) and is received by a receiver (5), in which respect this receiver has the following units : - a regenerator circuit for regenerating the scanning elements (Fig. 3, signal f), - a detector for determining data transitions of the scanning elements (Fig. 3, signal h), - a regenerator for the data timing (Fig. 3, signal g) ; and in which respect the circuit arrangement (8) which is connected to the receiver (5) has the following units : - a frequency generator circuit consisting of a controllable oscillator (14) for generating a timing signal having the timing frequency f1 of a first divider (15) with a constant ratio of division for generating a first timing signal (Fig. 3, signal i) having the timing frequency f2 , and of a second divider (16) with a controllable ratio of division for generating a second timing signal (Fig. 3, signal k) having the timing frequency f3 , in which respect the timing frequency f2 corresponds to the higher timing frequency fA and the timing frequency f3 corresponds to the timing frequency fD and in which respect the timing frequency f1 corresponds to the least common multiple of the data timing frequency (fD ) and of the frequency (fA ) of the scanning signal, as well as of a first phase comparator (13) for comparing the data timing (Fig. 3, singal g) with the first timing signal (Fig. 3, signal i) for generating a control singal for the oscillator (14), - a control input (21) of the second divider (16) for the input of control signals, by reason of which individual timing segments of the second timing signal having the frequency f3 are in each case variable in length by a fixed amount, - an output circuit (28) in which the second timing signal scans the regenerated scanning elements (Fig. 3, signal f) and at the output (9) of which (28), upon correct scanning phase relationship, the regenerated data signal is tappable ; characterised - by a scanner (22) which is connected to the outputs of the dividers (15, 16) and which scans the second timing signal (Fig. 3, signal k) in relation to the first timing signal (Fig. 3, signal i), whereby there ensues at its output (23) a master signal (Fig. 3, signal m), flanks of which designate the points in time at which data transitions of the scanning elements are to be expected, - by a second phase comparator (25), a first input (23) of which is connected to the scanner (22), a second input (11) of which is connected to the detector for determining the data transitions of the scanning elements, and the output (20) of which is connected to at least one control input (21) of the second divider (16), and which within a predetermined phase region constantly checks whether the data transitions of the scanning elements (Fig. 3, signal k) occur in-phase with the master signal flanks (Fig. 3, signal m) and which, upon each phase deviation, delivers a control signal to the second divider (16).

Description

The invention relates to a circuit arrangement for regenerating an isochronous data signal consisting of data and a data clock, this data signal having been sampled in a transmitter by a plesiochronous sampling signal of higher frequency, transmitted via a line as a sequence of sampled elements and received by a receiver, the receiver being provided with regenerator circuits for regenerating the higher frequency and the sequence of sampled elements and with a detector for determining data transitions, and the circuit arrangement being provided with a regenerator for the data clock, with a phase-locked loop for setting the correct phase relationship for sampling and with a sampler for sampling the sequence of sampled elements by means of the in-phase data clock.

In order to regenerate a transmitted data signal it is always necessary to regenerate the clock. For this reason the problems of clock regeneration for digital character elements or for a data signal are known from the literature. This can be seen, for example, from Swiss Patent 604 440.

The regeneration of transmitted data signals is furthermore associated with the in-phase sampling of the transmitted signal by the regenerated clock signal. For lining up the correct sampling phase a phase control cir25 cuit is used. From the journal IEEE Transactions on Communications, Vol. Com-26, No.l, January 1978, page 35 45, a digital phase-locked loop is known which could be used for such a lining up of the sampling phase. It 664 - 3 consists of an oscillator, a variable divider, a phase comparator, a digital sequence filter and a feedback arrangement from the phase comparator via the filter to the variable divider. The phase comparator continuously compares the phase of an external input signal with the phase signals at the output of the variable divider. If during this process a phase shift is found the variable divider is given a control instruction, via the feedback arrangement, to change its dividing ratio once. By this means the phase of the output signal of the divider is changed step by step until the phase comparator no longer detects a phase shift. The digital sequence filter serves as a buffer by letting through only periodic phase deviation signals and blocking single signals. This reduces the effect of isolated wrong decisions by the phase comparator on the phase relationship of the output signal.

If a data signal is being sampled by a sampling signal the frequency of which does not form an integral relationship to the frequency of the data signal, a sampling pattern is formed. This sampling pattern is an expression of the fact that the signal elements of the data signal are represented in a periodic sequence by a variable number of equivalent signal elements of the sampling signal.

If a sampled, isochronous data signal is transmitted via a line, it is the receiver's task to regenerate from the unequally long sequences of signal elements of equal value the data clock and the data as such. The circuit arrangement performing this task is characterised by a frequency generator circuit for generating a first frequ48664 - 4 ency which corresponds to a common multiple of the data clock frequency and to the frequency of the sampling signal, consisting of the units, arranged in a closed circuit in the manner of a phase—locked loop, of a control5 lable oscillator, a first divider and a first phase comparator, the dividing ratio of the first divider being constant and selected in such a manner that its output sig nal has a clock frequency which is identical to the frequency of the sampling signal, by a second divider which is connected to the output of the oscillator and to at least one control line and the dividing ratio of which is variable as a function of control signals on the control line in such a manner that with a missing control signal at the divider output a divider signal is produced the clock frequency of which is identical to the data clock frequency and that with the presence of a control signal the dividing ratio changes in each case once by a fixed amount by a first sampler which is connected to the outputs of the dividers and which samples the output signal of the second divider by means of the output signal of the first divider, due to which process at its output a pattern signal is produced the one edges of which mark the points in time at which data transitions are to be expected, and by a second phase comparator the two inputs of which are con25 nected to the sampler and to the output of the detector for determining data transitions and the output of which is connected to the control line, and which constantly checks, within a predetermined phase range, if there is a phase shift between an edge of the pattern signal and a data transition and which in the event of a phase shift - 5 supplies a control signal to the control line.

The invention accordingly provides a circuit arrangement for regenerating an isochronous data signal which consists of data and data timing having the timing frequency fD and which is scanned in a transmitter by a scanning signal which is plesichronous for same and which has a higher timing frequency fA, is transmitted by way of a line as a sequence of scanning elements with this frequency (fA) and is received by a receiver in which respect this receiver has the following units : -a regenerator circuit for regenerating the scanning elements, -a detector for determining data transitions of the scanning elements, ->a regenerator for the data timing; and in which respect the circuit arrangement which is connected to the receiver has the following units: a frequency generator circuit consisting of a controllable oscillator for generating a timing signal having the timing frequency f^ of a first divider with a constant ratio of division for generating a first timing signal having the timing frequency f2, and of a second divider with a controllable ratio of division for generating a second timing signal having the timing frequency f3, in which respect the timing frequency f2 corresponds to the higher timing frequency fft and the timing frequency f^ corresponds to the timing frequency fD and in which respect the timing frequency f^ corresponds to the least common multiple of the data timing frequency (fD) 6 64 - 6 and of the frequency (fA) of the scanning signal, as well as of a first phase comparator for comparing the data timing with the first timing signal for generating a control signal for the oscillator, a control input of the second divider for the input of control signals, by reason of which individual timing segments of the second timing signal having the frequency are in each case variable in length by a fixed amount, an output circuit in which the second timing signal scans the regenerated scanning elements and at the output of which, upon correct scanning phase relationship, the regenerated data signal is tappable; characterised by a scanner which is connected to the outputs of the dividers and which scans the second timing signal in relation to the first timing signal, whereby there ensues at its output a master signal, flanks of which designate the points in time at which data transitions of the scanning elements are to be expected, by a second phase comparator, a first input of which is connected to the scanner, a second input of which is connected to the detector for determining the data transitions of the scanning elements, and the output of which is connected to at least one control input of the second divider, and which within a predetermined phase region constantly checks whether the data transitions of the scanning elements occur in-phase with the master signal flanks and which, upon each phase deviation, delivers a control signal to the second divider. 4.8664 - 7 The said circuit arrangement works digitally. This produces an extremely simple and interference-proof control characteristic.

In the text which follows the invention is described in greater detail by way of example with the aid of three Figures, in which: Figure 1 shows a simple block diagram of a transmission system, Figure 2 shows a circuit arrangement for regenerating the data clock and the data signal, and Figure 3 shows timing diagrams of signals occurring in Figure 1 and Figure 2.

Figure 1 shows a simple block diagram of a transmission system. 1 is a transmitter with three inputs 2.1, 2.2, 3 and one output which is connected to transmission line 4. Via the inputs 2 isochronous data signals with a clock frequency f^, for example with a frequency of 9.6 kBits/s, and the associated data clock of 9.6 kHz are input. Via the third input 3 a sampling signal is input.

This has a second, higher clock frequency f and is used to sample the data signal on line 2.1. The second frequency fA could be, for example, 32 kHz and 3fA could have a plesiochronous relationship to 10fD.

By way of an example, in Figure 3a a bit sequence 10011100 of the data signal is represented in digits and as a diagram ( with the time scale t from left to right).

The associated data clock fD is shown in Figure 3b, with constant fundamental periods of 1/f^. Figure 3c shows the sampling signal with a frequency f&. The sequence of samp4-8 0 64 - 8 led elements, produced by the sampling in the transmitter, with the shorter fundamental period l/fA is shown in Figure 3d. The digits illustrate that the sampling at a frequency fA, which is not an integral multiple of the frequency fD, produces a periodic sampling pattern due to the fact that alternately a different number of sampled elements with a fundamental period of l/fA corresponds to a signal element with the fundamental period l/ίθ of the data signal. In the example chosen the sampling pattern has the sequence 3-3-4.

The sequence of sampled elements (Figure 3d) is output by the transmitter 1 to the transmission line 4.

This line can be of any design. It can transmit the data elements and the data clock on a common wire or on separ15 ate wires. The receiver 5 receives the signals and regenerates, with the aid of a known first control loop, the frequency of the transmission clock (Figure 3g) which is identical with sampling frequency fA, and the sequence of the sampled elements (Figure 3f) transmitted. In addition the receiver 5 determines the time of occurrence of data transitions in the transmitted sequence (Figure 3h). These changes correspond to the edges of the data signal of Figure 3a. Figures 3f, 3g and 3h show these signals determined by the receiver 5.

With faultless transmission the distances between the detected data transitions correspond to combinations, corresponding to the sampling pattern, of 3 and 4 fundamental periods l/fA of the sampling frequency, that is to say, 3, 4, 6, 7, 10, 13 and so forth fundamental periods. In order to regenerate the isochronous data signal, the job - 9 is to convert this varying data sequence {Figure 3h), -which corresponds to the sampling pattern and the data signal, into a sequence in which the distances between edges are integral multiples of the fundamental period l/fD of the data signal. This means regeneration of the isochronous data clock fQ. This job is made more difficult by the fact that regeneration of the data signal must be ensured even if the sampling pattern is occasionally interfered with by errors in synchronisation (bitslips) or by transmission errors. Synchronisation errors correspond to insertions or omissions of one fundamental period l/fA and thus lengthen or shorten the transmission sequence by one fundamental period. This is indicated, for example, in Figure 3f by an arrow and by omitting one fundamental period l/fA8 is a circuit arrangement which.solves the abovementioned problem by using the regenerated clock frequency fA> the sequence of regenerated, transmitted sampled elements and the detected data transitions of this sequence, arriving via the lines 6, 7 and 11. The circuit arrangement 8 is provided with two outputs 9 and 10 at which the regenerated, isochronous data signal and its data clock fQ can be picked up.

Figure 2 shows the circuit arrangement 8 for regenerating the data clock fQ and the data signal. According to Figure 1, the clock frequency fA is input via line 6, the sequence of sampled elements via line 7 and the data transitions via line 11. is a phase comparator, 14 a controllable oscillator and 15 a first divider. Together, these three units 8 6 6 4 - 10 form a frequency generator circuit in the manner of a phase-locked loop. The dock frequency f& is input to the phase comparator via the line 6. Controlled by the voltage supplied by the phase comparator, the oscillator 14 oscil, 5 lates at a frequency f3 which is, for example, higher than the frequency fA by a factor of 3. At the output 18 of the first divider 15, with a dividing ratio which corresponds to the aforementioned factor of 3, a signal with the frequency f2 is produced which is equal to the frequency 10 fA* In addition, the output of the oscillator 14 is connected to a second divider 16 the dividing ratio of which is selected in such a manner that at its output 17 a signal with the frequency is produced which is iden15 tical to the data clock frequency fp.

Thus the frequency f^ is a common multiple of the frequencies fA and fp or f2 and f^. If f^ is the smallest common multiple then = 96 kHz for the illustrative frequencies fp = 9.6 kHz and fA = 32 kHz.

The second divider 16 is provided with a variable dividing ratio which can be affected by control signals on a control line 20, 21 connected to it. In general, the dividing ratio is 1 : n. This standard dividing ratio, however, can be increased or decreased non-repetitively by a fixed amount, for example by 1. In other words, this means that the counter.contained in the divider 16, when triggered by a control signal, non-repetitively counts either to (n+1) or only to (n-1) instead of to a final count n.

The outputs 18 and 17 of the two dividers 15 and - 11 16 are connected to a sampler 22. This sampler samples the output signal of the second divider 16 (Figure 3k) by means of the output signal of the first divider 15 (Figure 3i). This process is similar to the sampling of the data signal in the transmitter 1. At the output 23 of the sampler 22 a pattern signal (Figure 3m) is produced. The one edges of the pattern signal, for example the positive edges, have periodically changing distances which correspond to a varying number of fundamental periods l/f2 or l/f^’ At the frequencies selected this corresponds to a sampling pattern of 3-3-4. Thus the positive edges of the pattern signal correspond to the edges of the sampling pattern which is generated by the transmitter 1. Figure 3m shows the pattern signal on line 23. The positive edges of the pattern signal mark the times at which data transitions are to be expected on line 11. is a second phase comparator the inputs of which are connected to the lines 11 and 23. The phase comparator 25 decides in each case within a predetermined comparison interval if a data transition is appearing before or after a positive edge of the pattern signal or at the same time with it. With non-simultaneity, the variable divider 16 is supplied via the control lines 20, with a control signal which non-repetitively changes the dividing ratio of the divider 16 in the manner discussed. If no data transition occurs on line 11 within the comparison interval, no control signal appears on the lines 20, 21.

The circuit arrangement 8 works as a regenerator for the data signal and as a digital phase controller. - 12 With the oscillator 14, the dividers 15 and 16 and the sampler 22 a pattern signal is produced the distances between the positive edges of which correspond to the sampling pattern at the transmitter 1. The phase comparison in the phase comparator 25 produces control signals which in each case, by non-repetitively changing the dividing ratio in the divider 16, cause phase shifts in the positive edges of the pattern signal in steps of 1/f^. The step-by-step phase shifts are repeated until the data transitions on line 11 always occur simultaneously with the positive edges on line 23. This is the desired inphase condition.

If during the transmission a bitslip occurs due to a synchronisation error, this will produce the effect that the phase comparator 25 detects a repeated regular phase deviation in one direction. A digital sequence filter 27 which is inserted into the control line 20 differentiates between control signals which are produced by isolated faulty data transitions and regularly repeated control signals which are produced due to a bitslip. To this end,the filter checks if during a predetermined time interval several or only one control signal arrives via the line 20. If on line 20 control signals of the same type occur regularly they are output to the line 21 by the filter 27. On the other hand, isolated control signals are not transmitted. This brings the advantage that not every deviation immediately leads to a control movement. This effectively suppresses the effect of transmission errors.

Figure 3 shows an example of the control process. 4-866 4 - 13 At the time indicated by an arrow in Figure 3f an element is omitted in the sequence of the transmitted sampled elements. This causes each subsequent data transition to be shifted by one fundamental period l/fA· Thus in the examp5 le of Figure 3f, between the data transitions the following distances are produced (from left to right): 3, 7, 9, and so forth fundamental periods l/fA· lu the in-phase condition the positive edges of the pattern signal (Figure 3m) always occur simultaneously with the changes in bit value (Figure 3h). In Figure 3n this is shown by simple arrows. After the omission of the sampled element the next data transition appears before its associated edge signal in time. This is recognized as a phase deviation and is shown by a double arrow in Figure 3n. The phase deviation triggers a control signal on the line 20, 21 in the manner described (not taking into consideration the filter 27 at the moment). This causes the dividing ratio to be changed in the counter 16 which causes one distance between edges of the output signal of the second divider 16 to be shortened by 1/fp This is indicated in Figure 3k by a horizontal arrow.

The change in the signal on the line 17 which has been described produces in the pattern signal on the line 23 a jump in the sampling pattern 3-3-4. In the time sequ25 ence of the phase readjustment the isochronous and non-isochronous occurrence of data transitions and pattern-signal edges alternate with one another. Each non-isochronous occurrence leads to a further control step which again produces a lined-up, in-phase condition. 4-8 6 6 4- 14 As has been described, two different control signals are used for changing the dividing ratio of the divider 16. The one control signal increases and the other control signal descreases the dividing ratio 1 ! n. This produces a control process which, after the omission or insertion of an element, restores the correct phase relationship in three single steps. In this process each single step is triggered by a data transition. This is why the duration of a complete control process depends on the frequency of data transitions.

Variants of the circuit arrangement can consist in that for each control signal the dividing ratio is changed by more than 1, for example by the value of 3 fromn to n-3 or n+3. This changes the control speed.

Another variant consists in that control is effected basically only in one direction. Due to the periodicity of the sampling pattern 3-3-4 it is possible to change the dividing ratio constantly in the same direction and, with sufficiently frequent repetition, to reach the correct 2o phase relationship again in this manner. With this process, though, errors occur in the regenerated data signal during the control process which really should be avoided. Instead of the series-connected control lines 20, 21, 22, on which two different control signals are used, of course two separate control lines can also be provided which are allocated to the two types of control signals.

In a preferred embodiment, the digital sequence filter 27 is a shift register the contents of which are shifted on on line 20 by each control signal and which is reset to its initial position at regular intervals or after - 15 each completed correction. It only outputs signals to line 21 if between two resets a number of control signals of one type arrives which corresponds to the number of places in the register or predominates accordingly if both types are occurring. Instead of the said reset at regular intervals, the shift register can also be brought back step by step into its reset position in periods of in-phase operation.

The circuit arrangement 8 is capable of working properly also if the data signal has a clock frequency f*D which is reduced by the factor of 2 or 4 or 8 with respect to the clock frequency fQ. For these new, slower clack frequencies f*D and the unaltered sampling frequency f^ f1 is also a common multiple. In these cases the sampling unit 22 generates an unaltered sampling pattern 3-3-4 which now no longer agrees with the sampling pattern generated by the transmitter 1. Since in the undisturbed case, however, each second (or fourth, and so on) positive edge o f the pattern signal in each case does not correspond to a data transition, and since in each case this does not lead to a control signal, an effect is produced as if only every second (fourth, and so on) pattern signal edge were being generated. This then corresponds to a sampling pattern of 6-7-7 (or 13-13-14, and so on) such as is being generated with the corresponding sampling process in the transmitter 1.

The unit 28 is used for regenerating the data signal. This unit is a flip flop the D input of which is connected to the line 7 and-the clock input of which is connected to the line 17. In this way the regenerated 4-8 6 6 4 - 16 sequence of sampled element is sampled periodically at a frequency via the clock input. In the adjusted condition the sampling phase has such a position that, independently of the sampling pattern and of the sequence in which the sampled elements occur, in each case sampling values are obtained which correspond to the values of the data signal at the transmitter 1.

If a synchronisation error causes a bitslip to occur this will produce a phase shift between the pattern signal edges and the data transitions. In the example chosen, this places the relative sampling phase into a critical sampling area. Even though no errors occur during sampling, a second synchronisation error would lead to a faulty data signal if the nominal phase relationship were not restored in the meantime. The sampled signal appears as a new data signal on line 9. Its associated data clock can be obtained from line 10 which represents the output of line 17.

A detailed description of the technical design of the units 22 and 25 can be omitted. Essentially, these units are D-type flip flops the circuitry of which is known from the literature.

Except for the oscillator 14 and its drive, not shown, the circuit arrangement works purely digitally. It can be constructed with simple components which are commercially available and it does not require any adjusting. It is insensitive to isolated interference, corrects isolated synchronisation errors relatively rapidly and in the absence of interference remains constant in its in30 phase condition. With these characteristics it fulfills - 17 all the demands made of the circuit arrangement according to the introduction to the description.

Claims (8)

1. CLAIMS:10

1. A circuit arrangement for regenerating an isochronous data signal which consists of data and data timing having the timing frequency f D and which is scanned in a transmitter by a scanning signal which is plesichronous for same and which has a higher timing frequency f^, is transmitted by way of a line as a sequence of scanning elements with this frequency (f A ) and is received by a receiver in which respect this receiver has the following units: -a regenerator circuit for regenerating the scanning elements, -a detector for determining data transitions of the scanning elements, -a regenerator for the data timing; and in which respect the circuit arrangement which is connected to the receiver has the following units: a frequency generator circuit consisting of a controllable oscillator for generating a timing signal having the timing frequency f^ of a first divider with a constant ratio of division for generating a first timing signal having the timing frequency f 2 , and of a second divider with a controllable ratio of division for generating a second timing signal having the timing frequency f 2 , in which respect the timing frequency f 2 corresponds to the higher timing frequency f A and the timing frequency f^ corresponds to the timing - 19 frequency f D and in which respect the timing frequency fj corresponds to the least common multiple of the data timing frequency (f^) and of the frequency (f A ) of the scanning signal, as well as of a first phase comparator for comparing the data timing with the first timing signal for generating a control signal for the oscillator, a control input of the second divider for the input of control signals, by reason of which individual timing segments of the second timing signal having the frequency f^ are in each case variable in length by a fixed amount, an output circuit in which the second timing signal scans the regenerated scanning elements and at the output of which, upon correct scanning phase relationship, the regenerated data signal is tappable; characterised -by a scanner which is connected to the outputs of the dividers and which scans the second timing signal in relation to the first timing signal, whereby there ensues at its output a master signal, flanks of which designate the points in time at which data transitions of the scanning elements are to be expected, — by a second phase comparator, a first input of which is connected to the scanner, a second input of which is connected to the detector for determining the data transitions of the scanning elements, and the output of which is connected to at least one control « Λ8664 - 20 input of the second divider, and which within a predetermined phase region constantly checks whether the data transitions of the scanning elements occur in-phase with the master signal 5 flanks and which, upon each phase deviation, delivers a control signal to the second divider.

2. A circuit arrangement as claimed in claim 1, characterised in that the second divider is a counter the end counting value of which is variable by 1. y 0

3. A circuit arrangement as claimed in claim 1, characterised in that the scanner is a D-flip-flop.

4. A circuit arrangement as claimed in claim 1, characterised in that the phase comparator, upon occurrence of a phase deviation in the one direction, delivers a first 15 control signal and, upon the ageuggnaec of a phase deviation in the other direction, delivers a second control signal to a control input of the second divider.

5. A circuit arrangement as claimed in claim 1, occtxeaaMce characterised in that the phase comparator, upon -oocwfranao 20 of a phase deviation in the one direction, delivers a first control signal to a first control input and, upon the occurrence of a phase deviation in the other direction, delivers a second control signal to a second control input of the second divider. - 21

6. A circuit arrangement as claimed in claim 1, characterised in that the phase comparator registers phase deviations within a phase region which corresponds to a basic length (l/ίθ) of the data timing (ίθ), 5

7. A circuit arrangement as claimed in claim 1, characterised in that interposed between the output of the phase comparator and the control input of the second divider is a sequence filter which does not pass on sporadic control signals, but which passes on control signals which occur 10 repeatedly within a predetermined interval of time.

8. A circuit arrangement as claimed in claim 1, substantially as herein described.