IE48117B1 - Memory bank switching - Google Patents

Abstract

A data processing system includes, e.g. four memory blocks (MB0-MB3) each of which stores two different word lengths, e.g. two thousand 18-bit words (EAO) and sixty-two thousand 16-bit words (A). The shorter 16-bit words are instructions with a 9-bit address part (V) which allows any one of a subset (EAO(SO)) of the 18-bit words in the same memory block to be addressed. The resulting accessed 18-bit word is used as an indirect address to any word in any one of the four memory blocks. Thus a processor based on 16- bit words may access a memory which is four times larger than the sixty-four thousand word memory usually regarded as the upper limit in a 16-bit processing system. The remaining subset (EAO(SI)) of 18-bit words not used for indirect addressing can be used for data. As 64K memories with 18 bits are not commercially available it is contemplated that 64K memories of 16-bit words be used with two 64K memories of 1 bit each to make up the 18 bit words.

Description

This invention relates to a data processing system including a computer with a processor and a memory, the memory being divided into blocks of memory locations, at least one of which blocks has memory locations storing instructions including first address information referring to second address information. The processor can address any of the memory locations of that one block, to then obtain second address information with the help of first address information stored in the thus address10 ed memory location and to finally address a memory location in any block with the help of the second address information and of means indicating which of the memory blocks has to he finally addressed.

Such a system is already known, our Patent No.. 1484380 (H. JANSSENS 1). This known system has two memory blocks or banks an indication of which is to be finally addressed with the help of the second address information uses a so-called bank flipflop, whose two conditions indicate the one or the other of the two banks respectively. To set this bank flipflop to its one or its other condition at a suitable moment during the execution of an above mentioned instruction, i.e. in the above-considered case during the so-called indirect cycle thereof, the computer has a pair of auxiliary flip25 flops, a logic circuit and a set of special control instructions. Just before the above mentioned instruction is addressed in memory the computer executes an appropriate one of these control instructions to set these auxiliary flipflops to a suitable condition and during the subsequent execution of the instruction the computer logic circuit resets the bank flipflop to its one or other condition in dependence on the condition of the auxiliary flipflops. Thus the means indicating the memory block to bo finally addressed are relatively complex, and relatively much computer time is consumed to control the bank and auxiliary flipflops.

The article 8086 microcomputer bridges the gap between 8-bit and 16-bit designs by B.J. Katz et al, published in Electronics, Februtry 16, 1978, pp 99-10-1, describes how a memory can be exl.ended by using a segment register which is in fact an extension of the bank flipflop of the above mentioned patent. This enables the address of any memory location to be obtained by adding the address of a segment of the memory comprising a plurality of such segments to the address of the location within this segment. This also needs an additional operation to obtain the address wanted.

An object of the present invention is therefore to provide a data processing system of the type disclosed in the above patent but which does not present the drawbacks thereof.

According to the present invention there is provided a data processing system, including a computer which has a processor and a memory, in which: (a) the memory is divided into blocks of memory locations, at least one of the blocks having memory locations which store instructions each including first address information, which first address information refers to second address information identifying which of the memory blocks is to be addressed; (b) the processor can address any of the memory locations of that one block to obtain therefrom second address information with the help of the first address information obtained as a result of the addressing of the said memory location; (c) the second address information obtained as in (b) is used to address a memory location in any one of the memory blocks; (d) said one block of memory locations includes locations of two different word lengths with the words in the shorter length locations enabling the addressing of memory locations in that one memory block only and the words in the greater length locations enabling the addressing of memory locations in any one of said blocks·; and (e) each of the words in the greater length locations includes the second address information which identifies which of the said memory blocks is to be finally addressed.

Since the second address information is of itself sufficient to 15 address any of the memory blocks, no more computer time is consumed than that needed in a system with a single memory block. To store the second address information only a relatively small amount of extra memory space is required. It should also be pointed out that the present solution permits an easy extension of a computer memory to any number of memory blocks without the instruction set having to be modified. Indeed, as described above the second address information is in fact obtained by a simple indirect addressing procedure which any computer can execute.

In such a data processing system in which at least one of the memory blocks stores the words of two different lengths, the smaller length words Z5 enabling the addressing of memory locations within the one memory block and the words of greater length enabling the addressing of memory locations within any of the other blocks, an advantage is that the existing set of instructions for a computer operating with words of a certain length, e.g, 16 bits, may be retained when extending the memory of this computer beyond the size normally defined by this length. Moreover, it has proved possible to secure 4811? a memory construction which simultaneously caters efficiently for words of the original size as well as for words of a fractionally increased size, e.g. 18 bits, thus affording greater flexibility, e.g. in programming, in addition to the increased memory size.

In one preferred embodiment the data processing system includes a computer with a processor and a memory divided in four memory blocks, each with a storage capacity of 64K words, K being equal to 1024, and which contains 2K words of 18 bits and G2K words of 16 bits.

This enables a computer based on words of 16 bits to use a memory four times larger than 23b = 64 K words, which would'be the maximum capacity with 16-bit words, since Q V 2=2 words out of the 2K 18-bit words may be accessed by 9-bit addresses in 16-bit instruction words. The 3K remaining y words of 18 bits can be used for data in addition to the 62K words of normal 16-bit length.

An embodiment of the invention will now be described in conjunction with the accompanying drawings wherein Fig. 1 is a schematic view of a data processing system embodying the invention; Fig. 2 represents the memory MEM of Fig. 1 in more detail and Fig. 3 shows the evolution of the contents of the register Y of Fig. 1 during the operation of the system of figure 1.

Referring to Fig. 1, the system shown therein includes a computer with a memory MEM and a processor CPU, of which only the arithmetic unit AU and the control unit CU are shown. This system is of the type described in the above mentioned'patent.

The arithmetic unit AU includes an 18-bit memory buffer register M to store a word to be written in or which has been read from a memory location of the memory MEM, an 18-bit memory location register Y to store an address of a memory location of the memory MEM, an 18-bit accumulator register A, and an 18-bit instruction counter P 117 to store the address of an instruction being or to be executed.

The buffer register M and the memory location register Y have access to the memory MEM via the distri5 bution bus DB, which is a gating circuit controlled by the control unit CU via control wires cw. The buffer register M, the location register Y, the accumulator A and the instruction counter P are connected to another gating circuit GC which permits these registers to be interconnected and enables the exchange of information between them, these operations also being controlled by the control unit CU via the control wires cw. The gating circuit GC is for instance of the type disclosed in Patent No. 1367709 (S. KOBUS et al 26-3-2).

The control unit CU includes a 16-bit register F and a logic circuit LC of well-known type for the control of the control wires cw. The input of the register F is connected to an output of the distribution bus DB, and its output is connected to the logic circuit LC, The output formed by the control wires cw of this circuit LC is connected to the distribution bus DB and to the gating circuit GC. The register F is used to store an instruction word read from the memory MEM, whilst the logic circuit LC is for the performance of control functions well known in the computer technique, e.g. from the above mentioned Patent No. 1484380.

Referring to Fig. 2, the memory MEM shown therein comprises four memory blocks MBO to MB3 of which only MBO and MB3 are shown, and which each include 64K mem30 ory locations, K being equal to 1024. The memory block MBO comprises an extended part ΕΛΟ of 2K 18-bit memory locations and a non-extended part NEAO of 62K '16-bit memory locations. The extended part EAO is divided into two k □ 3k sectors EAO (SO) and EAO (SI) of and memory locals tions respectively. The memory locations of EAO (SO) store 18-bit effective operand addresses such as EOA, whilst the memory locations of EAO (SI) store 18-bit data words, data words meaning all types of words except instruction words. The non-extended part NEAO of MBO stores 16-bit instruction words and data words.

The memory block MB3 is similar to MBO and stores similar information words.

Referring to Figs. 1 to 3 the operation of the above system will now be described all the operations being controlled by the control unit CU of the processor CPU and more particular by logic circuit LC of CU.

We assume that the instruction counter ? and the register Y initially store an 18-bit address A(Fig.3) comprising 16 bits 0 to 15 forming a 16-bit partial address U of a memory location in each of the memory η blocks MBO to MB3 because 2 = 64K, and two address bits 16 and 17 indicating one of these memory blocks.

By means of this address A stored in the register Y, the control unit CU addresses the memory MEM and more particularly the memory location ML1 (Fig. 2) with partial address U in the memory block MBO, as the additional bits 16 and 17 of the address A are for instance equal to 00 (Fig. 3).

As a consequence a 16-bit instructioii word represented in Fig. 2 and stored in ML1 is transferred from this location to the buffer register M as well as to the register F. The instruction word is for instance a 16-bit load-in accumulator A instruction comprising: (a) a 9-bit address V stored in bits 0 to 8 of ML1; (b) a 2-bit factor K stored in bits 9 and 10 of ML1. This K factor is assumed to be equal to 10, indicating that the 9-bit address V is an address to be used for indirectly addressing a word in a sector SO (storing 23 = ^-words) of a memory block, i.e EAO (SO) to EA3 (SO) of MBO to MB3; (c) a 5-bit operation code CLDA stored, in bits 11-15 of ML1.

The operation code CLDA and the factor K are analyzed in the logic circuit LC and as a result it is fou5 nd that the instruction is a load-in-accumulator A instruction and that the load operation has to be performed on a word stored in a memory location having-an effective address obtained with the help of the partial address V stored in the instruction. Hence the logic cir10 cuit LC first calculates an indirect address XA by registering the address V of the LDA instruction in bits 0 to 8 of the register Y and setting to zero the bits 9 to 15, of this register Y. The indirect address IA thus finally obtained in the register Y comprises: (a) bits 0 to 8 forming the 9-bit partial address V of a memory location in sector So of each of 9 K the blocks MBO to MB3, because 2 = ; (b) bits 9 to 15 on 0; (c) additional bits 16 and 17 equal to 00 indicat20 ing memory block MBO.

With the indirect address IA thus stored in the register Y the control unit CO addresses the memory MEM and especially the memory location ML2 for the address V in sector EAO (SO) of MBO. Thus an 18-bit-word con25 stituting a so-called effective operand address EOA and which is stored in ML2 is first transferred from MBO to the memory buffer register M and then to the register Y. It comprises (Fig. 3) additional bits 16 and 17 equal to 11 indicating memory block MB3 and a 16-bit partial address W of a memory location within that block MB3.

By means of the address EOA stored in the register Y, the control unit CU addresses the memory MEM and especially memory location ML3 belonging to the extended sector EA3 (SI) of MB3. Hence, an 18-bit data word DW is transferred into the maraory buffer register M for further processing. These operations are however not described because this is not relevant to the invention.

It is clear that the additional bits 16 and 17 of the effective operand address EOA indicate the memory block which has finally to be addressed, so that any of these blocks can be addressed.

Obviously either the extended or the non-extended part of this block can be addressed, so that 16-bit as well as 18-bit data words can be accessed. For instance, when a jump instruction is executed the 18-bit return address, obtained by incrementing the contents of the instruction counter by 1, is stored in the extended area of memory block MBO.

Summarizing, the partial address V contained in an instruction word read from a memory location ML1 of the , memory block MBO enables the memory location ML2 in an extended sector SO of the same memory block MBO to be , { addressed and that this memory location ML2 stores an j extended address EOA enabling any of the memory blocks MBO to MB3 e.g. MB3 to finally obtain 16- or 18-bit data words. ‘ As also described above, and as shown in Fig. 2, i each memory block MB0...MB3 has an extended part EAO to EA3 and a non-extended part NEAO to NEA3. In practice, use of memory blocks having non-extended parts is generally preferred over the use of memory blocks with extended and non-extended parts and for this reason the additional bits of the memory part to be extended are stored in one or more separate memory units.

In the present case it would be desirable to store the 2K x 2 additional bits of a memory part to be extended into a corresponding 2K x 2 bit memory unit. Unfortunately such 2K x 2 bits memory units are not available today, so use is made Of the available 4K x 1 bit memory unit. To be able to simjlfcaneouslv address a row of bits to 15 of a non-extended memory block and the associated additional bits 16 and 17, the additional bits of each set of 2K x 2 bits are stored in corresponding rows (one-bit locations) of two such 4K x 1 memory units.

In general, when one has to extend m rows of an n x p bit memory each of q additional bits, use is made of additional memory units each with at least m rows (locations), corresponding rows of these additional memory units storing together q corresponding additonal bits.

Claims (6)

1. A data processing system, including a computer which has a processor and a memory, in which: (a) the memory is divided into blocks of memory locations, at least one of the blocks having memory locations which store instructions each including first address information, which first address information refers to second address information identifying which of the memory blocks is to be addressed; (b) the processor can address any of the memory locations of that one block to obtain therefrom second address information with the help of the first address information obtained as a result of the addressing of the said memory location; (c) the second address information obtained as in (b) is used to address a memory location in any one of the memory blocks; (d) said one block of memory locations includes locations of two different word lengths with the words in the shorter length locations enabling the addressing of memory locations in that one memory block only and the words in the greater length locations enabling the addressing of memory locations in any one of said blocks; and (e) each of the words in the greater length locations includes the second address information which identifies which of the said memory blocks is to be finally addressed.

2. A system as claimed in Claim 1, and in which the greater length memory locations include a set of such locations which store data which can also be addressed with the help of the second address information.

3. A system as claimed in Claim 1 or 2, and in which said at least one memory block the number of greater length locations does not exceed half of the number of locations in that block.

4. A system as claimed in Claim 1 , 2 or 3, and in which the 5 words in the greater length locations each have £ additional bits as compared with the words in the shorter length locations, so that the additional bits, which form the second address information, can control selection among a maximum of 2 X different memory blocks,

5. A system as claimed in Claim 4, and in which said one memory 10 block consists of a memory matrix for storing words of the shorter length and a plurality £ H word one-bit memories, n being the number of greater length words, for storing the additional bits of the greater length words, so that each greater length memory location consists of a shorter length location plus respective 15 locations in each of the £ word one bit memories.

6. A data processing system substantially as described with reference to the accompanying drawings.