IE47847B1 - Automatic image processor - Google Patents

Description

This invention relates to pattern recognition and analysis devices and more particularly to a class of automatic image processors employing techniques of integral geometry and other mathematical methods to classify patterns in an input silhouette image.

A wide variety of applications exist in which it would be desirable for a machine to automatically recognize, analyze, and/or classify patterns existing in silhouette images (solid black forms against a white background). Some of the simpler problems, which have been implemented with at least limited success by machines, include the recognition of alphanumeric characters and recognition or counting of certain particles, such as blood cells. More ambitious tasks of this class, which appear to be beyond the ability of present technology, would be automatic recognition of military targets from infrared imaging sensors, or the translation of handwriting into a machine usable code.

Elaborate programs have been written, for general purpose computers to perform pattern analysis and classification. The limited success of the general purpose computer to perform pattern analysis and classification is due to the extremely ' ' long‘processing times to process images with very many data points.- A more promising approach may be the use of a special ' purpose processor which implements a mathematical technique applicable to data in the form of images, integral geometry ----- being-such a-technique. One such approach considers the input data as an M by N array of zeroes and ones representing black or white picture elements. From the input array another M by N array is derived wherein each point in the second array is a function of the state of the equivalent point in the initial array and of various neighbouring points in the initial array.

A series of these transforms may be performed to determine some of the characteristics of patterns displayed in the initial array. For example, U.S. Patent 3,241,547 discloses such a special purpose image processor used for counting lymphocytes in blood. Devices employing similar forms of processes for implementing these neighbourhood transforms are disclosed in Pattern Detection and Recognition by Unger, Proceedings of the IRE, 1959, page 737, and Feature Extraction by Goley, Hexagonal Pattern Transformers, Preston, Jr., IEEE Transactions on Computers, Volume C-20, No. 9, September, 1971.

Another class of special purpose machines for implementing a form of integral geometry analysis employing what the author terms hit-or-miss transformations is disclosed in The Texture Analyzer, Journal of Microscopy, Volume 95, Part II, April, 1972, pages 349-356.

These prior art image processors have all operated on images wherein the data points have been reduced to binary form, either zero or one, in with the conventional requirements of integral geometry. For applications of integral geometry in pattern recognition see: 1. G. Matheron, Random Sets and Integral Geometry, Wiley, 1975. 2. Albert B.J. Novikoff, Integral Geometry as a Tool in Pattern Perception, in Principles of Self-Organization, edited by Von Foerstn and Zopf, Pergamon Press, 1962. 3. J. Serra, Stereology and Structuring Elements, Journal of Microscopy, Volume 95, Part 1, February 1972, pages 93-103.

According to the present invention there is provided an automatic image processor for analyzing an image represented by a series of digital electrical data signals having values associated with points in the image, said processor comprising: a chain of substantially identical serial neighbourhood transformation modules, each module having an input and an output, each module output, other than the last module, being connected to the input of a subsequent module in the chain, each module having neighbourhood extraction means for sequentially accessing substantially all of the neighbourhood including a data signal associated with a given point in the image and data signals associated with image points surround15 ing said given point; and analysis logic means for generating a transformation output signal value which is a function of the relationship between transformation criteria values and the values of the data signals in each of the extracted neighbourhoods , said output signal being coupled to the in20 put of a subsequent module in the chain? and central programmable means communicating with each module for selecting the analysis to be performed by each module in the chain by supplying preselected transformation criteria values and transformation output signal values to each module.

The present invention is broadly directed toward an image processor employing an extension of the integral geometry concept wherein the transformations involve matrices in which each point of an image may be assigned a greater number of states than the states that may be assumed by an image point in the original image. For example, if the original digitized image is a silhouette, having image points expressed as binary values, the matrices resulting from transformations of that image may have three or more possible image point states or values. The extension of integral geometry to these multiple state transforms, and the circuits disclosed by the present application for implementing the mathematical techniques, are substantially simpler and/or more powerful than the corresponding techniques and machines of the prior art and result in a substantial advance in the ability to recognize, analyze, and classify silhouette patterns.

As disclosed in the following detailed description of a preferred embodiment of the invention, the image processor takes the form of a serial chain of identical processing stages, each stage consisting in part of multi-bit shift registers and random access memories, implemented by any memory technology such as core, semi-conductor, or magnetic bubble. In the preferred embodiment, each image point is expressed in two binary bits so that it may assume one of four possible states. In alternative embodiments, the range of image point states could be higher. The function of the shift register in each processing stage is to gain sequential access to all possible neighbourhoods in the input image to the stage. To this end it is assumed that the image points are provided to the stage in sequential form, scanned line by line. The shift register contains output ports at suitable locations such that the value of any point and its immediate neighbors may be simultaneously examined. These simultaneously available values form the argument of a logical function which is implemented in the form of a random access memory, a programmable logic array, or a network of logic elements.

As the values of the points represented in the matrix are shifted through the register, each data point and its neighbours are sequentially examined and the logic generates a transformed data point which is a function of the value of the equivalent data point in the input image and the values of the neighbouring data points in the input image. The logical function implemented on these neighbourhood values produces the output of a single processor stage and are fed to the next processor stage in the chain where another transformation is performed.

The nature of the transformation performed by each of the processor stages may be modified under control of a central programming unit which communicates with each image processing stage.

The concept of performing multi-stage integral geometry transformations in a serial network of identical processing stages eliminates the need for a variety of peripheral image storage devices and arithmetic and logical elements normally associated with special purpose image processors. Moreover, the output of each processing stage occurs at the same rate as its input, its speed of operation limited only by the shift register and logic technology employed. Therefore, the serial processor handles data produced by a line scanning sensor at a real time rate, the analyzed image being continuously available at the output of the last processing stage with only a fixed delay proportional to the number of processing stages in the serial string.

The method of processing data represented by the present invention broadly involves the implementation of neighbourhood transforms on a two-dimensional matrix formed of image data points having N possible states to create transformed matrices wherein each image data point is expressed in N + M possible states. For example, if each image data point has two possible values in the input data, the first processing stage may generate a transformed matrix wherein each image data point may have one of three values. Subsequent transforms performed by later processing stages in the chain may increase or decrease the number of states that may be assigned to an image data point. While most of the transforms will increase or decrease the number of permissible states used to express an image data point by one, the method is general enough to encompass transformations which change the number of permissible states by more than one.

As a simple example of an analytic method implementable in the present invention, consider the two-dimensional array of ones and zeroes illustrated in Figure 1, the ones forming a number of open non-intersecting curves of various lengths. Consider the process of selecting those of the curves having a length greater than L, an even integer expressed in units of the minimum spacing between two array points, i.e., the resolution limit of the two-dimensional rhombic array. The first processing stage of a serial string of stages implements a neighbcurhood transformation on the input array wherein all l's having a single immediate neighbouring 1 are converted to 2's, all other image points maintaining their initial states Figure 2). This transform marks the end points of each of the lines. Next, a series of identical transformations are performed wherein each image point of value 1 having a 2 in its immediate neighbour47847 hood is converted into a 2. This transformation is performed L/2-1 times in L/2-1 processing stages following the initial stage of the string. At this point all lines of length less than or equal to L will consist solely of 2's, and the longer lines will have a central portion of l's (Figure 3). Next a series of 1/2 transformations are performed in the next 1/2 processing stages wherein each point which is a 2 and has an immediate neighbouring 1 is converted to a 1. After this series of transformations, lines of length greater than 1 will be represented by l's, and lines of length 1 or less will be represented by 2's (Figure 4). Thus, the lines have been discriminated into two groups according to their lengths and marked by two different image data point values. The analysis is implemented in a string of 1 processing stages. in considering this series of transforms, it should be noted that the transformed image of every stage in the series contains a sufficient amount of information to reconstruct the original input image. Thus, there is no need to store the initial image nor any intermediate image as is required in the prior art image analysis systems; nor is there any need to add or subtract images from one another as required by prior art image analyzers since the same equivalent results may be achieved by the transformations implementable in the present invention. το perform the above analysis on an image processor formed in accordance with the present invention it is simply necessary to program a series string of processing stages of a length equal to the number of neighbourhood transformations in the length discrimination algorithm. The individual stages of the serial processor can be programmed to accomplish a particular neighbourhood transform from a central controller, taking its data from a keyboard or any other suitable information source. Alternatively, a higher level programming language could be divised to program the individual processing stages. For example, implementing the series of transformations described above, the number L could be entered into the central controller from a keyboard. The central controller would then program the appropriate stages in the string at appropriate points rather than the user being required to repeatedly designate the required transformation 1+1 times.

Each processor module performs a similar transformation on its input data stream. First, the central cell of the nine cell neighbourhood is checked to determine whether it has value Kl. Next, a subset N of the eight boundary neighboring cells are checked to determine whether there exists at least one cell of the subset having value K2. If these two conditions are met, then the value of the central cell is changed to K3. Programming a processor module consists of inserting values for N, Kl, K2 and K3 into the proper storage registers in the module.

A preferred embodiment of the image processor formed in accordance with the present invention and representative forms of the processing methods of the present invention are disclosed in the following detailed description. The description makes reference to the accompanying drawings in which: Figures 1-4 are schematic illustrations showing a sequence of transformations utilizing the apparatus of the present invention; Figure 5 is a block diagram of a computer for implementing the transforms of the present invention representing a preferred embodiment of apparatus of the present invention; Figure 6 is a block diagram of a portion of the circuitry of a typical module employed in the system of Figure for sequentially extracting the cell neighbourhoods from an input data stream; Figure 7 is a block diagram of the address decoder and storage register arrangement of one of the modules employed in Figure 5.

Figure 8 is a block diagram of the circuitry employed in the module of Figure 5 for determining the identity between the raighbouring cell values and the contents of the K2 register; Figure 9 is a block diagram of the circuitry in a module of the system of Figure 5 for determining the identity between a central cell and the contents of the K1 register; Figure 10 is a block diagram of circuitry within each of the modules of Figure 5 for determining a position dependent neighbourhood subset.

Figure 11 is an illustration of typical subfields defining the set of positions in the input array which are processed with identical neighbourhood configurations by the modules employed in the system of Figure 5; and Figure 12 is a block diagram of an alternative configuration for the circuitry for comparing the values of each cell neighbour to the contents of the K2 register.

The methods of the present invention may he practiced fay suitably programmed general purpose computers but are of such form as to make possible a class of relatively simple and extremely powerful special purpose computers. As illustrated in Figure 5, a preferred embodiment of the computer of the present invention consists of a plurality of modules 10, which are substantially identical to one another and are connected in serial fashion, with the output of one module providing the input to the next module in the chain. The numher of available modules limits the number of transformations that the computer can perform on a data input in a 478 4 7 η single pass. Since each module is relatively simple and inexpensive, computers having hundreds or thousands of modules are physically realizable and compare favourably in cost to a general purpose computer.

The input data matrix to the first module 10 in the chain is from a data source 12 which may include a storage device, such as a tape 14, or could represent a digitizer operating on a data stream provided by a real time device such as a radar receiver 16.

The output of the final module 10 in the chain is provided to a display or recording device 18 which could take the form of a cathode-ray display or a tape recorder or the like which could later be used to fill a display.

The transformation that is performed by each of the modules 10 is determined by a transformation controller 20. The operation of the controller may be modified by a keyboard 22, or other suitable program source, such as punched cards, tape, etc. The controller 20 connects to each of the modules through an address bus 24 and a transformation bus 26. To modify the transformation formed by a single module, the controller 20 first generates the address of that module on the bus 24 and then generates an appropriate transformation code on the bus 26. Each module 10 contains a stored unique address means for comparing an address provided on the bus 24 with that stored address. When comparison is noted, the transformation code which follows on bus 26 is stored in the module and controls its mode of operation.

All of the circuits within the computer operate on a synchronous basis under control of timing signals generated by a clock 28.

The major logical assemblies of a typical module 10 are detailed in Figures 6-10. Figure 6 illustrates the shift register arrangement for sequentially extracting the nine cell neighborhoods from the input data stream. In this illustration, each cell can take on any one of four possible values, thus two bits of storage per cell are required of all shift register stages If the input data matrix is W elements wide, the shift register must be W-3 stages long.

Each processor module has an address which is determined by its position in the processor module chain. To program a module, the controller simultaneously transmits the address of the module which is to be programmed on the address bus and the values of N, ΚΙ, K2 and K3 on the data bus. The value of N is an eight bit binary number, where a one in the ith bit position indicates that the boundary neighbourhood cell i is to be included in the neighbourhood subset N of the central cell (see Figure 6 for boun15 dary neighbourhood cell numbering). Figure 7 illustrates the address decoder, storage register arrangement.

For each extracted neighbourhood, the two bit value of each neighbour is compared to the contents of the K2 register in a bank of eight comparators (Figure 8). The output of a com20 parator is one if, and only if, the contents of the nei^boudiood cells matches the contents of the K2 register. The output of each comparator is then gated by the appropriate bit on the neighbourhood subset register, or N-register. The output of any gate is one if, and only if, its corresponding neighbourhood position is included in the neighbourhood subset N and the contents of the neighbourhood cell has value X2. A single OR gate examines each AND gate output, its output being a one if, and only if, at least one neighbouring cell in the subset N has a value K2.

The contents of the central cells are compared to the contents of the K1 register in the comparator shown in Figure 9. The output of the comparator is a one if, and only if, the central cell has value Kl. This condition satisfied in conjunction with the previously derived condition on the neighbouring cells causes the output of the multiplexer to be set to K3, otherwise, the output of the multiplexer is equal to the content of the central cell. The output of the multiplexer constitutes the output data stream of a module.

It may not always be desirable to process each cell in an array in exactly the same manner, independent of its position in the array. In general, the subset N of neighbours of a central cell whose.position is i, j in the array can be a function of the central cell position. The manner of determining the position dependent neighbourhood subset is illustrated in Figure 10. The set of all cell positions in the input array which are processed with identical neighbourhood configurations constitutes a subfield. An array may be partitioned into M subfields, where M may be equal to 2, 3, 4 or more. Some useful subfields are illustrated in Figure 11.

For subfield processing, it is convenient to replace the N-register with a more extensive memory element, one holding M eight bit words corresponding to M neighbourhood subsets, one for each of M possible subfields. The output of this neighbourhood memory device is selected by the input to the device which is the subfield label R, where R = 1, 2, . . ., M. The neighbourhood memory device is programmable from the controller via the address and data bus in a manner similar to the scheme illustrated to program the N-register.

The subfield label R is derived from the central cell position i, j in the subfield logical array. The exact nature of the subfield logical array network depends upon the number of subfields and their particular configuration in the data array. Since central cells are examined sequentially, the central cell coordinates can be kept track of by a counter, provided the counter is initially set by the controller corresponding to the position of the processing module in the processing chain.

The neighbourhood processing stage illustrated in Figures 6-10 is sufficiently general so that all useful neighbourhood transformations can be accomplished by one or more processing stages arranged in series. The circuit of Figure 12, however, is useful in that certain types of transformation may be accomplished by a single processing stage rather than a series of processing . stages. The circuit of Figure'12 is identical to the circuit of Figure 8, except that the OR gate has been replaced by a generalized logical function of eight variables, stored in a random access memory. The ram is, of course, programmable from the controller via the address and data buses.

Claims (11)

1. An automatic image processor for analyzing an image represented by a series of digital electrical data signals having values associated with points in the image, said processor comprising; a chain of substantially identical serial neighbourhood transformation modules, each module having an input and an output, each module output, other than the last module, being connected to the input of a subsequent module in the chain, each module having neighbourhood extraction means for sequentially accessing substantially all of the neighbourhood including a data signal associated with a given point in the image and data signals associated with image points surrounding said given point; and analysis logic means for generating a transformation output signal value which is a function of the relationship between transformation criteria values and the values of the data signals in each of the extracted neighbourhoods, said output signal being coupled to the input of a subsequent module in the chain; and central programmable means communicating with each module for selecting the analysis to be performed by each module in the chain by supplying preselected transformation criteria values and transformation output signal values to each module.

2. The image processor of claim 1 which further comprises: first memory means in each module for storing a selected transformation criteria value supplied by the central programmable means, said selected value being used to determine which data signals in the neighbourhood have said selected value.

3. The image processor of claim 2 which further comprises: second memory means in each module for storing selected transformation criteria values associated with particular neighbourhood patterns supplied by the central programmable means, said selected values being used to determine whether the data signals in the neighbourhood having the selected value are configured in said particular pattern.

4. The image processor of claim 3 which further comprises: third memory means in each module for storing transformation output signal values supplied by the central programmable means.

5. The image processor of claim 4 wherein: said analysis logic means is adapted to select a value from the . third memory means as the transformation output signal value for the module when data signals in the neighbourhood having the selected value stored in the first memory means are in a pattern defined by the second memory means.

6. The image processor of claim 5 wherein the image is represented by data signals having binary values of zero and one, and wherein the transformation output signal value from at least one of the modules provided by the third memory means therein has a greater number of values.

7. The image processor of claim 5 which further comprises: fourth memory means for storing a given transformation criteria value supplied by the central programmable means which is used to determine whether the data signal associated with the given point in the neighbourhood has said given value.

8. The image processor of claim 7 wherein the analysis logic means is adapted to select the value of the data signal associated with the given point as the transformation output signal value of the module when the surrounding data signals in the neighbourhood having the selected value are not in a pattern defined by the second 5 memory means.

9. The image processor of claim 1 wherein each neighbourhood consists of data signals representing an Ν x M array points, and wherein said neighbourhood extraction means in each module includes Ν x M storage devices for 10. Temporarily storing the data signals associated with each neighbourhood.

10. The image processor of claim 9 wherein said series of data signals are shifted through the storage devices to sequentially access the neighbourhoods.

11. 15 11. An image processor for analyzing images substantially as hereinbefore described with reference to the accompanying drawings.