DK149240B - Automatic image processing unit - Google Patents

Description

o 149240 i

This invention relates to an apparatus of the kind set forth in the preamble of claim 1, and in particular to an apparatus for digital analysis of image or sign patterns reproduced as a matrix of digital signals produced by serial scanning of image points with an automatic image processing using a mathematical method by which the pattern of a silhouette image can be classified.

Many applications are known in which it will be desirable to have a machine for automatically recognizing, analyzing and / or classifying patterns in the form of silhouette images, ie. black drawings on white background. Some of the simpler tasks that have at least partially been solved by such machines are recognition of alphanumeric characters and recognition of 15 or counting of certain particles, such as blood cells. More ambitious targets of this kind, however, which are beyond the scope of the prior art, are automatic recognition of military targets with infrared image sensors or a conversion of handwriting into a code that can be read by a machine.

Calculators of the generally applicable type have already developed large complicated programs for pattern analysis and classification. However, it has been found that the generally usable calculator has only had a limited success in performing pattern analysis and classification due to the extremely long processing time of processing data for a large number of images. One promising method seems to be the use of a special data processing equipment which realizes a mathematical technique that can be applied to data available in the form of images. This technique can be integral geometry. In such a method, described in U.S. Patent 4,060,713, the data entered is considered as a matrix of zeros and ones corresponding to 35 black or white pixels. From the loaded matrix, a second matrix is derived, where each point in the second matrix is a function of the state of the equivalent point in the first matrix and the state of some neighboring points to the equivalent point in the first matrix. A series of such transformations can be performed to determine some characteristic properties of the patterns in the original matrix.

For example, U.S. Patent No. 3,241,547 discloses such a special image processing unit that can be used to count blood lymphocytes. Apparatus employing similar methods to realize such neighbor transformations are described in "Pattern Detection and Recognition" by Unger, 10 Proceedings of the IRE, 1959, page 737, and "Feature Extraction by Golay Hexagonal Pattern Transformers", Preston,

Jr., IEEE Transactions on Computers, Volume C-20, No. 9, September 1971.

Another type of special equipment utilizing integral-geometry analysis utilizing so-called "hit-or-miss transformations" is described in "The Texture Analyzer," Journal of Microscopy, Volume 95, Part Two, April 1972, pages 349- 356th

The previously known image analysis systems have all worked with images in such a way that data for the individual pixels has been reduced to binary form, ie. either 0 or 1, as is a common requirement in integral geometry. For applications of integral geometry for pattern recognition 25, see: 1. G. Matheron, "Random Sets and Integral Geometry", Wiley, 1975.

30 2. Albert B.J. Novikoff, "Integral Geometry as a Tool in

Pattern Perception ", in Principles of Self-Organization, published by Von Foerstn and Zopf, Pergamon Press, 1962.

3. J. Serra, "Stereology and Structuring Elements," Journal 35 of Microscopy, Volume 95, Part One, February 1972, pages ne 93-103.

3 149240

ISLAND

The object of the invention is to provide an image analysis equipment of the kind described in US Patent No. 4,060,713 and which does not require a special calculator and which has a very simple structure.

5

This is achieved with a device of the kind specified in the preamble, which equipment has the features specified in the characterizing part of claim 1.

10 For example, if the original digital image. is a silhouette of pixels that can be expressed as binary values, the matrices obtained by modifying the original image may have three or more possible pixel states or values. The selection of the integral geometry and these multi-state transformations and the circuits shown with the present realization of the mathematical technique are substantially simpler and / or more efficient than the previously used technique and equipment and offer significant advances in recognition, analysis and classification. of silhouette patterns.

20

As shown in the following detailed description of a preferred embodiment of the invention, the image analysis equipment consists of a chain of identical data processing units, each unit comprising a multi-bit switch register 25 and direct access memory storage, ie. so-called RAM bearings, which can be built using appropriate techniques, such as core bearings, semiconductor bearings or magnetic bubble memory. In the preferred embodiment, each pixel is expressed in two binary bits so that it can assume one of four possible states.

In alternative embodiments, the range of pixel modes may be larger. The shift register in each data processing unit must, in order, give access to all possible neighboring points in the sub-image loaded in the processing unit. For this purpose, it is assumed that pixel data is fed into the

OC

the sequencer in sequence as the image is scanned line by line. The switch register contains output ports at appropriate locations so that the value of a pixel and its neighboring points can be examined simultaneously. These simultaneously available values form the argument in a logical function, which is constructed as a direct access memory (RAM) memory, a programmable logic circuit arrangement, a so-called array, or a network of logical elements.

When the values of the pixels in the matrix are displaced through the register, data for each pixel and its neighbor points are sequentially examined, and the logic produces a transit-shaped data point which is a function of the values of the equivalent data point and its neighbor points in the loaded image. The logical function that depends on these neighbor values produces the output of a single data processing unit and this output is applied to the next data processing unit in the chain. In this next data processing unit, a further transformation is performed.

The nature of the transformation performed by each data processing unit can be modified from a central programmable controller which is associated with each data processing unit.

The performance of multistage integral-geometry transformations in a series of identical data processing units eliminates the need for several different external image storage units and arithmetic and logic elements usually associated with specialized image analysis equipment. Furthermore, the output data of each processing unit occurs at the same frequency as its input data, the data processing rate being limited only by the shift register and the logic technology used. Therefore, the serial data processing equipment processes data generated by a line scanner sensor real-time, so that the analyzed image is constantly available at the output of the last data processing unit only with a fixed delay 35.

proportional to the number of serial connected data processing units.

0 149240 5

The data processing method represented by the present invention employs the realization of neighboring transformations on a two-dimensional matrix consisting of image data points with "N" possible states for the purpose of creating transformed matrices, each image data point being expressed by N + M

possible states. If the data entered for each pixel can assume two possible values, the first data processing unit can generate a transformed matrix, where each pixel can have one of three possible values. The following transit formations performed by the next data processing units in the chain can either increase or decrease the number of states to which data can be assigned to a pixel. Although most of the transformations will increase or decrease the number of allowed states by one, the method is sufficiently general to include transformations which change the number of allowed states by more than one.

As an example of an analytical method that can be used in the present invention, one can consider the two-dimensional arrangement of zeros and zeros shown in FIG. 1, wherein the singles form a number of open, non-intersecting curves of different lengths. In the following, the task is considered to select the curves having a length greater than L, where L is an even integer expressed in units equal to the minimum distance between 25 two points, ie. the solubility of the two-dimensional rhombic array. The first data processing unit in a chain of units performs neighbor transformation on the loaded matrix, converting all ones with only one neighbor number to a total. All other pixels retain their original state, see FIG. 2. This transformation marks the endpoints of each of the lines. Next, a series of identical transformations are performed in which each pixel with the value one and with a total, as neighbor, is converted to a total. This transformation is performed L / 2-1 times in L / 2-1 data processing units in series with the first unit. Thereafter, all lines of length less than or equal to L will consist solely of totals, and the longer lines will have a center portion of 0, see FIG. 3. Next, L / 2 transformations are performed in the next L / 2 data processing units, whereby each point, which is a total and currently has one to neighbor, is converted to one. Following this series of transformations, lines whose length is greater than L will consist of singles, and lines whose length is equal to or less than L will consist of totals, see FIG. 4. The lines have thus been divided into two groups according to their length and marked with two different pixel data values. The analysis is carried out in a chain of L data processing units.

Considering this chain of transformations, it should be noted that the transformed image at each stage of the chain contains a sufficient amount of information to reconstruct the initially loaded image. Thus, there is no need to store the original image or any other temporary image, as is necessary in the prior art image analyzers. Also, there is no need to add or subtract images apart, as has also been necessary in the prior art image analyzers, since the same or equivalent results can be obtained from the transformations proposed according to the present invention. 1 2 3 4 5 6 7 8 9 10 11

If the above analysis is to be performed on an image data processing 2 system according to the invention, it is only necessary to program 3 a chain of data processing units having a length corresponding to 4 the number of neighbor transformations in the length discriminating 5 algorithm. The individual steps in the chain of data processing units 6 can be programmed to perform a special neighbor transformation 7 of a central controller receiving data from a keyboard 8 or other appropriate source of information. Alternatively, 9 a high-level programming language could be used to program 10 of the individual data processing units. In performing an 11 series of transformations, as described above, the number L could be entered into the central controller from a keyboard. The central controller could then program the relevant steps in the chain at appropriate points instead of the user having to designate the necessary transformation L + 1 times.

5 Each data processing unit performs a similar transformation of the loaded data stream. First, the central cell in the nickeled area is examined to determine if it has the value Kl. Next, a subset N consisting of the eight neighboring neighboring cells is examined to determine if among them 10 there is at least one cell of the subset having the value K2. If these two conditions are met, the value of the central cell changes to the new value K3. Thus, programming a data processing unit consists of entering the values to be assigned to N, K1, K2 and K3 in the appropriate memory stores 15 in the unit.

BRIEF DESCRIPTION OF THE DRAWINGS The invention will be explained in more detail below with reference to the drawing, in which: FIGS. 5 is a block diagram of a calculator for realizing the transformations in a preferred embodiment of the apparatus according to the invention; 6 is a block diagram of a portion of a data processing unit of a typical module of FIG. 5, 30 FIG. 7 is a block diagram of an address decoder and a storage register arrangement for one of the modules of FIG. 5, FIG. 8 is a block diagram of a circuit of the module of FIG. 5 to determine identity between the values of. neighbor cells and the contents of register K2, 149240 and 8 fig. 9 is a block diagram of a circuit in a module of the system of FIG. 5 for determining identity between a central cell and the contents of the register K1; 10 is a block diagram of a circuit in each of the modules of FIG. 5 to determine a position depending on the neighboring quantity; FIG. 11 shows an example of typical subfields defining 10 a set of positions in the input matrix which are processed with identical enumeration configurations of the modules used in the system of FIG. 5, and FIG. 12 is a block diagram of an alternative embodiment of the circuit designed to compare the values of each neighboring cell with the contents of register K2.

The methods used in the present invention can be realized in connection with generally usable computers, but are of such a nature that it is possible to realize with a class of relatively simple, and highly effective special calculators. As shown in FIG. 5, a preferred embodiment of the calculator according to the invention consists of a number of modules 10 which are substantially identical to each other and which are connected in series so that the output of one module is connected to the input of the next module in the chain. The number of modules limits the number of transformations the calculator can make on loaded data at a single throughput. Since each module is relatively simple and inexpensive, calculators with hundreds or thousands of modules can be physically realized and can compete in price with a calculator usable for all purposes.

A matrix of data to be loaded into the first module 35 10 in the chain comes from a data source 12. The data source 12 may contain a memory such as a tape 14, or may represent a digitizer processing a data stream from a data source. real-time equipment such as a radar receiver 16.

The output of the last module 10 in the chain is fed to a data monitor or recording equipment 18, such as a cathode ray tube or tape recorder or the like, which may later be used in connection with a data monitor.

The transformation performed by each of the modules 10, 10 is determined by a transformation controller 20. The operation of the controller can be modified by a keyboard 22 or from other appropriate program sources such as a hole card, tape, etc. The controller 20 connects to each of the modules through a address bus 24 and a transformation bus 26. When the transformation performed by a single module is to be modified, the controller 20 first sends the address of that module out on the bus 24 and then an appropriate transformation code on the bus 26. Each module 10 contains a stored unique address system for comparing an address from the bus 20 24 with the stored address. When the comparison is made, the transformation code, which follows on bus 26, is stored in the module, and then controls its operation.

All the circuits in the calculator are synchronized by time signals 25 generated by a clock or clock generator '28.

The main logical units of a typical module 10 are shown in detail in FIG. 6-10. FIG. 6 shows the shift register arrangement to sequentially separate the nine neighbor cells in the stream of loaded data. In this example, each cell can assume one of four possible values, i. two bits in storage per cell are required for all switch register steps. If the input data matrix is W elements wide, the shift register must fill the W-3 steps in length.

Each module has an address which is determined by its position in the module chain. To program a module, the controller sends the address of the module to be programmed on the address bus, while sending the values N, K1, K2 and K3. The value of N is an eight-bit binary number, where one in the 1st bit position indicates that the adjacent 5th cell must be included in the neighboring or surrounding subset N of the central cell (see Fig. 6 for the numbering of neighboring neighboring cells). . FIG. 7 shows the address decoder and storage registers.

10 For each neighboring neighbor separated region, the value of the two bits for each neighbor is compared to the contents of register K2 in a group of eight comparators (Fig. 8). The output of a comparator is one if, and only if, the contents of the neighbor cell match the contents of the register K2. The output 15 of each comparator is then fed into an AND gate along with the corresponding bits in the neighbor subset register, ie. N-register. The output of one of the AND gates is one if, and only if, its corresponding neighbor position is contained in the neighbor subset N and the contents of the neighbor cell have a value of 20 K2. A single OR gate examines the output of each AND gate so that its output is one if, and only if, at least one neighbor cell in the subset N has the value K2.

The contents of the central cells are compared with the contents 25 of the register K1 in the comparator shown in FIG. 9. The output of the comparator is one if, and only if, the central cell has the value Kl. When this condition is met at the same time as the previously derived condition of the neighboring cells, the output of the multiplexer will be set equal to K3, otherwise the output 30 of the multiplexer will be equal to the content of the central cell. The output of the multiplexer generates the flow of output data from a module.

It is not always advantageous to process each cell in a matrix in exactly the same way, regardless of its position in the matrix. The subset N of neighbors to a central cell whose position is i, j in the row may be a function of the position of the central cell. The manner in which to determine the position-dependent neighboring quantity is shown in FIG.

10. The amount of all cell positions in the input matrix processed with identical neighboring configurations forms a subfield. An array can be divided into M subfields, where M can be 2, 3, 4 or more. Some useful subfields are shown in FIG. 11th

For processing a subfield, it is convenient to replace the 10 N register with a larger extension memory element, e.g. one containing M eight bit words corresponding to M neighboring subsets, one for each of M possible subsets. Output from this memory device is selected by N data for the device ie. the subfield label R, where R = 1, 2, -, M. The neighbor-18 memory unit can be programmed from the controller over the address and data bus in a manner similar to the programming of the N register.

The sub-field label R can be derived from the central cell position 20 i, j in the logical matrix of the sub-field. The exact design of the sub matrix logical matrix network depends on the number of sub fields and their particular configuration in the data matrix.

Since central cells are examined sequentially, the central cell coordinates can be traced by a counter, provided the counter is initially set from the controller corresponding to the position of the module in the processed chain.

The neighboring step shown in FIG. 6-10 is so general that all usable neighbor transformations can be performed by a series coupling of such steps. The circuit of FIG. 12 is peculiar in that certain types of transformations can be performed by a single machining step instead of a series of machining steps. The circuit of FIG. 12 is identical to the circuit of FIG. 8, except that the OR gate is replaced by a common logic function with eight variables stored in a RAM (available memory). This RAM can of course be programmed from the controller through the address and data buses.

Claims (2)

149240 O Patent Claims. Apparatus for digital analysis of image or character patterns represented by a matrix of digital data signals obtained by a serial scan of pixels and emitted from a data source (12) and having several possible values, the value of each data signal is a function of a corresponding pixel, and with a chain of successively coupled data processing units (10) to selectively provide a new value for each data signal as a function of the data values of the surrounding points in the image and each data processing unit (10) ) comprises an arrangement of 15 'digital storage means (la, lb-9a, 9b) for temporarily storing a sub-section of the image, comprising a central data signal (9a, 9b) corresponding to a given central pixel, and neighboring data signals (la, lb-8a, 8b) corresponding to neighboring pixels surrounding the central point and having 20 means for sequentially sequencing all the different data signals for the image in the digital storage means for analysis, characterized in that all data processing units (10) are identical and contain individually programmable analysis circuits (fig. 8 and 9), 25 communicating with a central programmable controller (20) which selectively provides analysis criteria for each data processing unit so that each data processing unit is able to selectively generate and transmit a new value (K3) for each data signal in the image to the input of the next 30 data processing unit, depending on the criteria (K1, K2) supplied by the central controller (20). Apparatus according to claim 1, characterized in that the output of each data processing unit (10) has a greater number of allowed states than the pixels to be analyzed have.