IE42022B1 - Phase locked oscillators - Google Patents

Abstract

1521971 Automatic frequency control STANDARD TELEPHONES & CABLES Ltd 21 Oct 1975 [29 Oct 1974] 46744/74 Heading H3A An oscillator arrangement, e.g. clock oscillators in a telephone exchange, includes: an array of oscillators, e.g. crystal oscillators 01, 02, 03 all tuned to the same predetermined frequency; meand PC1,A1 PC2,A2 PC3,A3 for phase locking each oscillator to the next, the last oscillator being locked to the first; detection means Q1, Q2, Q3, one associated with each oscillator, for detecting an out of lock condition between pairs of oscillators; and means, e.g. AND gates G1, G2, G3 for identifying a malfunctioning oscillator and preventing it from changing the frequencies of the other oscillators. If for example oscillator 02 goes too far off frequency, then a large correction signal is produced from phase comparators PC2, PC3. This large signal is detected by detectors Q2, Q3 which then produce an output signal from AND gate G3 to cause oscillator 03 to adopt a frequency near the centre of its range, regardless of the signal from phase comparator PC3.

Description

Thia invention relates to phase locked oscillators, and in particular to an arrangement of oscillators in which the frequency of each oscillator is phase locked to that of the next oscillator; Clock oscillators, particularly for use in electronics telephone exchanges, must have a high degree of accuracy and reliability. Accuracy can be achieved by using an arrangement in which two or more oscillators are tuned to the same frequency and phase-locked together.

Such an arrangement, however, may suffer from the disadvantage that failure of any one oscillator can cause malfunction of the oscillators of the arrangement.

The object of the invention is to minimise or to overcome this disadvantage.

According to the invention there is provided an oscillator arrangement, including an array of oscillators all tuned to the same predetermined frequency, means for phase locking said oscillators one to the next, the last oscillator of the array being phase-locked to the first 2Ό oscillator, detection means, one associated with each pair of phase-locked oscillators, for detecting an out.of lock condition between the pairs of oscillators, arid means for identifying a malfunctioning oscillator and substantially preventing it from changing the frequency of the other oscillators of the array.

According to the invention there is further provided an oscillator arrangement, including first, second and third oscillators, said oscillators being phase-locked one to the next, first, second and third phase comparators for determining the phase relationships of the oscillator -2- . 80S 2 circuits, first, second and third detector circuits, and first, second and third AND-gates to which the outputs of the detector circuits are fed, in which phase drift of any one oscillator causes two corresponding phase comparator circuits to generate a correction voltage, and in which 'when excessive phase drift of any one oscillator causes the two corresponding comparator circuits to trigger the detector circuits, the corresDond· ing AND-gate is enabled, the output of that AND-gate holding the oscillator following the one oscillator at the centre of its frequency range.

An embodiment of the invention will now be described with reference to the accompanying drawing which shows a clock oscillator arrangement in which three oscillators are phase locked together. The drawing shows an arrangement of three oscillators, although in some applications the arrangement may be extended by the addition of further oscillators together with their accompanying circuitry.

The arrangement includes three oscillators, 01, and 03 which may advantageously be of the quartz crystal controlled type. The output of each oscillator is fed to two of three phase comparator circuits, PCI, PC2 and PC3 as shown in the drawing such that each comparator circuit receives the outputs of two adjacent oscillators. A phase drift of any one oscillator causes the corresponding phase comparator circuits to generate D.C. voltages which are amplified by D.C. amplifiers, Al, A2, A3, one connected to each comparator circuit output. The amplified voltages are then fed back to the oscillators thus applying correction voltages which alter the frequencies so as to reduce the phase differences. - 3 In this way each oscillator acts as a master oscillator controlling the frequency of the next oscillator, but no one oscillator operates independently of the others.

Detection circuits Ql, Q2 and QJ which measure 5 the output voltages of the phase comparator circuits after amplification, respond to a severe malfunction of any one oscillator, phase comparator or amplifier. If severe frequency or phase drift of an oscillator occurs the output voltages of the corresponding phase comparator circuits will rise to the point at which triggering of the detector circuits, which are arranged to respond at a predetermined voltage'threshold, will occur. This threshold should be adjustedtp below the point at which the amplifier output is no longer proportional to the phase difference.

The outputs of the three detector circuits are fed to an arrsy of' three AND gates Gl, G2 and GJ which, in response to malfunction signals from the alarm circuits, identify the malfunctioning oscillator and apply a signal to the appropriate line Ll, L2 or L3 to cause the first functioning oscillator past the fiult to adopt a frequency · near the centre of its range regardless of the inputs of its phase comparator. The following oscillator remains phase-locked to this one thus maintaining the correct output signal from at least two oscillators.

The operation of the detector circuits Ql, Q2 and QJ cah easily be tested by breaking each corresponding feed-back loop in turn without causing any one oscillator to become unlocked.

The clock oscillator arrangement described herein is suitable for use as, but not limited to, a clock generator for an automatic telephone exchange.

Claims (6)

1. An oscillator arrangement, including an array of oscillators all tuned to the same predetermined frequency, means for phase locking said oscillators one to the next, 5 the last oscillator of the array being phase locked to the first oscillator, detection means, one associated with each pair of phase-locked oscillators, for detecting an out of lock condition between the pairs of oscillators, and means for identifying a malfunctioning oscillator and substantially 10 preventing it from changing the frequency of the other oscillators of the array.

2. An oscillator arrangement, including first, second and third oscillators, said oscillators being phase-locked oneto the next, first, second and third phase comparators for Is determining the phase relationships of the oscillator circuits, first, second and third detector circuits, and first, second and third AND-gates to which the outputs of the detector circuits are fed, in which phase drift of any one oscillator causes two corresponding phase comparator circuits /0 to generate a correction voltage, and in which when excessive phase drift of any one oscillator causes the two corresponding comparator circuits to trigger the detector circuits, the corresponding AND-gate is enabled, the output of that AND-’jate holding the oscillator following the one oscillator at the centre of its frequency range. 2o

3. · An oscillator arrangement as claimed in claim 1 or 2, and in which each said oscillator is frequency controlled by a quartz crystal. An oscillator arrangement substantially as

4. »««* described herein with reference to the accompanying drawing.

5. A method of phase-locking an array of oscillators substantially as described herein with reference to the accompanying drawing.

6. A telephone exchange when fitted with one or more oscillators as claimed in any one of claims 1-4.