HU193837B - Computer for combined processing words and bits - Google Patents

Abstract

This computer system for combined word and bit processing has a word processor with associated word program memory, a bit processor with associated bit program memory, a core image storage, connections for digital and binary input and output channels, an address bus, a data bus and a control bus, with a bus isolating switch. The objective is to make optimum usage of the available storage capacity of the program memories. This means that the word and bit processing should take place simultaneously, together with program corrections for both program memories, from a single connection point for a programming device. For this purpose, the word program memory, the bit program memory and the image memory on the address bus, data bus and control bus of the word processor with its word program memory form a first grouping, and the bit processor, the bit program memory and the core image storage form a second grouping. The connections for digital and binary input and output channels are attached directly to the word and bit processors, where a start control line is connected from the word processor to the bit processor and a stop control line is connected from the bit processor to the bus isolating switch and the word processor.

Description

BACKGROUND OF THE INVENTION The present invention relates to a computer for combined word and bit processing having a word processor associated with a word library, a bit processor associated with a bit library, a mapping library, connection points for digital and binary inputs and inputs, an address, data and control bus is equipped,

It is known to use central data processing units as programmable controllers which process each bit with a bit processor and word processing with a word processor. During the processing of each bit, the logical variables, which indicate the logic state of encoders, for example on a machine tool, are logically connected to each other. Word processing processes data carrying multiple bits of information and performs special tasks such as arithmetic operations, data exchange with parent computers, connection of peripherals, etc.

The programmable controls are a central one ^; in the past, it had only bit processing and, in accordance with its purpose, had a control circuit designed with discrete circuitry, which executed the control program at high speed. With the spread of integrated microprocessors, they have also been used as programmable controllers as guides, and bit processing has been carried out with a properly interpreted breakdown of the control program. However, the advantage of being able to perform word processing (for example, arithmetic operations, calculation programs) had the disadvantage of having high program runtime (cycle time) and the fact that bit processing required very high storage capacity. To overcome these drawbacks and to take advantage of the advantages of word processing, a single control unit was combined with a bit processor and a word processor.

For example, DE-OS 31 01 270 discloses a word and bit processing switching arrangement having a program library containing word and bit processing instructions. In the case of a bit instruction, the bit processor is activated and at the same time data processing in the word processor stops. In the meantime, however, the word processor continues to address the container and retrieve the command, meaning that the bit processor does not have its own access to the library. The disadvantage of this switching arrangement is that the bit processor and the word processor cannot operate at the same time and consequently the processing speed is not high enough. This solution is based on the idea that essentially word processing is required, whereas the bit processor is only exceptionally engaged for bit processing.

DE-PS 25 22 343 discloses an additional circuit arrangement having a word processor and a bit processor. The instructions for the word processor and the bit processor are also stored in a common library in this solution.

This apparatus is provided with a coordinating unit which connects the libraries to the bit processor for a bit instruction and a word processor for the word processor. A signaling circuit establishes a connection between the bit processor and the word processor. This signaling circuit is tapped by the bit processor and scanned by the word processor, which then calls the corresponding subprogram. The disadvantage of this switching arrangement is that the word processor has no direct access to the mapping pair and the binary process and output channels, thus limiting the flexibility of the programmed control. In addition, a disadvantage is that the coordinating unit is a relatively costly unit that has to decode incoming instructions constantly in order to distinguish between the instructions for the word processor and the instructions for the bit processor and to assign the library accordingly.

It also describes a control device with a word and bit processor in Technica, 1983-19, pp. 1555-1558. In this solution, the storage for the word instructions and the bit instructions are strictly separated from each other. Although this solution allows simultaneous word and bit processing, the strong separation between word and bit libraries prevents the use of flexible storage capacity. In applications where many word processing is required (for example, when many subprograms need to be processed), it is not possible to use parts of the bit program library for word instructions. In addition, the switching unit for interconnecting buses with different structures of word and bit processing subunits is quite complex and requires an additional signaling circuit for the exchange of information between the word and bit processors.

A further disadvantage of this solution is that the programming device can only be connected to it at specific connection points designed for this purpose. Such a programming device may be required to make changes to the library, especially during commissioning.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a computer capable of combined word and bit processing that operates flexibly and thus quickly with minimal storage capacity,

-2193837 to make optimum use of the existing storage capacity of the library.

A further requirement is to be able to connect to a programming device which can be accessed without any modification of the connection points.

The object of the present invention is to provide a computer for combined word and bit processing, which simultaneously enables the word processor to execute the word instructions and the bit instructions by the bit processor while providing the bit program storage space for the word instruction. In addition, an on-line interface must be provided to enable programming device-connected program changes and display functions to be implemented in both word and bit libraries.

The object of the present invention has been solved by attaching a word library, a bit library and a mapping library to the address, data and control buses of the word processor. A bus separator unit is included in the address, data and control bus, which divides the word processor into associated first and second groups with the associated word library and the associated bit library and mapping library, and the digital and binary input channels directly connected to a word processor or a bit processor. The word processor connects the word processor to the bit processor and the bit processor to the bus separator and the word processor via a STOP wire.

Preferably, the bit processor is provided with a storage element having a write input with a comparator recognizing the coding of the VEGE instruction, an eraser input connected to a START wire from the word processor, and an output of the storage element as a STOP line to the bus separator join.

The contents of each deleted storage partition of the bit library preferably contain the code of the END instruction.

In a further preferred embodiment of the invention there is provided a second mapping memory which is associated with the first group in the address, data and control bus.

In the first embodiment, the digital and binary input and output channels are connected to the word processor, while in the second embodiment, the digital input and output channels are connected to the word processor and the binary input and output channels are connected to the bit processor.

The invention will now be described in more detail with reference to the exemplary embodiments shown in the accompanying drawings. The drawing shows:

Figure 1 is a circuit diagram of a computer according to the invention, a

Figure 2 is a block diagram illustrating the bus separation unit of the bus lines of the computer of Figure 1,

FIG. 3 is a circuit arrangement providing control signals for the bus separation unit of FIG. 2.

As shown in Figure 1, the word processor of the present invention, WP, is connected to, for example, a microprocessor bus 1 formed on a single semiconductor chip. The I bus consists of 8-bit data lines, 16-bit address lines and control lines.

Bus 1 is connected by a WSP word library and mapping AB2. A bus separator 2 is connected to the bus 1, and a bit processor BP, a bit program library BSP and an mapping storage AB1 are connected. BP bit processor over 1 bit data bus with mapping AB1 and over 8 bit data bus and address bus to BSP bit library! is related. In addition, the word processor WP has connection points for digital input and output units 3 (e.g., a serial interface for connecting a higher-level system or programming device) and binary input and output units 4 (e.g., outputs and outputs of a machine to be controlled). However, the binary input and output unit 4 can also be connected to the BP bit processor as indicated by the dotted line in FIG. The START bit is connected from the WP word processor to the BP bit processor, while the BP bit processor is connected to the bus separator 2 and the WP word processor to a STOP wire.

The block diagram of Fig. 2 shows the structure of the 2-bus separator unit, which in effect represents five TRI-TR5 separators, which are circuits with three-state outputs.

The TRI-TR5 separates between a first group WP word processor WSP word library and mapping AB2 and a second group BP bit processor BSP bit library and mapping AB1 encapsulated in bus 1, which is on an ADR address bus, a DAT data bus and STL is divided into control wires.

The address bus ADR is connected to the BSP bit library on the TRI separator, and to the mapping memory AB1 via the separator TR2.

The separator TR3 is encapsulated in the data lines of the mapping memory AB1. The separator TR5 includes: a STAB1 control line for calling mapping AB1, a STBSP control line for calling a BSP bit library, and a STWR control line for writing / reading a BSP bit library and mapping AB1.

The design of dividers TR3 and TR4 is bidirectional as opposed to dividers TR1, TR2 and TR5, which only operate in one direction.

The auxiliary circuit included in the BP bit processor for generating the STOP stop signal (FIG. 3) includes: 5 storage elements, in this case a Flip-Flop, with S write input 6

Connects to the -3193837 similar output. The comparator input 6 is connected to the data lines of the BP bit processor. The wiper input R of the storage element 5 is connected to the START wire from the word processor WP. The inverting Q output of the storage element 5 is a STOP line to the bus separator 2 and is output from the bit processor BP to the interrupt input of the word processor WP.

Within the BP bit processor, the STOP line is connected to an internal START / STOP controller 7 to which the non-inverting Q output of the storage element 5 is connected.

The circuit arrangement according to the invention, in which the binary input and output channels are connected to the WP word processor, operates as follows:

The bus separator 2 allows the WP word processor to be uncoupled from the mapping memory AB1 and the BSP bit library, or it allows the WP word processor to access both the mapping AB1 and the BSP bit library when switching bus lines. .

By switching the three-state output circuits used in the bus separation unit 2 to a high resistance state, the separation function can be easily accomplished.

Each control cycle always starts with an I / O routine, that is, the logical state of the inputs to the process is mapped in mapping AB1, and the outputs activated during the last pass of the BSP bit library are output to the mapping AB1. During this input / output phase, the BP bit processor is in a stopped state, i.e. its operation is interrupted, the bus separator 2 is inactive, and the WP word processor has access to all storage. At the same time, it implements the input / output routine through the binary I / O units. In this way, the input / output routine is executed under the influence of program control, and the execution can be flexibly adapted, for example, to the input / output speed required by the process being controlled. After completion of the I / O routine, the WP word processor provides the BP bit processor with a START control signal which causes the BP bit processor to activate bus separator 2 and execute the program stored in the BSP bit library to update the outputs of the mapping storage AB1. . During this time, when the BP bit processor executes the BSP bit library program, the WP word processor runs the WSP word library program (e.g., arithmetic operations, time counting routines), or data through the digital input / output unit 3. complex with an additional calculator. When the BP bit processor has reached the last bit processing program instruction (END statement), it stops (STOP state), after which the 2-bus separator unit becomes inactive. This STOP state is reported by the STOP line to the WP word processor at the interrupt input. The WP word processor can then interrupt its current program and complete the input / output routine.

The storage element 5 in the BP bit processor (Fig. 3) implements the START / STOP operating state, including control of the bus separator 2. The comparator 6 recognizes the code of the END command and activates the input S of the storage element 5. From the entry of the storage element 5 (the BP bit processor in STOP state) to the deletion of the storage element 5 (the BP bit processor starts), the WP word processor has access to the total storage capacity. As a result, during this period, you can execute instructions that are in the BSP bit library. This makes sense if the BSP bit library is not utilized because there are few bit processing instructions and these storage bays are not allocated. The free storage space in the BSP bit library can be reserved by word instructions that are accessed and executed by the WP word processor in the STOP state of the BP bit processor. A further advantage of STOP storage access is the ability to enter various program adjustments and the ability of the WP word processor to utilize the storage capacity of the BSP bit library and mapping AB1.

A programming device can be connected to the storage locations of the BP bit processor and the WP word processor, for example, via a serial interface of the WP word processor.

The instruction code of the BSP bit library END is preferably stored in each of the erased storage compartments of the BSP bit library. In the embodiment shown, this content is FF by hexadecimal encoding. This solution enables the BP bit processor to interact with the WP word processor even without a loaded bit program, since the BP bit processor recognizes an END when decoding the first called word of the BSP bit library, which causes the bus separator 2 to be TRI-TR5 separators become inactive.

The mapping memory AB2, as a second mapping memory, allows for additional exchange of signals and parameters to the BP bit processor or WP word processor. For example, the word processor WP can write data from the mapping memory AB1 to the mapping memory AB2 during the inactive phase of the bus separator 2, and then process this data as a word program in the active phase of the bus separator 2.

The optional connection of the binary input / output unit 4 to / from the process to be controlled with the BP bit processor provides the advantage that the BP bit processor is

-4193837 can execute / release at high speed.

Claims (6)

PATENT CLAIMS A computer for word and bit processing combined with a word processor associated with a word library, a bit processor associated with a bit library, a mapping repository, connectors for digital and binary input and output channels, an address, data and control bus, and a bus. equipped with a separator unit, characterized in that the word library (WSP), the bit library (BSP) and the mapping store (AB1) are located in the address processor (ADR, DAT and STL) of the word processor (WP) and a first group consisting of a word processor (WP) and associated word library (WSP) in the address, data and control bus (ADR, DAT and STL) and a bit processor (BP) ), between a second group of associated bit library (BSP) and mapping library (AB1) associated with it, and digital and binary input and output channels directly in the word and these are connected to the bit processor (WP or BP), the word processor (WP) with the START wire (START), the bit processor (BP) and the bit processor (BP) with the STOP wire (STOP) and the bus separator (2); is connected to a word processor (WP). Computer according to Claim 1, characterized in that the bit processor (BP) is provided with a storage element (5) having a write input (S) for an erasure input (R) of a comparator (6) recognizing the coding of the END instruction from the word processor (WP). The START wire (START) is connected, and the output of the storage element (5) is connected as a STOP wire (STOP) to the activating input of the bus separator (2) and to the interrupt input of the word processor (WP). Computer according to claim 1 or 2, characterized in that the code for the END statement is stored in each of the erased storage bits of the bit program library (BSP). 4. A computer as claimed in any one of the preceding claims, characterized in that it is provided with a second imaging store (AB2), which is associated with the first group on the address, data and control bus (ADR, DAT and STL). 5. A computer as claimed in any one of the preceding claims, characterized in that the digital and binary input and output channels are connected to the word processor (WP). The computer of any one of claims T-4, wherein the digital input and output channels are connected to the word processor (WP) and the binary input and output channels are connected to the bit processor (BP).