HU190529B - Circuit arrangement for bus arrangement of systems with distributed intelligence, preferably for systems of automatic measurements - Google Patents

Abstract

The essence of the invention is that it has a distributed intelligence, a multi-level hierarchy, e.g. Measuring Automation System Controller MASTER Unit (1) Transmitter Drive Output (10) and Clock Line Drive Output (11) as well as Receiving Line Receiver Input (12) and Receiving Receiver Input (13) and receiving one or more SLAVE Units (3) data line receiving inputs (30) and a clock receiving process (31) as well as a receiver line output (32) and an output transmitter (33) and a clock line (21), a receiving line (22), and an application line (23) of the transmission line (20) of its system bus (2) and that the input line (30) of the transmission line drive output (10) of the MASTER unit (1) and the data line receiving (30) of the one or more SLAVE units (31) to the transmission line (29) of the system bus (21) is a clock line drive output (11) of its MASTER unit (1) and one or more SLAVE units (9) clock receiving inputs (31) on the clock line (21) of the system bus (21) on the receiving line (12) of the MASTER unit (1), and one or more SLAVE units k (3) ve line drive output (32) on the bus (2) of the system bus (2), the receiving input (31) of the MASTER unit (1), and the output (33) of one or more SLAVE units (3) on the system bus ( 2) join the application line (23). 1 ohm -1-

Description

BACKGROUND OF THE INVENTION The present invention relates to a system bus and interface assembly for bidirectional information transfer, which is particularly useful for metering automated and data acquisition systems with distributed intelligence requiring galvanic separation.

In computer and microcomputer-controlled systems, the expanding range of computing equipment and lowering prices has made possible and increasingly common systems where a system controller MASTER (micro) computer controls a very large number of measuring, data acquisition, data processing, and control units, but these subunits respectively. systems themselves contain intelligence (eg microcomputers). Such shared intelligence systems - other complex or large-scale systems such as. similar to measuring automated systems - lower level controller, etc. function microcomputers and the system controller MASTER. various bus systems are used to implement information traffic.

Some bus systems are widely distributed and, due to their technical advantages, have also been internationally standardized, while most measurement automation systems, especially target systems, are built on a special bus system that is best suited to the task.

For small-scale systems, the most obvious solution is to extend the control (micro) computer bus, possibly by simple buffering. However, such a solution generally allows only short distances to be bridged and does not allow a large number of peripherals to be connected.

The easiest way to bridge long distances is to use simple serial - eg. It is implemented by RS 232 standards, but cannot be upgraded to a bus system.

The IEC 625 (IEEE 488) bus system, which is internationally approved, is widely used. This bus with 16 active wires provides bridging distances of several meters. However, a major disadvantage with cost-minimized assemblies is that galvanically separated subsystems are very difficult to implement.

CAMAC system standards also provide a solution for interconnect buses for multiple CRATE systems. However, BRANCH HIGHWAY, due to its 128 interconnection wires, requires extremely complex interfaces, does not provide galvanic separation and cannot be used to control intelligent subsystems within the standard module system.

The difficulties described above are overcome by the circuit arrangement of the present invention, which also has further application advantages.

It is an object of the present invention to provide a bus system for shared intelligence systems comprising a MASTER controller (micro) computer and one or more SLAVE units, in which, in addition to the bus data line providing information from the MASTER unit to the SLAVE (s), the SLAVE (s) ) to the MASTER customer information line and

Interruptos login line (s) of SLAVE (s), respectively. It has a pair of lines to which additional power supply lines are connected to enable the address decoder units built into the SLAVE units and galvanic isolation of the SLAVE unit (s).

SUMMARY OF THE INVENTION The MASTER unit having a transmitter drive output has an additional independent clock synchronous output output and a receiving line input and interrupt receiving input for one or more SLAVE units, and an independent clock receiving input for one or more SLAVE units. a receiving line drive output and an interrupt output, and having an additional clock line, a receiving line, and an application line outside the system bus transmitting line, and having a MASTER unit transmitting line output and one or more SLAVE unit data line receiving to a system bus transmitting line clock input of multiple SLAVE units to the system bus clock line, MASTER unit receiving line input, and one or more SLAVE unit receiving line driver outputs the system bus receiving line ,, the interrupt receiving input of the MASTER unit and the interrupt output of one or more SLAVE units are connected to the system bus application line.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention is illustrated by the following units:

1. MASTER unit

System bus 2

3. SLAVE unit (s)

In Figure 1, the system wires 2 and 3 of the system bus 2 are shown in FIG. depending on the version, possibly pairs of wires) are indicated:

transmitting line (for transmitting information from MASTER to SLAVE) clock line (for synchronizing information flow within the system) receiving line (for transmitting information to MASTER).

application line (parallel interrupt wire for SLAVE units)

24, 25.26 power lines.

The transmission line 10 output of the MASTER unit 1 and the data line receiving line 30 of one or more SLAVE units 3 to the transmission line 20, the 11 clock line output of the MASTER unit 1 and the 31 clock input of one or more of the 3 SLAVE units 2 clock line, master line 12 master input 1 of master 1, and receiver line driver output 32 of one or more slave units 3 to receiving line 22 of system bus 2, 13 interrupt receiving input of 1 MASTER unit, and 33 interrupt output of one or more SLAVE units 3 to application line 23 join.

The circuit arrangement of Figure 1 operates as follows:

Multi-level hierarchy, possibly distributed intelligence - e.g. The central control unit for the measurement automation system is the 1 MASTER unit, which contains a (micro) computer and controls the

One or more 3 SLAVE slaves are connected via 190 529 system buses. All information traffic is initiated by MASTER 1 and transmitted synchronously to the respective clock clock input 21 of each of the SLAVE units 3 through the transmission line 20 it drives to the SLAVE units 3 in series. At the command of MASTER 1, a designated SLAVE unit 3 can send a message to MASTER 1 by driving the receiving line 22 of the system bus 2. The SLAVE units 3 are connected in parallel to the registration line 23, which serves to transfer their interrupted login to the MASTER 1.

An embodiment of the invention will be described with reference to FIG.

Figure 2 shows the following units (not previously described):

4.6 galvanic isolation blocks in SLAVE units my messages decoder circuit in SLAVE units unspecified central unit of SLAVE units serial signal and interrupt transmitter in SLAVE units line driver

In the embodiment of Figure 2, the switching arrangement is supplemented by a decoder circuitry for my messages 5 incorporated in the SLAVE units. My message 5 is a 50 line signal input to the decoder circuit via line receiver 9 and other units, directly or indirectly to the receiving line 30 of the SLAVE unit 3 data line. Similarly, its 51 clock inputs are directly or indirectly connected to the 31 clock input in the SLAVE unit.

The advanced circuit layout works as follows:

My messages 5 built into SLAVE units 3 decode decoder circuitry into properly organized information blocks (e.g., IBM SDLC bus protocol) from the data block heads on the transmission line 20 without using the intelligence of the SLAVE unit 3 to determine whether the message applies to that unit. As a result, information processing is significantly accelerated and does not burden the processing of each message head on the local microcomputer of the SLAVE units.

In a further expanded embodiment of the circuit arrangement, to provide galvanic isolation, the system bus 2 is supplemented with DC 24,25,26 power supply lines, and the 3 SLAVE units also include one or more 4,6 galvanic isolation blocks, which supply 24,25,26 power lines. The power supply outputs 14,15,16 of the MASTER unit and 34,35,36 power inputs of one or more of the 3 SLAVE units are connected, and which 34,35,36 power inputs are the 4.6 galvanic isolation block (s) 17,18 they are connected to a power input, while some of the galvanic isolation block (s) 6 are connected to the 50 serial signal inputs or to the decoder circuit of my 5 messages. 51 clock inputs and 30 data line receiving inputs and 3 slave units respectively. They are inserted between the 31 inputs of the clock signal and the other 4 galvanic isolation blocks 4 are connected to the 52 serial outputs of the 8 serial signal and interrupt transmitter. 53 interrupt output and 32 output line driver output of the SLAVE unit 3. 33 interrupt transmissions are inserted between them. The unspecified central unit 7 of the SLAVE units 3 is transmitted via control connections 54 to the decoder circuit and / or the transducer. connected to the 8 serial and interrupt transmitters.

The advanced switching arrangement works as follows: The system bus 2 is fed by DC power supply lines 24,25,26 through its power supply outputs 14,15,16, and the line receivers 9, 19 drives and 4, the SLAVE units 3, The 6 galvanic isolation blocks provide power to the bus-side input voltage 17.18 via this.

In addition to the above-described address decoder function of my decoder circuit 5, my messages also forward information received at the data line receiving input 30 to the respective SLAVE unit 3 to the central unit 7.

In a practical embodiment, the 4,6 galvanic isolation blocks not shown in the figure, for example with optical separators (e.g., type HCPL-2630), my message decoder circuit 5 for the SDLC standard protocol, e.g. with the SIIL VLSI component of the ZILOG Z80 family, the central unit of the 7 SLAVE units is conveniently implemented with a matching Z80 CPU. The 9.19 line receiver or line bending circuits according to SN 75107. . . They can be easily built using SN 75110 family elements or similar line drive / receiving components.

Because of the small number of wires, it is very advantageous that the galvanic isolation part of many SLAVE units can be fed from a single MASTER unit, eliminating the need for expensive and disturbed disconnected power supplies to be installed in the SLAVE units.

Thus, the advantages of the coupling according to the invention are as follows:

- as with serial data traffic systems, it allows bridging distances that vary depending on the speed of data traffic, but in any case considerable.

- does not require synchronization signal lengths with a decreasing effect on data traffic speeds due to synchronous data transmission.

- the interrupt cable allows for non-real-time logon for simple serial transmission systems.

- allows bidirectional interrupted information flow even with a small number of wires, - provides easy isolation of galvanic separation between individual components, - allows the maximum data rate allowed by the microcomputer to be realized between microcomputer subsystems, - low implementation costs .

Claims (3)

PATENT CLAIMS A circuit arrangement for a bus intelligence system for distributed intelligence systems, in particular measurement automation systems comprising a MASTER unit (1) and one or more SLAVE units (3) and a system bus (2), and wherein the transmission line drive output (10) of the MASter unit (1). system bus (2) transmission line (20) and data line receiving input for SLAVE unit (s) 190 529 (30) and which transceiver driver output (10) is connected to the transceiver line (20) of the system bus (2), provided that an additional clock line driver of the MASTER unit (1) is provided. has an output (11) and a receiving line input (12) and an interrupt receiving input (13) and that one or more SLAVE units (3) has a further clock receiving input (31) and a receiving line drive output (32) and interrupt output an output bus (33), and that the system bus (2) has an additional clock line (21), a receiving line (22) and an entry line (23), and that the MASTER unit (1) has a clock line output (11) and one or more Sl.AVE units ( 3) Clock receiving input (31) to system bus (2) clock line (21), MASTER unit (I) receiving line receiving (12) and one or more Sl.AVE units (3) receiving line drive output (32) to system bus (2) ) to customer line (22), MASTER unit (I) The interrupt receiving input (13) and the interrupt output (33) of one or more SLAVE units (2) are connected to the system bus (2) reporting line (23). A circuit arrangement according to claim 1, characterized in that one or more of the Sl.AVE units (3) of my message comprises a decoder circuit (5), the serial signal input (50) of my messages decoder circuit (5) being directly or directly by the SLA5 VE unit. (3) is connected to the receiving line (30) of the data line and its clock train (51) is connected directly or indirectly to the clock receiving (31) of the SLAVE unit (3). The circuit arrangement according to any one of claims I or 2, characterized in that The system bus (2) also has one or more galvanic isolation blocks (4,6) for supplying 10 galvanic isolation to the DC bus lines (24,25,26) and the SLAVE units (3) to supply the DC supply lines (24,25,26). the power supply outputs (14,15,16) ^{10 of} the MASTER _ unit (1) and one or more SLAVFs. the power inputs (34,35,36) of unit (3) are connected and which power inputs (34,35,36) are connected to the power input (17,18) of the galvanic isolation block (s) (4,6), galvanic 2Q isolation block (s) (6) is the serial signal input (50) to my messages at decoder current (5). clock input (51) and the data line receiving input (30) of the SLAVE unit, respectively. are inserted between the clock input terminals (31).