HK40112913A - Doherty amplifier with adaptive biasing - Google Patents

Description

Doherty amplifier with adaptive bias

Related applications

This application claims the benefit of provisional patent application serial number 63/346,391, filed on May 27, 2022, the disclosure of which is incorporated herein by reference in its entirety.

Technical Field

This disclosure relates to an amplifier structure for maximizing power amplifier efficiency under low average output power and low power supply voltage operation.

Background Technology

Compared to conventional power amplifiers, symmetrical Dougherty power amplifiers significantly improve power amplifier efficiency at power levels down by approximately 6 dB from their peak continuous wave power. Dougherty power amplifiers are typically configured to achieve optimal efficiency and linearity at their maximum average power under signal modulation. However, due to insufficient self-biasing of the peak amplifier in Dougherty power amplifiers, their performance is generally suboptimal under low average output power and low power supply voltage operation.

When a Dougherty power amplifier is configured to achieve optimal efficiency and linearity at its maximum average power under signal modulation, its performance is typically suboptimal at low average output power and low power supply voltage (Vcc) operation due to insufficient self-biasing of the peak amplifier. Although gallium arsenide (GaAs) heterojunction bipolar transistor (HBT) Dougherty power amplifiers can slightly improve continuous-wave P1dB power in the high Vcc range (>3.5V) compared to conventional counterparts, GaAs HBT Dougherty power amplifiers still exhibit significant amplitude modulation-amplitude modulation (AMAM) distortion and significant P1dB power loss (up to 6dB) in the low to mid-Vcc range (<3.5V). Therefore, further improvements to Dougherty amplifiers are needed because the average power statistics of mobile phones are largely distributed in the lower power region. This necessitates a new Dougherty amplifier architecture and approach to enable Dougherty power amplifiers to operate over a wider supply voltage range, including low to medium Vcc (<3.5V).

Summary of the Invention

An amplifier is disclosed, comprising a carrier amplifier and a peak amplifier coupled in parallel to the carrier amplifier, wherein the peak amplifier has a peak output transistor. A peak power supply adaptive bias generator is coupled to a bias control terminal of the peak output transistor. The peak power supply adaptive bias generator is configured to sense the power supply voltage of the peak amplifier and increase the bias current to the peak output transistor as the power supply voltage decreases.

After reading the following detailed description in conjunction with the accompanying drawings, those skilled in the art will understand the scope of this disclosure and recognize its additional aspects.

Attached Figure Description

The accompanying drawings, which are incorporated in and form a part of this specification, illustrate several aspects of this disclosure and, together with the specification, serve to explain the principles of this disclosure.

Figure 1 is a schematic diagram illustrating the differential Dougherty architecture in the demonstration power adaptive bias (dashed box).

Figures 2A to 2C show continuous wave waveform simulations of a differential Dougherty power amplifier and a conventional differential power amplifier, Fc = 2593 MHz.

Figure 2A is a graph showing the continuous wave power-added efficiency referenced at the power amplifier output: the pin sweeps from -30dBm to +10dBm in 1dB steps, and Vcc from 1V to 5.5V in 0.5V steps.

Figure 2B is a graph showing the amplitude modulation-amplitude modulation distortion of the transmitted continuous wave.

Figure 2C is a graph showing the simulated average power tracking of the transmission without memory: Signal: 100MHz 5G Cyclic Prefix Quadrature Phase Shift Keying (CP_QPSK) internal RB, MPR = 1.5dB.

Figure 3 shows a graph of the GSMA report on the transmit power distribution of mobile phones from wideband code division multiple access, and is a good approximation of 4G and 5G FR1 (frequency range 1) signals.

Figure 4 is a schematic diagram illustrating an embodiment of a bipolar junction transistor (BJT) with low leakage power supply adaptive bias; the BJT device can be replaced by a field-effect transistor (FET).

Figures 5A, 5B, 5C, and 5D are graphs illustrating adaptive biasing of a DC analog power supply and peak amplifier biasing with a swept supply voltage (Vcc) based on an exemplary gallium arsenide (GaAs) heterojunction bipolar transistor (HBT) embodiment: power amplifier bias categories are indicated in Figures 5C and 5D; Ven = 2.8V, Ireg2p = 4.6mA, Tambient = 25°C.

Figures 6A and 6B show the total Vcc leakage current simulation of the GaAs HBT Dougherty power amplifier at temperature and Vcc: Ven = 0V, Ireg = 0A.

Figure 6A is a graph showing the power supply adaptive bias with leakage protection D2 and Q11 removed as a baseline.

Figure 6B is a graph illustrating an embodiment of power supply adaptive bias (SAB) including D2 and Q11.

Figures 7A to 7F show the operation and instantaneous module output power of the Dougherty power amplifier under swept power supply Vcc.

Figures 7A, 7B, and 7C are graphs illustrating a conventional Dougherty power amplifier without power supply adaptive bias.

Figures 7D, 7E, and 7F are graphs showing a Dougherty power amplifier with power supply adaptive bias: pins: -30dBm to +10dBm, Fc = 2593MHz.

Figures 8A, 8B, 8C, and 8D are graphs showing the overall performance simulation of the Dougherty power amplifier with and without power supply adaptive bias: Fc = 2593 MHz.

Figure 9 is a comparison table of linear transmit output power in decibels to milliwatts (dBm).

Figures 10A, 10B, and 10C are plots showing the modulated signal simulation of the Dougherty power amplifier at module Avg Po = 15 dBm in the n41 band: Signal: 100 MHz 5G CP-QPSK internal RB; DC-DC converter eff = 92% in Ibatt's calculations.

Figure 11 is a schematic diagram illustrating another general embodiment of power supply adaptive bias; Ven is bound to Vreg or Ireg power supply is bound to power amplifier bias.

Figure 12 is a schematic diagram illustrating an alternative power adaptive bias embodiment with an enable device Q11 replaced by a FET device.

Figure 13 is a schematic diagram illustrating an alternative power supply adaptive biasing embodiment with both Q10 and Q11 replaced by FET devices.

Figure 14 is a schematic diagram illustrating an alternative complementary metal-oxide-semiconductor power supply adaptive bias embodiment with the positions of Q10 and Q11 swapped.

Figure 15 is a schematic diagram of a wireless communication device incorporating the Dougherty amplifier of this disclosure.

Detailed Implementation

The embodiments described below illustrate the information necessary to enable those skilled in the art to practice the embodiments and demonstrate the best mode of practice. Those skilled in the art will understand the concepts of this disclosure and recognize applications of these concepts not specifically described herein when reading the following description in conjunction with the accompanying drawings. It should be understood that these concepts and applications fall within the scope of this disclosure and the appended claims.

It should be understood that although the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

It should be understood that when an element, such as a layer, region, or substrate, is referred to as "on another element" or "extending to another element," it may be directly on or directly extended to the other element, or intermediate elements may be present. Conversely, when an element is referred to as "directly on another element" or "directly extending to another element," no intermediate elements are present. Similarly, it should be understood that when an element, such as a layer, region, or substrate, is referred to as "above another element" or "extending above another element," it may be directly above or directly extended above the other element, or intermediate elements may be present. Conversely, when an element is referred to as "directly above another element" or "extending directly above another element," no intermediate elements are present. It will also be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or intermediate elements may be present. Conversely, when an element is referred to as "directly connected" or "directly coupled" to another element, no intermediate elements are present.

For example, relative terms such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical" may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region as illustrated in the figures. It should be understood that these terms, and those discussed above, are intended to include different orientations of the device other than those depicted in the figures.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms “a” and “described” are also intended to include the plural forms. It should also be understood that, when used herein, the terms “comprises” and/or “includes” specify the presence of said features, integers, steps, operations, elements, and/or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that, unless expressly defined herein, the terms used herein shall be interpreted as having the same meaning as they have in the context of this specification and in the relevant art, and shall not be interpreted in an idealized or overly formal sense.

Embodiments are described herein with reference to illustrative drawings of embodiments of this disclosure. Thus, the actual dimensions of layers and elements may vary, and shapes are expected to differ from those illustrated due to, for example, manufacturing techniques and/or tolerances. For example, areas illustrated or described as squares or rectangles may have circular or curved features, and areas shown as straight lines may have some irregularity. Therefore, the areas illustrated in the figures are schematic, and their shapes are not intended to illustrate the precise shapes of the areas of the device, nor are they intended to limit the scope of this disclosure. Furthermore, for illustrative purposes, the size of structures or areas may be enlarged relative to other structures or areas, and thus structures or areas are provided to illustrate the general structure of the invention, and may be drawn to scale or not. Common elements between the figures may be indicated herein by common element reference numerals and may not be described further thereafter.

This disclosure relates to a power supply adaptive biasing method for adjusting the peak amplifier bias current based on the sensed supply voltage (Vcc) to achieve adequate load modulation across a wide Vcc supply range. Furthermore, a saturation-mode bipolar junction transistor device is placed within the power supply adaptive biasing to disable it in the power amplifier's shutdown mode. As a result, the Dougherty power amplifier exhibits improved amplitude modulation-amplitude modulation, amplitude modulation-phase modulation, and efficiency not only in the medium to low power range but also demonstrates specification-compliant power supply leakage current (≤1.2 μA) under extreme Vcc and temperature conditions. Additionally, this disclosure relates to a method for implementing low-leakage automatic power supply adaptive biasing in a Dougherty amplifier to achieve optimal average power point tracking (APT) performance in power mode/low power mode.

Figure 1 is a schematic diagram depicting a differential Dougherty power amplifier 10 constructed according to the present disclosure. The Dougherty power amplifier 10 is designed for use in 5G handheld transmission (TX) systems in the n40 and n41 frequency bands using gallium arsenide (GaAs) heterojunction bipolar transistor (HBT) technology. The Dougherty power amplifier 10 has two power amplification stages, wherein the first stage 12 is single-ended and the second stage 14 is differentially ended. The specified continuous-wave 1-dB gain compressed power target is 33.5 dBm at the antenna port 16 labeled ANT.

The first stage 12 has a radio frequency (RF) signal input 18 labeled RFIN. A 90° splitter 20 is configured to direct a first portion of the RF signal arriving at the RF signal input 18 into a carrier signal path and a second portion of the RF signal into a peak signal path. The carrier signal path includes a carrier driver transistor Q1 and a carrier input matching network 22 coupled between the carrier splitter output 24 of the 90° splitter 20 and the first driver base 26 of the carrier driver transistor Q1. A carrier driver bias generator 28 coupled to the first driver base 26 is configured to provide a substantially fixed bias for the carrier driver transistor Q1. A first coupling capacitor C1 is coupled between the first driver collector 30 and the first driver output 32 of the carrier driver transistor Q1. The first driver emitter 34 of the carrier driver transistor Q1 is coupled to a fixed voltage node G1, which in this exemplary embodiment is ground. The peak signal path includes a peak driver transistor Q2 and a peak input matching network 36 coupled between the peak splitter output 38 of the 90° splitter 20 and the second driver base 40 of the peak driver transistor Q2. A peak driver bias generator 42 coupled to the second driver base 40 is configured to provide a substantially fixed bias for the peak driver transistor Q2. A second coupling capacitor C2 is coupled between the second driver collector 44 of the peak driver transistor Q2 and the second driver output 46. The second driver emitter 48 of the peak driver transistor Q2 is coupled to a fixed voltage node G1.

The second stage 14 includes a first carrier power transistor Q3, configured to amplify the positive portion of the RF signal using the carrier path. A third coupling capacitor C3 is coupled between the positive carrier input 50 and the positive carrier base 52. The positive carrier emitter 54 of the first carrier power transistor Q3 is coupled to a fixed voltage node G1. The positive carrier collector 56 is coupled to a quarter-wavelength converter 58 via a first quarter-wavelength input 60. The second stage 14 further includes a second carrier power transistor Q4, configured to amplify the negative portion of the RF signal using the carrier path. A fourth coupling capacitor C4 is coupled between the load wave input 62 and the load wave base 64 of the second carrier power transistor Q4. The load wave emitter 66 is coupled to a fixed voltage node G1. The load wave collector 68 is coupled to a quarter-wavelength converter 58 via a second quarter-wavelength input 70. The first carrier power transistor Q3 and the second carrier power transistor Q4 are collectively referred to as carrier output transistors.

A carrier power bias generator 72 is coupled between the positive carrier base 52 and the load wave base 64. The carrier power bias generator 72 is configured to provide a substantially fixed bias to both the first carrier power transistor Q3 and the second carrier power transistor Q4. A carrier signal converter 74 is coupled within the carrier signal path between the first stage 12 and the second stage 14. The carrier signal converter 74 has a primary coil 76 coupled between the first driver output 32 and the fixed voltage node G1. The carrier signal converter 74 has a secondary coil 78 coupled between the positive carrier input 50 and the load wave input 62.

The second stage 14 further includes a first peak power transistor Q5, which is configured to amplify the positive portion of the RF signal using a peak path. A fifth coupling capacitor C5 is coupled between the positive peak input 80 and the positive peak base 82. The positive peak emitter 84 of the first peak power transistor Q5 is coupled to a fixed voltage node G1. The positive peak collector 86 is coupled to a positive output 88, which is further coupled to a first quarter-wavelength output 92 of the quarter-wavelength converter 58. The amplified signals from the first carrier power transistor Q3 and the first peak power transistor Q5 are summed together at the positive output 88.

The second stage 14 further includes a second peak power transistor Q6, which is configured to amplify the negative portion of the RF signal using the peak path. A sixth coupling capacitor C6 is coupled between the negative peak input 94 and the negative peak base 96 of the second peak power transistor Q6. The negative peak emitter 98 is coupled to a fixed voltage node G1. The negative peak collector 100 is coupled to a negative output 102, which is further coupled to a second quarter-wavelength output 104. The amplified signals from the first peak power transistor Q5 and the second peak power transistor Q6 are summed together at the negative output 102.

A peak power supply adaptive bias generator 106 is coupled between the positive peak base 82 and the negative peak base 96. The peak power supply adaptive bias generator 106 is configured to provide bias to both the first peak power transistor Q5 and the second peak power transistor Q6. The first peak power transistor Q5 and the second peak power transistor Q6 are collectively referred to as peak output transistors.

A peak signal converter 108 is coupled within the peak signal path between a first stage 12 and a second stage 14. The peak signal converter 108 has a primary coil 110 coupled between a second driver output 46 and a fixed voltage node G1. The peak signal converter 108 has a secondary coil 112 coupled between a positive peak input 80 and a negative peak input 94. A balun 114 has a balanced side coil 116 coupled between a positive output 88 and a negative output 102. The balanced side coil 116 has a power tap 118 coupled to a power supply voltage source VCC, which supplies power to a first carrier power transistor Q3, a second carrier power transistor Q4, a first peak power transistor Q5, and a second peak power transistor Q6. A first bypass capacitor C7 is coupled between the power tap 118 and the fixed voltage node G1. An isolation inductor LISO1 is coupled between the power tap 118 and the voltage source VCC. A second bypass capacitor C8 is coupled between the voltage source VCC and the fixed voltage node G1. The unbalanced side coil 120 is coupled between the antenna port 16 and the fixed voltage node G1.

The Dougherty power amplifier 10 depicted in Figure 1 is designed for use in 5G mobile phone transmission (TX) modules in the n40 and n41 bands based on GaAs HBT processes. The Dougherty power amplifier 10 has a continuous-wave 1-dB gain compression power target (P1dB), specified at 33.5dBm at its output, where Vcc = 5V. Figure 2A is a graph showing the simulated performance of the baseline Dougherty power amplifier without adaptive power supply bias, compared to a conventional differential power amplifier designed for the same band. The baseline Dougherty power amplifier exhibits a significant improvement in power back-off (PBO) power-added efficiency (PAE) over the conventional power amplifier at swept Vcc, as shown in Figure 2A. However, the emitter gain versus instantaneous output power graph plotted in Figure 2B highlights the problems with the baseline Dougherty power amplifier before implementing adaptive power supply bias. While the baseline Dougherty power amplifier slightly improves continuous wave P1dB power in the high Vcc range (>3.5V) in this example, it exhibits significant amplitude modulation-amplitude modulation (AMAM) distortion and a substantial loss of up to 6dB in P1dB power in the low to mid Vcc range (<3.5V in this example). Figure 2C is a graph illustrating a transmit (TX) memoryless modulated signal simulation, where an exemplary 5G signal is located at a resource block within a 100MHz cyclic prefix quadrature phase shift keying (CP-QPSK). As expected from the continuous wave simulation, the baseline Dougherty power amplifier achieves a linear output power loss of 5dB to 6dB in the low to mid Vcc range that meets the Evolved Universal Terrestrial Radio Access (EUTRA) target of -36dBc, compared to a conventional power amplifier. The performance gaps of the baseline Dougherty power amplifier, as shown in Figures 2A, 2B, and 2C, require improvement because low-power operation is crucial for the average mobile phone user experience. The GSM Association has published the TX power probability distribution function, as shown in Figure 3 for Wideband Code Division Multiple Access (WCDMA). These published TX power probability distribution functions are good approximations for both 4G and 5G signals. Although power amplifiers are typically optimized for peak power performance, statistically, the probability of it operating at that level is very low. Instead, it is more likely to occur between 10dB and 50dB below peak power. Compared to peak power, backoff power operation requires a lower supply voltage Vcc to reduce battery current draw.

Figure 4 is a detailed schematic diagram of an exemplary embodiment of a peak power supply adaptive bias generator 106, which controls the bias of the first peak power transistor Q5 and the second peak power transistor Q6 of the second stage 14 of the Dougherty power amplifier 10 shown in Figure 1. The bias generator circuit 122 and the power supply adaptive circuit 124 constitute the peak power supply adaptive bias generator 106. The bias generator circuit 122 has a seventh transistor Q7 and an eighth transistor Q8, both in a diode configuration, and is coupled in series with a regulator resistor REG1 between node A and the fixed voltage node GND1. In operation, a current IREGB flows from the current regulator terminal IREG at node A. The current IREGB flows through the regulator resistor REG1. A ninth transistor Q9, configured as a bias generator transistor, has its base coupled to node B. The emitter of the ninth transistor Q9 is coupled to the positive peak base 82 through the first base resistor RBB1, and to the negative peak base 96 through the second base resistor RBB2. The collector of the ninth transistor Q9 is coupled to the battery voltage VBATT. The first filter capacitor CFIL1 is coupled from the base of the ninth transistor Q9 to the fixed voltage node GND1.

In this exemplary embodiment, the power adaptive circuit 124 includes a tenth transistor Q10, referred to as a debiasing transistor, and an eleventh transistor Q11, referred to as an enable transistor, connected in series between node A and a fixed voltage node GND1. Debiasing control, in the form of the base or gate of the tenth transistor Q10, is coupled to a power supply voltage sensing terminal labeled VCC(SENSE) via a first sensing resistor RS1, a second sensing resistor RS2, and a first diode D1, referred to as a sensing diode, having a cathode coupled to the base of the tenth transistor Q10. The collector of the tenth transistor Q10 is coupled to node A via a debiasing current branch, which in this exemplary embodiment includes a second diode D2, referred to as a debiasing diode, and a first collector resistor RC1. In this exemplary embodiment, node A is the bias control node of the bias generator circuit 122. However, in other embodiments, node B is the bias control node to which the debiasing current branch is coupled. In this exemplary embodiment, the cathode of the second diode D2 is coupled to the tenth transistor Q10. The second filter capacitor CFIL2 is coupled between the fixed voltage node GND1 and the node between the first sensing resistor RS1 and the second sensing resistor RS2. The base of the eleventh transistor Q11 is coupled to the enable terminal marked VEN via a third diode D3, referred to as the enable diode, and an enable resistor REN1. The cathode of the third diode D3 is coupled to the base of the eleventh transistor Q11.

The sense current I _sense is calculated by the following equation 1:

Where β is the forward current gain of the BJT device in equations 1 to 4.

This disclosure relates to a Vcc power supply adaptive biasing method to overcome low-power performance degradation in a baseline Dougherty power amplifier 10. As shown in Figure 4, the peak power supply adaptive biasing generator 106 first senses Vcc at the radio frequency (RF) filter node VCC (SENSE) of the TX module. Rs1 and Cfil2 further reduce any spurious RF coupled to the sensed signal. Then, the power supply adaptive biasing derives and injects a current Idebias associated with Vcc, as shown in Equation 2. This Idebias is subtracted from the existing external bias Vreg or Ireg. For simplicity, Ireg is chosen for analysis. Therefore, the net Iregb (＝Ireg-Idebias) entering the power amplifier biasing network also depends on Vcc. To have the desired Idebias versus Vcc curve, as shown in Figure 5A, several components of the power supply adaptive biasing circuit are used:

(i)Q10 generates Idebias based on the sensed Vcc and operates in a cutoff mode below the Vcc threshold, an active region in the medium Vcc region, and a saturation mode in the high Vcc region.

(ii) D1 is used to control the Vcc threshold voltage of the Idebias ramp, which is ~1.7V in this exemplary embodiment (see Figure 5A).

(iii) The slope of Idebias relative to Vcc within the Vcc range in the control of Rs (＝Rs1+Rs2) and Re (＝RE1 resistance) values.

(iv) Rc (＝RC1 resistor) and D2 control the Vce margin of the Q10 device and limit Idebias at high Vcc levels, as shown in Figures 5A and 5B.

(v) Q11 is turned on and off by an external Ven power supply. When Q11 is on, it operates in saturation mode and its saturation Vce is very low (<0.2V for GaAs HBT process, as shown in Figure 5B).

In equation (v), the external Ven supply voltage needs to be higher than the combined turn-on voltage of D3 and Q11 as expressed by equation 3 during the on-state. Equation 4 shows the Ren condition for driving Q11 to saturation mode during the on-state. A practical guideline is that the left side of the inequality is approximately 0.1 times that of the right side. On the other hand, when Ren is too low, it will cause excessive current to be drawn from the Ven supply. Ren and D3 should be designed in accordance with the Ven supply specifications. During the power amplifier's off-state, Vcc can be high, but Ven and Ireg are off, blocking Q11 and presenting an open circuit to prevent any current leakage through it. To completely limit Icc leakage, D2 serves a secondary purpose by stopping the reverse current from the Q10 B-C diode to Q7, Q8, and GND1. Adding Q10 and D2 to remove the power supply adaptive bias leakage current is an advantageous feature of the architecture according to this disclosure.

Figure 4 also depicts a general embodiment of a power supply adaptive bias for controlling the power amplifier bias, where the Idebias shunt location can be any node along the reference current path of the bias network, as labeled “A”, “B”, and “C”. The BJT device in the power supply adaptive bias can be replaced with a field-effect transistor (FET) device when available. Q10 in Figure 4 is used to scale the Idebias from the sensed Vcc. Q11 in Figure 4 is used to turn the power supply adaptive bias on and off. When implemented with a BJT, the BJT operates in saturation mode to achieve a low Vce drop and operates in cutoff mode to present an open circuit to GND. When using an FET, the FET simply operates in on and off modes. Diodes D1, D2, and D3 can be conventional diodes or three-terminal devices, such as diode connections of a BJT or FET. Alternatively, D1 and D2 can be omitted when specifying a low Vcc range. The placement of diode D3 according to this disclosure causes a level shift in the base voltage of Q11, and therefore it can be removed when the supplied Ven is only slightly higher than Q11 Vbe. Rs is divided into Rs1 and Rs2 in Figure 4 to achieve design flexibility for the filter time constant. Rs1 and Rs2 can be combined into one. Cfil2 can be removed if the sensed Vcc is considered sufficiently clean.

After careful design, the required pQ2 (i.e., Q5 and Q6) bias versus Vcc curves are shown as solid traces in Figures 5C and 5D. In the high Vcc region, pQ2 is biased at category “C” as required in a standard Dougherty power amplifier design. As Vcc decreases, the pQ2 quiescent current Icq is pulled up to category “B”, and then pulled up to category “AB” at extremely low Vcc levels. This bias curve is designed to compensate for the weaker RF-regulated self-biasing in the low Vcc region. Furthermore, the reduction in Vcc leakage current according to this disclosure is shown in Figure 6. Figure 6A plots the leakage current of a power-adaptive biased Dougherty power amplifier without considering this aspect, by removing Q11 and D2. A maximum Vcc leakage of 300 μA is simulated under extreme conditions, which severely deviates from the typical 10 μA specification of a mobile phone TX module. In Figure 6B, a maximum Vcc leakage of 1.2 μA under the same extreme conditions is shown according to a complete embodiment of this disclosure, which conforms to current leakage specifications with good margin.

Figure 7 analyzes the bias, load modulation, and output power breakdown of the Dougherty power amplifier during power and Vcc sweeps. Based on the theoretical load line design of the Dougherty power amplifier, the simulated carrier amplifier load is expected to travel from 48 ohms in the low/medium power region to a target of 24 ohms at peak power. Accordingly, the peak amplifier load should move from a very high impedance to the target 24 ohms at peak power. The actual simulated peak power load drifts slightly due to the effect of the power amplifier's harmonic termination on the power amplifier's performance. Figures 7A, 7B, and 7C illustrate the operating conditions of the Dougherty power amplifier without power supply adaptive bias, while Figures 7D, 7E, and 7F illustrate those with power supply adaptive bias. For a fixed-bias Dougherty power amplifier, both the carrier amplifier and peak amplifier biases remain constant in the low power region as the power supply Vcc sweeps from 1V to 5.5V, as shown in Figure 7A. In the high power region, these bias points shift due to the self-biasing of the RF regulation. Figure 7B illustrates the root cause of performance degradation in the low Vcc region (Vcc ≤ 3.5V). Although load modulation occurs as expected on the power drive in the high Vcc region, it is significantly reduced in the low Vcc region. Both the carrier amplifier and the peak amplifier miss their peak power load target at low Vcc. Therefore, both power amplifiers experience peak Pout losses at low Vcc, as shown in Figure 7C. When the power supply adaptive bias according to this disclosure is implemented in the Dougherty power amplifier, the power supply adaptive bias adaptively biases the peak amplifier 14 according to the Vcc value shown in Figure 7D. The benefit is shown in Figure 7E, where both the carrier amplifier and the peak amplifier load are now optimally down-modulated to the peak power target at all Vcc levels. Figure 7F shows how the output power POUT of the second stage 14 is significantly improved at low Vcc, and how the power contributed by the first carrier power transistor Q3, the second carrier power transistor Q4, the first peak power transistor Q5, and the second peak power transistor Q6 converges in the curve for all Vcc values, as is expected in the operation of a symmetrical Dougherty power amplifier, i.e., with equal peak Pout between the carrier and peak amplifiers.

The AMAM and Amplitude Modulation-Phase Modulation (AMPM) plots in Figures 8A and 8C respectively illustrate the significant continuous wave performance improvement of the Dougherty power amplifier with the disclosed power adaptive bias in the low Vcc region compared to the Dougherty power amplifier without power adaptive bias. The 5G CP-QPSK simulated EUTRA adjacent channel power (ACP) plot (Figure 8D) also shows a significant linear power improvement. Only negligible AMAM and AMPM effects are observed in the high Vcc region. The power amplifier PAE plot (Figure 8B) does not show the negative impact from the power adaptive bias across Vcc and actually exhibits improved PBO efficiency in the high Vcc region. A tabular linear Pout at the module output is summarized in Figure 9, which also includes a conventional non-Dougherty power amplifier for reference. It should be noted that for Vcc > 3.5V, the Dougherty power amplifier in this exemplary design shows a Pout that is very similar to or higher than that of a conventional power amplifier. When Vcc drops below 3.5V, the Dougherty power amplifier without power adaptive bias exhibits significant losses at Pout, but power adaptive bias corrects the Pout issue, as shown in the last column of Figure 9. At 1V, the power adaptive bias Dougherty power amplifier still lacks a few dB of power compared to the reference design, which can be compensated for by further optimizing the bias current and quiescent current profile changes, possibly at the expense of efficiency.

Figures 10A, 10B, and 10C are plots illustrating the modulated signal simulation of a Dougherty power amplifier at a module Avg Po = 15 dBm in the n41 band: Signal: 100 MHz 5G CP-QPSK internal RB; DC-DC converter eff = 92% in Ibatt calculations. Note that for the baseline Dougherty power amplifier without power supply adaptive bias, Vcc needs to be increased to overcome power losses. The pQ2 Ireg2P value was found through performance optimization, and the remaining power stage biases were at the same value between the two power amplifiers. The two power amplifiers have very similar gain and EUTRA ACP performance. However, the disclosed embodiment of the Dougherty power amplifier 10 with power supply adaptive bias shows approximately 10% Ibatt current savings in the n41 band.

Alternative embodiments include, but are not limited to, the following:

1. An alternative implementation of the dashed box in Figure 4 can be achieved by removing D1, D2, D3, or any combination of D1, D2, and D3.

2. If the sensed Vcc has a relatively low level of radio frequency energy, an alternative implementation of the embodiment in Figure 4 can be achieved by removing Rs1 and Cfil2.

3. An alternative embodiment, as shown in Figure 11, is implemented by supplying Ven directly from the power amplifier bias Vreg or Ireg. This is feasible because the power amplifier bias voltage is at least 2x Vbe of the BJT device and is therefore high enough to drive Q11. When the power amplifier is off, Vreg or Ireg is typically turned off. This embodiment saves on an external Ven supply, thereby simplifying the implementation according to this disclosure.

4. An alternative embodiment with adaptive power bias is shown in Figure 12. When available from the process, Q11 is replaced with a FET device. If Q11 is a complementary metal-oxide-semiconductor (CMOS) device, Ren and D3 can be removed.

5. Figure 13 shows another alternative embodiment of power supply adaptive bias. Both Q10 and Q11 are implemented using FET devices. When Q11 is a CMOS device, REN1 and D3 can be removed. When Q10 is a CMOS device, RS2, D1, and RE1 can be removed.

6. Figure 14 shows another alternative embodiment of the power supply adaptive bias. Both Q10 and Q11 are implemented using CMOS devices, and their placement is interchanged. In this embodiment, REN1 and D3 can be removed. RS2 and D1 can also be removed.

In operation, in this method, the peak power supply adaptive bias generator 106 is configured to sense the supply voltage of the peak amplifiers (i.e., Q5 and Q6) and increase the bias current to the peak output transistor as the supply voltage decreases. In an exemplary embodiment, the method further includes the steps of: controlling the magnitude of the bias current flowing to the peak output transistor in response to the debias current flowing through the bias control nodes A/B; and adjusting the debias current flowing through the debias current branch in response to changes in the supply voltage.

Furthermore, the power supply adaptive circuit 124 is configured to gradually reduce the debias current of the bias control nodes A/B of the bias generator circuit 122 as the power supply voltage decreases. The method also includes the step of increasing the bias current of the peak output transistor in response to the reduced debias current.

Furthermore, the power supply adaptive circuit 124 is configured to gradually increase the debias current supplied to the bias control nodes A/B of the bias generator circuit 122 as the power supply voltage increases. The method also includes the step of reducing the bias current of the peak output transistor in response to the increased debias current.

Referring to Figure 15, the concepts described above can be implemented in various types of wireless communication devices or user elements 126, such as mobile terminals, smartwatches, tablets, computers, navigation devices, and access points, that support wireless communications such as cellular, wireless local area networks (WLAN), Bluetooth, and near-field communication. User element 126 typically includes a control system 128, a baseband processor 130, a transmitting circuit system 132, a receiving circuit system 134, an antenna switching circuit system 136, multiple antennas 138, and a user interface circuit system 140. The receiving circuit system 134 receives radio frequency signals from one or more base stations via antennas 138 and through antenna switching circuit system 136. Low-noise amplifiers and filters cooperate to amplify and eliminate broadband interference from the received signal for processing. Then, a down-conversion and digitization circuit system (not shown) down-converts the filtered received signal to an intermediate or baseband frequency signal, and then digitizes the signal into one or more digital streams.

Baseband processor 130 processes the digitized received signal to extract the information or data bits transmitted in the received signal. This processing typically includes demodulation, decoding, and error correction operations. Baseband processor 130 is typically implemented in one or more digital signal processors (DSPs) and application-specific integrated circuits (ASICs). For transmission, baseband processor 130 receives digitized data, which may represent voice, data, or control information, from control system 128, and encodes the digitized data for transmission. The encoded data is output to transmit circuitry system 132, where a modulator uses the data to modulate a carrier signal at a desired transmission frequency or multiple desired transmission frequencies. Dougherty power amplifier system 10 amplifies the modulated carrier signal to a level suitable for transmission and delivers the modulated carrier signal to multiple antennas 138 via antenna switching circuitry system 136. The multiple antennas 138, along with the repeating transmit circuitry 132 and receive circuitry 134, can provide spatial diversity. Those skilled in the art will understand the modulation and processing details.

Those skilled in the art will recognize improvements and modifications to this disclosure. All such improvements and modifications are considered to be within the scope of the concepts disclosed herein.

Claims (34)

1. An amplifier, comprising: • Carrier amplifier; A peak amplifier, coupled in parallel with the carrier amplifier, wherein the peak amplifier has a peak output transistor; and A peak power supply adaptive bias generator is coupled to the bias control terminal of the peak output transistor, wherein the peak power supply adaptive bias generator is configured to sense the power supply voltage of the peak amplifier and increase the bias current of the peak output transistor as the power supply voltage decreases. 2. The amplifier according to claim 1, wherein the peak power supply adaptive bias generator comprises: • A bias generator circuit having a bias control node and a bias output coupled to a bias control input of the peak output transistor, wherein the bias generator circuit controls the magnitude of the bias current to the peak output transistor in response to a debias current flowing through the bias control node; and • A power adaptive circuit having a power voltage sensing terminal configured to receive the power supply voltage supplying the peak amplifier, and a debias current branch coupled to the bias control node, wherein the power adaptive circuit is configured to adjust the debias current flowing through the debias current branch in response to a change in the power supply voltage. 3. The amplifier of claim 2, wherein the power supply adaptive circuit is configured to: • The debiasing current supplied to the bias control node of the bias generator circuit gradually decreases as the power supply voltage decreases; and Accordingly, the bias generator circuit is configured to increase the bias current of the peak output transistor in response to a decrease in the debias current. 4. The amplifier of claim 2, wherein the power supply adaptive circuit is configured to: • The debiasing current supplied to the bias control node of the bias generator circuit gradually increases as the power supply voltage increases; and Accordingly, the bias generator circuit is configured to reduce the bias current of the peak output transistor in response to an increased debias current. 5. The amplifier of claim 2, wherein the bias generator circuit includes a bias generator transistor having a base coupled to the bias control node, a collector coupled to a voltage source, and an emitter coupled to the bias control terminal of the peak output transistor. 6. The amplifier of claim 5, wherein the bias generator circuit further includes a filter capacitor coupled between the base and the fixed voltage node. 7. The amplifier of claim 2, wherein the power supply adaptive circuit includes a debiasing transistor and an enable transistor connected in series within the debiasing current branch, wherein when the enable transistor is in an enabled state, a debiasing current flows through the debiasing transistor and the enable transistor, and wherein when the enable transistor is in a disabled state, no debiasing current flows through the debiasing transistor and the enable transistor. 8. The amplifier of claim 7, wherein both the debiasing transistor and the enable transistor are bipolar transistors. 9. The amplifier of claim 7, wherein both the debiasing transistor and the enable transistor are field-effect transistors. 10. The amplifier of claim 7, wherein the debiasing transistor is a bipolar transistor and the enabling transistor is a field-effect transistor. 11. The amplifier of claim 7, wherein the debiasing transistor has a debiasing control terminal coupled to a power supply voltage sensing terminal configured to receive the power supply voltage, and the enable transistor has an enable control coupled to an enable terminal configured to receive an enable/disable voltage level that places the enable transistor in the enable state and the disable state. 12. The amplifier of claim 7, wherein the debias current branch further comprises a debias diode connected in series with the debias transistor and the enable transistor. 13. The amplifier of claim 7 further includes an enable diode coupled between the enable control and the enable terminal. 14. The amplifier of claim 7 further includes a sensing diode coupled between the debias control terminal and the power supply voltage sensing terminal. 15. The amplifier of claim 7, further comprising a low-pass filter coupled between the power supply voltage sensing terminal and the debiasing control terminal, wherein the low-pass filter is configured to remove RF frequency noise from the power supply voltage at the power supply voltage sensing terminal. 16. A method for amplifying a signal using a carrier amplifier and a peak amplifier coupled in parallel with the carrier amplifier, and a peak power supply adaptive bias generator, wherein the peak amplifier has a peak output transistor, and the peak power supply adaptive bias generator is coupled to a bias control terminal of the peak output transistor, the method comprising configuring the peak power supply adaptive bias generator to sense a power supply voltage of the peak amplifier, and increasing the bias current of the peak output transistor as the power supply voltage decreases. 17. The method of claim 16, wherein the peak power supply adaptive bias generator comprises a bias generator circuit and a power supply adaptive circuit, the bias generator circuit having a bias control node and a bias output coupled to a bias control input of the peak output transistor, the power supply adaptive circuit having a power supply voltage sensing terminal and a debias current branch coupled to the bias control node, the method further comprising the following steps: • The magnitude of the bias current controlled to the peak output transistor in response to the debias current flowing through the bias control node; and • Adjust the debias current flowing through the debias current branch in response to changes in the power supply voltage. 18. The method of claim 17, wherein the power supply adaptive circuit is configured to gradually reduce the debias current supplied from the bias control node of the bias generator circuit as the power supply voltage decreases, the method further comprising the step of increasing the bias current of the peak output transistor in response to the reduced debias current. 19. The method of claim 17, wherein the power supply adaptive circuit is configured to gradually increase the debias current supplied from the bias control node of the bias generator circuit as the power supply voltage increases, the method further comprising the step of reducing the bias current of the peak output transistor in response to the increased debias current. 20. A wireless communication device, comprising: • Baseband processor; • A transmitting circuit system configured to receive coded data from the baseband processor and modulate a carrier signal with the coded data, wherein the transmitting circuit system includes: • Carrier amplifier; A peak amplifier, coupled in parallel with the carrier amplifier, wherein the peak amplifier has a peak output transistor; and A peak power supply adaptive bias generator is coupled to the bias control terminal of the peak output transistor, wherein the peak power supply adaptive bias generator is configured to sense the power supply voltage of the peak amplifier and increase the bias current of the peak output transistor as the power supply voltage decreases. 21. The wireless communication device of claim 20, wherein the peak power supply adaptive bias generator comprises: • A bias generator circuit having a bias control node and a bias output coupled to a bias control input of the peak output transistor, wherein the bias generator circuit controls the magnitude of the bias current to the peak output transistor in response to a debias current flowing through the bias control node; and • A power adaptive circuit having a power voltage sensing terminal configured to receive the power supply voltage supplying the peak amplifier and a debias current branch coupled to the bias control node, wherein the power adaptive circuit is configured to adjust the debias current flowing through the debias current branch in response to a change in the power supply voltage. 22. The wireless communication device of claim 21, wherein the power adaptive circuit is configured to: • The debiasing current supplied to the bias control node of the bias generator circuit gradually decreases as the power supply voltage decreases; and Accordingly, the bias generator circuit is configured to increase the bias current of the peak output transistor in response to a decrease in the debias current. 23. The wireless communication device of claim 21, wherein the power adaptive circuit is configured to: • The debiasing current supplied to the bias control node of the bias generator circuit gradually increases as the power supply voltage increases; and Accordingly, the bias generator circuit is configured to reduce the bias current of the peak output transistor in response to an increased debias current. 24. The wireless communication device of claim 21, wherein the bias generator circuit includes a bias generator transistor having a base coupled to the bias control node, a collector coupled to a voltage source, and an emitter coupled to the bias control terminal of the peak output transistor. 25. The wireless communication device of claim 24, wherein the bias generator circuit further includes a filter capacitor coupled between the base and the fixed voltage node. 26. The wireless communication device of claim 21, wherein the power adaptive circuit includes a debiasing transistor and an enable transistor connected in series within the debiasing current branch, wherein when the enable transistor is in an enabled state, a debiasing current flows through the debiasing transistor and the enable transistor, and wherein when the enable transistor is in a disabled state, no debiasing current flows through the debiasing transistor and the enable transistor. 27. The wireless communication device of claim 26, wherein both the debiasing transistor and the enable transistor are bipolar transistors. 28. The wireless communication device of claim 26, wherein both the debiasing transistor and the enable transistor are field-effect transistors. 29. The wireless communication device of claim 26, wherein the debiasing transistor is a bipolar transistor and the enabling transistor is a field-effect transistor. 30. The wireless communication device of claim 26, wherein the debiasing transistor has a debiasing control terminal coupled to a power supply voltage sensing terminal configured to receive the power supply voltage, and the enabling transistor has an enabling control coupled to an enabling terminal configured to receive an enabling/disabling voltage level that places the enabling transistor in the enabling state and the disabling state. 31. The wireless communication device of claim 26, wherein the debias current branch further includes a debias diode connected in series with the debias transistor and the enable transistor. 32. The wireless communication device of claim 26, further comprising an enable diode coupled between the enable control and the enable terminal. 33. The wireless communication device of claim 26 further includes a sensing diode coupled between the debiasing control terminal and the power supply voltage sensing terminal. 34. The wireless communication device of claim 26, further comprising a low-pass filter coupled between the power supply voltage sensing terminal and the debiasing control terminal, wherein the low-pass filter is configured to remove RF frequency noise from the power supply voltage at the power supply voltage sensing terminal.