HK1237991B - Methods for removing nuclei formed during epitaxial growth - Google Patents

Description

Method for removing nuclei formed during epitaxial growth

Technical Field

The present application relates generally to methods for fabricating semiconductor devices. More particularly, the disclosed embodiments relate to methods for removing nuclei formed on semiconductor devices during an epitaxial growth process.

Background Art

Epitaxial growth is a common method for creating crystalline regions on semiconductor substrates. However, the formation of semiconductor structures in undesired regions of a semiconductor substrate is undesirable. For example, any semiconductor structures grown in undesired regions of a semiconductor substrate may adversely affect the electrical and/or mechanical properties of devices formed on the substrate.

Selective epitaxial growth (SEG) is used to create crystalline regions on targeted areas of a semiconductor substrate. For selective epitaxial growth, the semiconductor substrate is covered with a mask material, exposing certain areas of the underlying substrate. For such a semiconductor substrate, epitaxial growth occurs primarily on the exposed areas of the semiconductor substrate and less frequently on the mask material. While selective epitaxial growth can reduce the formation of structures (e.g., in the form of nuclei or layers) on the mask material during epitaxial growth, depending on process conditions, many semiconductor structures may still form on the mask material during epitaxial growth.

Various attempts have been made to eliminate the formation of epitaxial growth structures on the mask material. For example, certain growth conditions have been found to further suppress the formation of epitaxial growth structures on the mask material. However, small deviations from the prescribed growth conditions can easily lead to the formation of more epitaxial growth structures on the mask material. Therefore, the use of such growth conditions is limited.

Summary of the Invention

Therefore, there is a need for an improved method for removing nuclei formed during epitaxial growth. In some embodiments, the method is less sensitive to changes in growth conditions. Thus, such an improved method also allows for faster epitaxial growth of semiconductor structures while reducing the formation of semiconductor structures on undesirable areas of the substrate during epitaxial growth.

Several embodiments that overcome the limitations and disadvantages described above are described in more detail below. These embodiments provide devices and methods for manufacturing such devices.

As described in greater detail below, some embodiments relate to a method for removing nuclei formed during a selective epitaxial growth process, comprising epitaxially growing a first set of one or more semiconductor structures on a substrate having one or more masking layers. Forming a second set of multiple semiconductor structures on the one or more masking layers. The method further comprises forming one or more protective layers on the first set of one or more semiconductor structures. At least a subset of the second set of multiple semiconductor structures is exposed from the one or more protective layers. The method further comprises etching at least a subset of the second set of multiple semiconductor structures after forming the one or more protective layers on the first set of one or more semiconductor structures.

According to some embodiments, a semiconductor device includes a substrate; a first mask layer region located on the substrate; and a second mask layer region located on the substrate. The first mask layer region has a top surface and side surfaces, and the second mask layer region has a top surface and side surfaces. The semiconductor device also includes an epitaxially grown semiconductor structure of a first semiconductor material type. The epitaxially grown semiconductor structure is located between the side surfaces of the first mask layer region and the side surfaces of the second mask layer region, and the epitaxially grown semiconductor structure contacts the side surfaces of the first mask layer region and the side surfaces of the second mask layer region. The top surface of the first mask layer region and the top surface of the second mask layer region do not contact any semiconductor of the first semiconductor material type other than the epitaxially grown semiconductor structure located between the side surfaces of the first mask layer region and the side surfaces of the second mask layer region.

BRIEF DESCRIPTION OF THE DRAWINGS

For a better understanding of the aforementioned aspects, as well as additional aspects and embodiments thereof, reference is made to the following detailed description in conjunction with the following drawings.

1A-1I are partial cross-sectional views of a semiconductor substrate according to some embodiments.

2A-2C are partial cross-sectional views of a semiconductor substrate according to some embodiments.

3A-3C are partial cross-sectional views of a semiconductor substrate according to some embodiments.

4A-4C are partial cross-sectional views of a semiconductor substrate according to some embodiments.

5A-5E are partial cross-sectional views of a semiconductor substrate according to some embodiments.

6A-6B are partial cross-sectional views of a semiconductor substrate according to some embodiments.

7A-7C are flow charts illustrating methods of removing nuclei formed during a selective epitaxial growth process, according to some embodiments.

8A-8B are scanning electron microscope (SEM) images of a semiconductor substrate before an etching process according to some embodiments.

9A-9B are scanning electron microscope (SEM) images of a semiconductor substrate after an etching process according to some embodiments.

Like reference numerals designate corresponding parts throughout the drawings.

Unless otherwise indicated, the accompanying drawings are not drawn to scale.

DETAILED DESCRIPTION

As explained above, the formation of undesired semiconductor structures in undesired regions (eg, on mask material) may result in poor electrical and/or mechanical properties of the semiconductor device.Certain growth conditions have been found to reduce the formation of undesired semiconductor structures in undesired regions.

For example, the substrate is exposed to an etchant (e.g., HCl gas) during epitaxial growth (e.g., by mixing HCl gas with the deposition gas), thereby allowing etching of undesired semiconductor structures during epitaxial growth. By maintaining the etching rate of the etchant above the rate at which the undesired semiconductor structure is formed and below the rate of epitaxial growth (of the target semiconductor structure), the formation of the undesired semiconductor structure is reduced or suppressed. However, the presence of the etchant affects the speed at which the epitaxially grown semiconductor structure is formed. The rate at which the target semiconductor structure is formed is hindered by the etching reaction and, therefore, is slower than the rate at which the target semiconductor structure is formed in the absence of the etchant. Thus, the reduced rate at which the target semiconductor structure is formed may become a bottleneck in the overall device manufacturing process. In addition, the presence of the etchant affects the shape of the epitaxially grown semiconductor structure. Specifically, the ratio of the growth rate in the dominant direction to the growth rate in the non-dominant direction is significantly increased. For example, in germanium epitaxial growth, (100) is the dominant growth direction. When the ratio of the growth rate in the dominant direction to the growth rate in the non-dominant direction increases, the resulting epitaxially grown germanium structure has a pyramidal shape with a (311) slope. Thus, the presence of the etchant makes it more challenging to obtain semiconductor structures with shapes other than pyramid shapes. Furthermore, if germanium is formed to have a pyramid shape with a (311) slope to cover certain areas, the height of the germanium pyramid may be high, which makes it more challenging to obtain a planarized surface (e.g., by using a chemical mechanical planarization (CMP) process).

In another embodiment, reducing the temperature and pressure during epitaxial growth is believed to reduce the formation of undesirable semiconductor structures during epitaxial growth. However, reducing the deposition temperature reduces the crystallinity of the grown semiconductor structure, which leads to increased leakage current in the semiconductor device. Reducing the pressure may result in a lower deposition rate and increase the roughness of the semiconductor structure, which may degrade the performance of the fabricated device.

In yet another example, increasing the pressure of germane gas (GeH ₄ ) favors the growth of planar germanium islands but increases the formation of undesirable semiconductor structures during epitaxial growth. Similarly, increasing the pressure of hydrogen gas (H ₂ ) favors the growth of planar germanium islands but increases the formation of undesirable semiconductor structures during epitaxial growth.

This paper describes the method for solving the above problems. By not using (or using less) etchant to epitaxially grow semiconductor structure, semiconductor structure can be grown faster. In addition, the shape of the semiconductor structure is less affected by the etchant, because there is no (or less) etchant during the epitaxial growth. In addition, during the epitaxial growth, pressure and/or temperature do not need to be reduced. Although the epitaxial growth without (or using less) etchant (and under normal pressure and temperature) will lead to the formation of the semiconductor structure on the undesirable area (for example, on the mask material), such semiconductor structure on the undesirable area is removed by etching process afterwards. Thus, the epitaxially grown semiconductor structure in the target area of the substrate can be obtained, and there is no or reduced semiconductor structure in the undesirable area.

Reference will now be made to certain embodiments, examples of which are illustrated in the accompanying drawings. While the underlying principles will be described in conjunction with these embodiments, it should be understood that this is not intended to limit the scope of the claims to only these specific embodiments. On the contrary, the claims are intended to cover alternatives, modifications, and equivalents within the scope of the claims.

Furthermore, in the following description, numerous specific details are set forth to provide a thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention can be practiced without these specific details. In other instances, methods, processes, components, and networks well known to those skilled in the art are not described in detail to avoid obscuring aspects of the underlying principles.

It should also be understood that the terms first, second, etc. may be used herein to describe various elements, but these elements should not be limited by these terms. These terms are only used to distinguish between elements. For example, a first set can be referred to as a second set, and similarly, a second set can be referred to as a first set without departing from the scope of the claims. The first set and the second set are both sets (e.g., a set of semiconductor structures), but they are not the same set.

The terms used in the specific embodiments of this article are only for the purpose of describing specific embodiments and are not intended to limit the scope of the claims. As used in the specification and the appended claims, the singular forms "a", "an", and "the" are intended to also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "and/or" used in this article refer to and include any and all possible combinations of one or more of the associated enumerated items. It should also be understood that when used in this article, the terms "include" and/or "comprising" specify the presence of the described features, integers, steps, operations, elements, and/or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts, and/or combinations thereof.

1A-1I are partial cross-sectional views of a semiconductor substrate according to some embodiments.

FIG1A illustrates a substrate 102 and a mask layer 104 on the substrate 102. Although the substrate 102 is shown as a wafer in FIG1A-1I, 2A-2C, 3A-3C, 4A-4C, and 5A-5E, the substrate 102 may include additional features not shown in FIG1A-1I, 2A-2C, 3A-3C, 4A-4C, and 5A-5E. In some embodiments, the substrate 102 includes a silicon device (e.g., a silicon complementary metal oxide semiconductor device and any other structures typically formed during front-end-of-line (FEOL) processing). In some embodiments, the substrate 102 includes an oxide layer on the silicon device (e.g., FIG6A-6B).

In some embodiments, mask layer 104 comprises a dielectric material (e.g., silicon dioxide). In some embodiments, mask layer 104 is made of a dielectric material (e.g., silicon dioxide). Mask layer 104 exposes one or more portions of substrate 102. In some embodiments, the dielectric material is deposited on substrate 102 and then etched to expose one or more portions of substrate 102. In some embodiments, substrate 102 is further etched. In some cases, this further etching provides a surface more suitable for epitaxial growth.

FIG1B shows that a semiconductor structure 106 (e.g., a germanium island) is epitaxially grown. The conditions for epitaxial growth of germanium (e.g., pressure, temperature, and chemical composition) are well known and, therefore, are omitted herein for the sake of brevity. However, as explained above, the method described herein does not require the use of an etchant (e.g., HCl gas) to suppress the growth of the semiconductor structure on the mask layer 104 during epitaxial growth, although the use of an etchant is not excluded. The conditions for epitaxial growth can be adjusted to obtain a desired growth curve. Therefore, the shape of the epitaxially grown semiconductor structure can be customized.

1B also shows that semiconductor structures 108 (eg, particles, also referred to herein as nuclei) are also formed on mask layer 104 during epitaxial growth of semiconductor structure 106. Semiconductor structure 108 typically has an amorphous and/or polycrystalline structure, whereas semiconductor structure 106 has a crystalline structure.

Figure 1C shows continued growth of semiconductor structure 106. Figure 1C also shows additional semiconductor structure 108 formed on mask layer 104. Figures 8A and 8B are scanning electron microscope (SEM) images of the substrate after epitaxial growth of germanium islands, which will be described in detail below.

FIG. 1D shows that in some embodiments, the semiconductor structure 108 is polymerized to form a thin film 110 .

FIG1E shows that, optionally, an adhesive layer 112 is applied (e.g., deposited) on substrate 102. In FIG1E, adhesive layer 112 covers semiconductor structure 106 and thin film 110 on mask layer 104. In some embodiments, adhesive layer 112 is a low thermal oxide. In some embodiments, adhesive layer 112 is hexamethyldisilane (HMDS). In some embodiments, adhesive layer 112 improves adhesion between epitaxially grown semiconductor structure 106 and photoresist.

1F shows that a protective layer 114 (e.g., a photoresist layer) is applied to substrate 102. In FIG1F , protective layer 114 covers a portion of adhesion layer 112 on semiconductor structure 106. In FIG1F , protective layer 114 does not cover thin film 110 (e.g., thin film 110 is exposed from protective layer 114, although thin film 110 is covered by adhesion layer 112).

1G shows that the area not covered by the protective layer 114 has been etched. As a result of the etching, the thin film 110 (and any other undesirable semiconductor structures formed during the epitaxial growth of the semiconductor structure 106) is removed. In addition, a portion of the bonding layer 112 located on the thin film 110 is also removed. In some embodiments, a selective etching process is used that removes the thin film 110 (and any other undesirable semiconductor structures formed during the epitaxial growth of the semiconductor structure 106) faster than the protective layer 114 (such an etching process is referred to as having high selectivity) so that when the thin film 110 and/or any other undesirable semiconductor structures formed during the epitaxial growth of the semiconductor structure 106 are removed, the semiconductor structure 106 is retained. In some embodiments, the etching process is a dry etching process (e.g., plasma etching, deep reactive ion etching, etc.). In some embodiments, the etching process is a wet etching process (e.g., etching using a liquid etchant). For example, advanced silicon etching equipment manufactured by Surface Technology Systems can be used for selective etching.

Figure 1H shows that the protective layer 114 and the bonding layer 112 are removed. Figures 9A and 9B are scanning electron microscope (SEM) images of the substrate after the protective layer 114 is removed, which will be described in detail below.

FIG1I shows that the semiconductor structure 106 has been planarized (e.g., using a CMP process). Since undesirable semiconductor structures (e.g., core 108 or thin film 110) have already been removed, the CMP process can be easily applied. Furthermore, since the shape of the semiconductor structure 106 can be adjusted to have a flat top, the CMP process is more easily performed.

2A-2C are partial cross-sectional views of a semiconductor substrate according to some embodiments.

2A-2C are similar to those shown in FIG1F-1H, except that the optional adhesion layer 112 (FIG. IE) is not used. FIG2A shows that the protective layer 114 is applied directly on the semiconductor structure 106 shown in FIG1D.

2B shows that the areas not covered by protective layer 114 have been etched, similar to the process described above with reference to FIG 1 G. As a result of the etching, thin film 110 (and any other undesirable semiconductor structures formed during the epitaxial growth of semiconductor structure 106) are removed.

Figure 2C shows that the protective layer 114 is removed, which is similar to the process described above with reference to Figure 1H. Next, the semiconductor structure 106 can be planarized, as described above with reference to Figure 1I.

3A-3C are partial cross-sectional views of a semiconductor substrate according to some embodiments.

The processes illustrated in Figures 3A-3C are similar to those illustrated in Figures 1E-1G, except that the semiconductor structures 108 (eg, particles) remain separate.

FIG. 3A shows adhesion layer 112 being applied over semiconductor structure 106 and semiconductor structure 108 (eg, particles) over mask layer 104 , similar to the process described above with reference to FIG. 1E .

FIG. 3B shows a protective layer 114 being applied to the substrate 102 , similar to the process described above with reference to FIG. 1F .

3C shows that the area not covered by the protective layer 114 has been removed, which is similar to the process described above with reference to FIG1G. As a result of the etching, the semiconductor structure 108 is removed. In addition, the portion of the bonding layer 112 located on the semiconductor structure 108 is also removed.

3C is further processed as described above with reference to FIG1H and 11. For example, protective layer 114 and adhesive layer 112 are removed and semiconductor structure 106 is planarized to obtain the semiconductor substrate shown in FIG1I.

4A-4C are partial cross-sectional views of a semiconductor substrate according to some embodiments.

The processes illustrated in Figures 4A-4C are similar to those illustrated in Figures 2A-2C, except that the semiconductor structures 108 (eg, particles) remain separate.

FIG. 4A shows that the protective layer 114 is applied directly onto the semiconductor structure 106 before the semiconductor structure 108 is polymerized.

Figure 4B shows that the areas not covered by the protective layer 114 have been etched, similar to the process described above with reference to Figure 2B. As a result of the etching, the semiconductor structure 108 is removed.

Figure 4C shows that the protective layer 114 is removed, which is similar to the process described above with reference to Figure 2C. Next, the semiconductor structure 106 can be planarized, as described above with reference to Figure 1I.

5A-5E are partial cross-sectional views of a semiconductor substrate according to some embodiments.

5A-5E illustrate that the process shown in FIG. 1A-1I can be performed to form multiple semiconductor structures (eg, germanium islands) on a single semiconductor substrate.

FIG. 5A shows that semiconductor structure 106 is epitaxially grown and semiconductor structure 108 is formed on mask layer 104 .

FIG. 5B shows that a protective layer 114 is applied over the semiconductor structure 106 while exposing the semiconductor structure 108 .

FIG. 5C shows that the semiconductor structure 108 is removed by etching.

FIG. 5D shows that the protective layer 114 is removed.

FIG. 5E shows that the semiconductor structure 106 is planarized (eg, using a CMP process).

Certain features described with reference to Figures 1A-1I, 2A-2C, 3A-3C, and 4A-4C may be similarly applied to the process shown in Figures 5A-5E. For example, before the protective layer 114 is applied (or formed) on the semiconductor structure 106, the bonding layer 112 may be applied on the semiconductor structure 106. For the sake of brevity, such details are not repeated herein.

6A-6B are partial cross-sectional views of a semiconductor substrate according to some embodiments.

FIG6A shows a substrate 102 including a complementary metal oxide semiconductor (CMOS) device having a source/drain 602 and a gate 604. In FIG6A , a mask layer 606 (e.g., silicon dioxide) is formed on the substrate 102. In some embodiments, the mask layer 606 includes silicon dioxide having a thickness of at least 2 μm for growing a germanium layer thereon. This thickness of silicon dioxide has been found to improve the crystalline quality of epitaxially grown germanium.

6B illustrates the formation of a semiconductor structure 608 (eg, germanium) using the process described above with reference to FIGS. 1A-1I , 2A- 2C, 3A- 3C, 4A- 4C, and 5A- 5E.

7A-7C illustrate a method 700 of removing nuclei formed during a selective epitaxial growth process, according to some embodiments.

Method 700 includes (702) epitaxially growing a first set of one or more semiconductor structures (e.g., semiconductor structure 106 in FIG. 1B ) on a substrate (e.g., a silicon substrate) having one or more mask layers (e.g., substrate 102 having mask layer 104 in FIG. 1B ). A second set of multiple semiconductor structures (e.g., semiconductor structure 108 in FIG. 1B ) is formed on the one or more mask layers. In some embodiments, the second set of multiple semiconductor structures is formed simultaneously with the epitaxial growth of the first set of one or more semiconductor structures. In some embodiments, a first semiconductor structure in the first set of one or more semiconductor structures is larger than a second semiconductor structure in the second set of multiple semiconductor structures. In some embodiments, the one or more semiconductor structures are homoepitaxially grown. In some embodiments, the one or more semiconductor structures are heteroepitaxially grown.

In some embodiments, a first set of one or more semiconductor structures is formed in a single epitaxial growth process (704). For example, in Figures 1B-1C, semiconductor structure 106 is formed in a single epitaxial growth process (e.g., rather than epitaxially growing a portion of semiconductor structure 106, etching a portion of semiconductor structure 106 and epitaxially growing an additional portion of semiconductor structure 106).

In some embodiments, method 700 includes forming a plurality of semiconductor grains (e.g., semiconductor structure 108 in FIG. 1C ) on one or more mask layers (e.g., mask layer 104 in FIG. 1C ) while epitaxially growing a first set of one or more semiconductor structures (e.g., semiconductor structure 106 in FIG. 1C ) on a substrate having one or more mask layers (e.g., mask layer 104 in FIG. 1C ). In some embodiments, the second set of the plurality of semiconductor structures includes a plurality of semiconductor grains.

In some embodiments, the second set of the plurality of semiconductor structures includes (708) a semiconductor thin film (e.g., semiconductor thin film 110 in FIG. 1D ) on one or more mask layers. In some embodiments, the second set of the plurality of semiconductor structures includes one or more semiconductor thin films on one or more mask layers.

In some embodiments, the first set of one or more semiconductor structures includes (710) Group IV materials (e.g., silicon, germanium, SiGe, etc.) In some embodiments, the first set of one or more semiconductor structures includes one or more Group III-V materials (e.g., GaAs, InGaAs, etc.).

In some embodiments, the first set of one or more semiconductor structures includes (712) germanium.

In some embodiments, a first set of one or more semiconductor structures is formed (714) on one or more regions of the substrate that are exposed from (e.g., not covered by) the one or more masking layers. For example, in FIG5A , semiconductor structure 106 is formed on regions of the substrate that are exposed from masking layer 104.

In some embodiments, a first set of one or more semiconductor structures has a crystalline structure (716) and a second set of the plurality of semiconductor structures has an amorphous and/or polycrystalline structure. For example, see FIG8 , which illustrates a first set of one or more semiconductor structures (e.g., germanium islands) having a crystalline structure and a second set of semiconductor structures having an amorphous and/or polycrystalline structure.

In some embodiments, the one or more masking layers include (718) a dielectric material.

In some embodiments, the one or more masking layers include (720) silicon dioxide.

Method 700 also includes (722, FIG. 7B) forming one or more protective layers (e.g., protective layer 114 in FIG. 1F, such as one or more photoresist layers) on the first set of one or more semiconductor structures. At least a subset of the second set of the plurality of semiconductor structures is exposed from the one or more protective layers. For example, in FIG. 1F, thin film 110 is exposed from protective layer 114. In some embodiments, the one or more protective layers are in direct contact with the first set of one or more semiconductor structures (e.g., FIG. 2A). In some embodiments, one or more intermediate layers (e.g., one or more adhesion layers, such as hexamethyldisilane (HMDS) or a low-temperature thermal oxide) are located between the first set of one or more semiconductor structures and the one or more protective layers (e.g., FIG. 1F).

In some embodiments, method 700 includes (724) forgoing etching of at least a subset of the second set of the plurality of semiconductor structures before one or more protective layers are formed on the first set of the one or more semiconductor structures. For example, in some embodiments, the second set of the plurality of semiconductor structures is not etched until after one or more protective layers are formed on the one or more semiconductor structures to protect the one or more semiconductor structures from the etching process.

In some embodiments, the method 700 includes (726) abandoning etching of at least a subset of the second set of the plurality of semiconductor structures after initiating epitaxial growth of the first set of one or more semiconductor structures on the substrate until one or more protective layers are formed on the first set of one or more semiconductor structures. For example, the etching of at least a subset of the second set of the plurality of semiconductor structures is abandoned during the epitaxial growth of the first set of one or more semiconductor structures. In some embodiments, the etching of at least a subset of the plurality of semiconductor structures is abandoned after initiating epitaxial growth of the first set of one or more semiconductor structures on the substrate and before forming one or more protective layers on the one or more semiconductor structures.

In some embodiments, the one or more protective layers include (728) one or more photoresist layers. In some embodiments, the one or more protective layers are one or more photoresist layers.

In some embodiments, method 700 includes (730) depositing one or more adhesion layers on at least a first set of one or more semiconductor structures before forming the one or more protective layers. For example, as shown in Figures 1E-1F, adhesion layer 112 is applied to semiconductor structure 106 before protective layer 114 is applied. In some embodiments, the one or more adhesion layers are deposited on at least the first set of one or more semiconductor structures.

In some embodiments, the one or more bonding layers include (732) hexamethyldisilane and/or low temperature thermal oxide.

In some embodiments, the method includes, after etching at least a subset of the second set of the plurality of semiconductor structures, removing the one or more bonding layers. In some embodiments, the one or more protective layers and the one or more bonding layers are removed simultaneously. In some embodiments, the one or more protective layers are removed after removing the one or more bonding layers.

In some embodiments, the substrate comprises silicon. In some embodiments, the substrate is a silicon substrate.

In some embodiments, the substrate includes (734) a plurality of semiconductor devices thereon (eg, Figures 6A-6B). For example, prior to epitaxially growing the first set of one or more semiconductor structures, the substrate may include a plurality of transistors.

In some embodiments, the substrate includes a plurality of transistors and a semiconductor structure in the first set of one or more semiconductor structures is electrically coupled to a source or a drain of a transistor in the plurality of transistors.

In some embodiments, the substrate includes (736) a plurality of complementary metal oxide semiconductor (CMOS) devices thereon (eg, Figures 6A-6B).

In some embodiments, the substrate includes a plurality of complementary metal oxide semiconductor devices thereon, including p-type metal oxide semiconductor transistors and n-type metal oxide semiconductor transistors. In some embodiments, the method includes electrically coupling a semiconductor structure from a first set of one or more semiconductor structures to a source or drain of one of the p-type metal oxide semiconductor transistor or the n-type metal oxide semiconductor transistor.

In some embodiments, a plurality of semiconductor devices are located on the substrate beneath one or more mask layers (738). For example, in Figures 6A-6B, semiconductor devices (e.g., transistors) are located beneath mask layer 606. In some embodiments, the plurality of semiconductor devices are located in a front-end-of-line (FEOL) region of the substrate.

Method 700 also includes (740, FIG. 7C ), after forming the one or more protective layers on the first set of one or more semiconductor structures, etching at least a subset of the second set of the plurality of semiconductor structures. For example, in FIG. 1F-1G , thin film 110 is removed as a result of the etching process. In some embodiments, at least a subset of the plurality of semiconductor structures exposed from the one or more photoresist layers is completely etched (e.g., removed). In some embodiments, at least a subset of the plurality of semiconductor structures exposed from the one or more photoresist layers is at least partially etched (e.g., removed). In some embodiments, one or more semiconductor structures of at least a subset of the plurality of semiconductor structures exposed from the one or more photoresist layers are etched (e.g., removed). In some embodiments, the entire second set of the plurality of semiconductor structures formed on the one or more masking layers is etched (e.g., removed).

In some embodiments, the method includes etching an entire subset of the second set of the plurality of semiconductor structures exposed from the one or more protective layers.

In some embodiments, method 700 includes (742), after etching at least a subset of the second set of the plurality of semiconductor structures, removing one or more protective layers (e.g., FIG. 1H ) and/or planarizing at least a subset of the first set of the one or more semiconductor structures (e.g., using chemical mechanical planarization). In some embodiments, method 700 includes removing one or more protective layers after etching at least a subset of the second set of the plurality of semiconductor structures. In some embodiments, method 700 includes planarizing at least a subset of the first set of the one or more semiconductor structures after etching at least a subset of the second set of the plurality of semiconductor structures. For example, in FIG. 1I , semiconductor structure 106 is planarized.

In some embodiments, etching at least a subset of the second set of the plurality of semiconductor structures includes (744) etching the at least a subset of the second set of the plurality of semiconductor structures at a first rate and etching the one or more mask layers at a second rate that is lower than the first rate. For example, in Figures 1F-1G, thin film 110 is etched faster than mask layer 104 and protective layer 114. In some embodiments, etching at least a subset of the second set of the plurality of semiconductor structures includes etching the at least a subset of the second set of the plurality of semiconductor structures without etching the one or more mask layers. In some embodiments, thin film 110 shown in Figure 1F is etched without etching mask layer 104 and protective layer 114.

In some embodiments, etching at least a subset of the second set of the plurality of semiconductor structures includes forgoing etching one or more masking layers.

In some embodiments, etching at least a subset of the second set of the plurality of semiconductor structures includes (744) etching at least a subset of the second set of the plurality of semiconductor structures at a first rate and etching at least a subset of the first set of one or more semiconductor structures at a third rate that is lower than the first rate. For example, in Figures 1F-1G, thin film 110 is etched faster than semiconductor structure 106. In some embodiments, etching at least a subset of the second set of the plurality of semiconductor structures includes etching at least a subset of the second set of the plurality of semiconductor structures without etching the first set of one or more semiconductor structures. In some embodiments, thin film 110 shown in Figure 1F is etched while semiconductor structure 106 is not etched (for example, because semiconductor structure 106 is protected by protective layer 114).

Certain features of the method 700 described with reference to Figures 7A-7C may be applied to the processes shown in Figures 1A-1I, 2A-2C, 3A-3C, 4A-4C, 5A-5E, and 6A-6B. For the sake of brevity, these details are not repeated.

8A-8B are scanning electron microscope (SEM) images of a semiconductor substrate before an etching process according to some embodiments.

8A and 8B are top views of the semiconductor substrate corresponding to FIG. 1C .

Figure 8A shows a germanium island corresponding to the semiconductor structure 106 in Figure 1C (before the etching process).In addition, a second set of semiconductor structures are formed around the germanium island on the mask layer.

Figure 8B is a zoomed-out view of the semiconductor substrate. Figure 8B shows a plurality of germanium islands and a second set of semiconductor structures formed on the mask layer.

9A-9B are scanning electron microscope (SEM) images of a semiconductor substrate after an etching process according to some embodiments.

Figure 9A is a germanium island corresponding to the semiconductor structure 106 in Figure 1H (after the etching process). Figure 9A shows a second set of germanium islands on the mask layer without semiconductor structures surrounding them.

Figure 9B is a zoomed-out view of the semiconductor substrate. Figure 9B shows the plurality of germanium islands without the second set of semiconductor structures.

9A-9B illustrate the effectiveness of the described method in removing a second set of semiconductor structures formed on one or more masking layers.

For the purpose of explanation, the foregoing has been described with reference to specific embodiments. However, the exemplary discussion above is not intended to be exhaustive of the present invention or to limit the present invention to the precise form disclosed. In light of the above teachings, many modifications and variations are possible. The embodiments have been selected and described in order to better explain the principles of the present invention and its practical application, thereby enabling other persons skilled in the art to better utilize the present invention and the various embodiments, and to make various modifications suitable for the specific use under consideration.

Claims (29)

1. A method for removing nuclei formed during a selective epitaxial growth process, comprising: A first set of one or more semiconductor structures is epitaxially grown on a substrate having one or more mask layers, wherein a second set of multiple semiconductor structures is formed on one or more mask layers; One or more protective layers are formed on a first set of one or more semiconductor structures, wherein at least a subset of a second set of the plurality of semiconductor structures is exposed from the one or more protective layers; After forming the one or more protective layers on a first set of the one or more semiconductor structures, at least one subset of a second set of the plurality of semiconductor structures is etched; and when the first set of the one or more semiconductor structures is epitaxially grown on the substrate having one or more mask layers, a plurality of semiconductor particles are formed on the one or more mask layers. 2. The method according to claim 1, comprising: Etching of at least one subset of a second set of the plurality of semiconductor structures is abandoned before the one or more protective layers are formed on the first set of the one or more semiconductor structures. 3. The method according to claim 1, comprising: After the epitaxial growth of a first set of one or more semiconductor structures on the substrate is initiated, etching of at least one subset of a second set of one or more semiconductor structures is abandoned until the one or more protective layers are formed on the first set of one or more semiconductor structures. 4. The method of claim 1, wherein the first set of the one or more semiconductor structures is formed in a single epitaxial growth process. 5. The method according to claim 1, wherein: The one or more protective layers include one or more photoresist layers. 6. The method according to claim 1, comprising: Before forming the one or more protective layers, one or more adhesive layers are deposited on at least a first set of the one or more semiconductor structures. 7. The method of claim 6, wherein the one or more adhesive layers comprise hexamethyldisilane and/or a low-temperature thermal oxide. 8. The method of claim 6, comprising: After etching at least one subset of the second set of the plurality of semiconductor structures, the one or more adhesive layers are removed. 9. The method of claim 8, wherein the one or more protective layers and the one or more adhesive layers are removed simultaneously. 10. The method of claim 8, wherein the one or more protective layers are removed after at least a portion of the one or more adhesive layers are removed. 11. The method according to claim 1, further comprising: After etching at least one subset of the second set of the plurality of semiconductor structures, the one or more protective layers are removed. 12. The method according to claim 1, further comprising: After etching at least one subset of the second set of the plurality of semiconductor structures, at least one subset of the first set of the one or more semiconductor structures is planarized. 13. The method of claim 1, wherein the second set of the plurality of semiconductor structures comprises one or more semiconductor thin films on the one or more mask layers. 14. The method of claim 1, wherein the first set of the one or more semiconductor structures comprises group IV materials. 15. The method of claim 1, wherein the first set of the one or more semiconductor structures comprises germanium. 16. The method of claim 1, wherein a first set of the one or more semiconductor structures is formed on one or more regions of the substrate exposed from the one or more mask layers. 17. The method of claim 1, wherein the first set of the one or more semiconductor structures has a crystalline structure and the second set of the plurality of semiconductor structures has an amorphous and/or polycrystalline structure. 18. The method of claim 1, wherein the one or more mask layers comprise a dielectric material. 19. The method of claim 1, wherein the one or more mask layers comprise silicon dioxide. 20. The method of claim 1, wherein etching at least one subset of the second set of the plurality of semiconductor structures comprises etching at least one subset of the second set of the plurality of semiconductor structures at a first rate and etching the one or more mask layers at a second rate lower than the first rate. 21. The method of claim 1, wherein etching at least a subset of the second set of the plurality of semiconductor structures comprises abandoning the etching of the one or more mask layers. 22. The method of claim 1, wherein the substrate comprises a plurality of semiconductor devices thereon. 23. The method of claim 22, wherein the plurality of semiconductor devices are located on the substrate beneath the one or more mask layers. 24. The method of claim 22, wherein the substrate includes a plurality of transistors thereon and a semiconductor structure in a first set of the one or more semiconductor structures is electrically coupled to a source or drain of a transistor in the plurality of transistors. 25. The method of claim 24, wherein the substrate comprises a plurality of complementary metal-oxide-semiconductor devices thereon, including p-type metal-oxide-semiconductor transistors and n-type metal-oxide-semiconductor transistors. 26. The method of claim 25, comprising: A first semiconductor structure in a first set of one or more semiconductor structures is electrically coupled to a source or drain of one of the following: a p-type metal-oxide-semiconductor transistor or an n-type metal-oxide-semiconductor transistor. 27. The method of claim 1, wherein the first set of the one or more semiconductor structures and the second set of the plurality of semiconductor structures are formed simultaneously. 28. The method of claim 1, wherein a first semiconductor structure in a first set of one or more semiconductor structures is larger than a second semiconductor structure in a second set of one or more semiconductor structures. 29. The method according to claim 1, comprising: The entire subset of the second set of the plurality of semiconductor structures exposed from the one or more protective layers is etched.