HK1237119B - Laminated ceramic capacitor - Google Patents

Description

Multilayer ceramic capacitors

Technical Field

The present invention relates to a multilayer ceramic capacitor having substantially L-shaped external electrodes provided at opposing end portions of a capacitor body.

Background Art

As a form of external electrodes provided at opposite ends of a multilayer ceramic capacitor, there is known a generally L-shaped external electrode having a portion along one surface in the length direction of the capacitor body and a portion along one surface in the height direction (see Patent Document 1 mentioned below). The multilayer ceramic capacitor disclosed in Patent Document 1 mentioned below (hereinafter referred to as the conventional multilayer ceramic capacitor) includes: a capacitor body having a first surface and a second surface opposite to each other in the length direction, a third surface and a fourth surface opposite to each other in the width direction, and a fifth surface and a sixth surface opposite to each other in the height direction; a generally L-shaped first external electrode having a first portion along the first surface of the capacitor body and a second portion along the fifth surface; and a generally L-shaped second external electrode having a first portion along the second surface of the capacitor body and a second portion along the fifth surface. A capacitor portion formed by stacking a plurality of first internal electrode layers and a plurality of second internal electrode layers with a dielectric layer interposed therebetween is built into the capacitor body. The end edges of the plurality of first internal electrode layers are connected to the first portion of the first external electrode. Furthermore, the end edges of the plurality of second internal electrode layers are connected to the first portion of the second external electrode.

In conventional multilayer ceramic capacitors, the first and second external electrodes are each substantially L-shaped, lacking a portion along the sixth surface of the capacitor body, a portion along the third surface, or a portion along the fourth surface. Therefore, compared to a multilayer ceramic capacitor of the same external dimensions (length, width, and height) using a U-shaped external electrode having a portion along the sixth surface, the height dimension of the capacitor body can be designed to be larger by an amount corresponding to the thickness of the portion along the sixth surface. Furthermore, compared to a multilayer ceramic capacitor of the same external dimensions using a bottomed, rectangular cylindrical external electrode having a portion along the sixth surface, a portion along the third surface, and a portion along the fourth surface, the height and width dimensions of the capacitor body can be designed to be larger by an amount corresponding to the thickness of the portion along the sixth surface, the portion along the third surface, and the portion along the fourth surface, respectively. In other words, the increase in the number and area of the internal electrode layers due to the increased size of the capacitor body can contribute to an increase in capacitance.

Regarding the increase in capacitance described above, attempts were made to use high-dielectric-constant dielectric ceramics with a high relative dielectric constant as the material for the capacitor body, excluding the first and second internal electrode layers. However, the use of high-dielectric-constant dielectric ceramics deteriorated the DC bias characteristics of the multilayer ceramic capacitor itself, significantly reducing the effective capacitance when a DC voltage higher than the rated voltage was applied.

Prior art literature

Patent Literature

Patent Document 1: Japanese Patent Application Laid-Open No. 2015-228481

Summary of the Invention

The technical problem that the invention aims to solve

An object of the present invention is to provide a multilayer ceramic capacitor that does not compromise the benefit of increased capacitance and can suppress deterioration of DC bias characteristics even when a high-dielectric-constant dielectric ceramic is used to further increase capacitance.

Technical solutions to technical problems

In order to solve the above-mentioned problems, the multilayer ceramic capacitor of the present invention is characterized in that it comprises: (1) a capacitor body comprising: a first surface and a second surface opposite to each other in the length direction; a third surface and a fourth surface opposite to each other in the width direction; and a fifth surface and a sixth surface opposite to each other in the height direction, and having a built-in capacitor portion in which a plurality of first internal electrode layers and a plurality of second internal electrode layers are stacked with dielectric layers therebetween; (2) a first external electrode having a first portion along the first surface of the capacitor body and a second portion along the fifth surface, the first portion of the first external electrode being connected to the plurality of first internal electrode layers and the second internal electrode layers. and (3) a second external electrode having a first portion along the second surface of the capacitor body and a second portion along the fifth surface, wherein the first portion of the second external electrode is connected to the end edges of the plurality of second internal electrode layers, the first surface of the capacitor body is concave, the first portion of the first external electrode is in contact with the first surface of the capacitor body, the second surface of the capacitor body is concave, and the first portion of the second external electrode is in contact with the second surface of the capacitor body.

Effects of the Invention

According to the present invention, a multilayer ceramic capacitor can be provided that does not lose the advantage of increased capacitance and can suppress deterioration of DC bias characteristics even when a high-dielectric-constant dielectric ceramic is used to further increase capacitance.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a diagram showing a multilayer ceramic capacitor according to the present invention as viewed from the sixth surface f6 of the capacitor body.

FIG. 2 is a cross-sectional view taken along line S1 - S1 in FIG. 1 .

FIG3 is a cross-sectional view taken along line S2 - S2 of FIG1 .

FIG. 4 is a diagram showing conditions and characteristics of evaluation samples.

Description of Reference Numerals

10…multilayer ceramic capacitor; 11…capacitor body; f1…first surface of the concave shape of the capacitor body; f2…second surface of the concave shape of the capacitor body; Dmax…maximum lengthwise dimension between the first surface of the concave shape and the second surface of the concave shape of the capacitor body; Dmin…minimum lengthwise dimension between the first surface of the concave shape and the second surface of the concave shape of the capacitor body; f3…third surface of the planar shape of the capacitor body; f4…fourth surface of the planar shape of the capacitor body; f5…fifth surface of the planar shape of the capacitor body, f6…sixth surface of the planar shape of the capacitor body; 12…first external electrode; 12a…first portion of the first external electrode; 12b…second portion of the first external electrode; 13…second external electrode; 13a…first portion of the second external electrode; 13b…second portion of the second external electrode.

DETAILED DESCRIPTION

First, the structure of a multilayer ceramic capacitor 10 according to the present invention will be described using FIG. 1 to FIG. 3 .

The dimensions of the multilayer ceramic capacitor 10 are defined by a length L, a width W, and a height H. The multilayer ceramic capacitor 10 includes a substantially rectangular parallelepiped capacitor body 11 , a substantially L-shaped first external electrode 12 , and a substantially L-shaped second external electrode 13 .

The capacitor body 11 includes: a first surface f1 and a second surface f2 that are opposite to each other in the length direction; a third surface f3 and a fourth surface f4 that are opposite to each other in the width direction; and a fifth surface f5 and a sixth surface f6 that are opposite to each other in the height direction. Furthermore, a capacitor portion (reference numerals omitted) is built into the capacitor body 11 and is formed by alternating stacking of a plurality of first internal electrode layers 14 and a plurality of second internal electrode layers 15 with dielectric layers 16 interposed therebetween. Both sides of the width direction and both sides of the height direction of the capacitor portion are covered by edge portions (reference numerals omitted) formed by dielectrics. Specifically, the outline of each first internal electrode layer 14 and the outline of each second internal electrode layer 15 are rectangular, the outline size and thickness of each first internal electrode layer 14 are substantially the same as the outline size and thickness of each second internal electrode layer 15, and the thickness of each dielectric layer 16 is substantially the same.

One end portion in the longitudinal direction of each first internal electrode layer 14 (the left end portion in FIG. 2 ) forms a lead portion 14a. The end edge of each lead portion 14a is led to the first surface f1 of the capacitor body 11, and each end edge is connected to the first portion 12a of the first external electrode 12. Furthermore, one end portion in the longitudinal direction of each second internal electrode layer 15 (the right end portion in FIG. 2 ) forms a lead portion 15a. The end edge of each lead portion 15a is led to the second surface f2 of the capacitor body 11, and each end edge is connected to the first portion 13a of the second external electrode 13.

The third surface f3, the fourth surface f4, the fifth surface f5, and the sixth surface f6 of the capacitor body 11 are respectively substantially flat plane shapes, but the first surface f1 and the second surface f2 are respectively concave shapes with depth. This "concave shape" is a shape with increasing depth toward the center or near the center, and the surface itself can be uneven or smooth. Dmax and Dmin in Figure 2 are dimensions that replace the specifications for the "concave shape". Dmax represents the maximum length direction dimension (maximum length direction dimension) between the first surface f1 of the concave shape and the second surface f2 of the concave shape, specifically the maximum length direction dimension presented between the edge of the first surface f1 and the edge of the second surface f2. Dmin represents the minimum length direction dimension (minimum length direction dimension) between the first surface f1 of the concave shape and the second surface f2 of the concave shape, specifically the minimum length direction dimension presented between the deepest part of the first surface f1 and the deepest part of the second surface f2. In addition, it is preferred that the maximum depth of the first surface f1 of the concave shape is approximately the same as the maximum depth of the second surface f2 of the concave shape, but they are not necessarily approximately the same. In addition, it is preferred that the specifications of the first surface f1 of the concave shape are approximately the same as the specifications of the second surface f2 of the concave shape, but they are not necessarily approximately the same.

The first external electrode 12 has a generally L-shaped structure, comprising a first portion 12a extending along the concave first surface f1 of the capacitor body 11, and a second portion 12b extending along the planar fifth surface f5. The first portion 12a is in close contact with the concave first surface f1, while the second portion 12b is in close contact with the planar fifth surface f5. Furthermore, the second external electrode 13 has a generally L-shaped structure, comprising a first portion 13a extending along the concave second surface f2 of the capacitor body 11, and a second portion 13b extending along the planar fifth surface f5. The first portion 13a is in close contact with the concave second surface f2, while the second portion 13b is in close contact with the planar fifth surface f5.

Furthermore, the thickness of the first portion 12a of the first external electrode 12 is greater than the maximum depth of the concave first surface f1 of the capacitor body 11, and the thickness of the first portion 13a of the second external electrode 13 is greater than the maximum depth of the concave second surface f1 of the capacitor body 11. Therefore, when the capacitor body 11 is viewed from the sixth surface f6, the first portion 12a of the first external electrode 12 and the first portion 13a of the second external electrode 13 each protrude outward from the capacitor body 11. While the thickness of the protruding portion of the first portion 12a of the first external electrode 12 and the thickness of the protruding portion of the first portion 13a of the second external electrode 13 are preferably approximately the same, they are not necessarily the same. Furthermore, the thickness and longitudinal dimension of the second portion 12b of the first external electrode 12 are approximately the same as the thickness and longitudinal dimension of the second portion 13b of the second external electrode 13.

Although not shown in the figure, the first external electrode 12 has a two-layer structure including a base film that is in close contact with the concave first surface f1 and the flat fifth surface f5 of the capacitor body 11, and a surface film that is in close contact with the outer surface of the base film, or a multilayer structure including at least one intermediate film between the base film and the surface film. Furthermore, the second external electrode 13 has a two-layer structure including a base film that is in close contact with the concave second surface f2 and the flat fifth surface f5 of the capacitor body 11, and a surface film that is in close contact with the outer surface of the base film, or a multilayer structure including at least one intermediate film between the base film and the surface film.

As a supplementary explanation of the material of the capacitor body 11, the portion of the capacitor body 11 other than the first internal electrode layer 14 and the second internal electrode layer 15 can preferably use a high dielectric constant dielectric ceramic whose main components are barium titanate, strontium titanate, calcium titanate, magnesium titanate, calcium zirconate, calcium zirconate titanate, barium zirconate, titanium oxide, etc., and more preferably use a high dielectric constant dielectric ceramic with a relative dielectric constant of 1000 or more.

To supplementally explain the material of each first internal electrode layer 14 and each second internal electrode layer 15 , each first internal electrode layer 14 and each second internal electrode layer 15 can preferably use a good conductor mainly composed of nickel, copper, palladium, platinum, silver, gold, or alloys thereof.

The materials and manufacturing methods of the base films of the first and second external electrodes 12, 13 are supplementally explained. The base films of the first and second external electrodes 12, 13 are, for example, formed of a baked film or a plated film. A good conductor primarily composed of nickel, copper, palladium, platinum, silver, gold, or alloys thereof can be used for the base films. The surface films are, for example, formed of a plated film. A good conductor primarily composed of copper, tin, palladium, gold, zinc, or alloys thereof can be used for the surface films. The intermediate films are, for example, formed of a plated film. A good conductor primarily composed of platinum, palladium, gold, copper, nickel, or alloys thereof can be used for the intermediate films.

1 to 3 illustrate a multilayer ceramic capacitor 10 having a length L, a width W, and a height H, respectively, such that length L > width W = height H. However, the relationship between length L, width W, and height H may be such that width W > length L = height H, width W > length L > height H, or width W > height H > length L, in addition to length L > width W > height H and length L > height H > width W. Furthermore, although the first and second internal electrode layers 14 and 15 are each depicted as having seven layers, and the dielectric layers 16 are depicted as having 13 layers, this is for illustration purposes only. The number of first and second internal electrode layers 14 and 15 may each be 8 or more (the number of dielectric layers 16 may be 15 or more), or 6 or less (the number of dielectric layers 16 may be 11 or less).

Next, an example of a manufacturing method applicable to the above-mentioned multilayer ceramic capacitor 10 will be described, citing reference numerals in FIG. 1 to FIG. 3 as appropriate.

During production, a ceramic slurry containing dielectric ceramic powder, a first electrode paste containing good conductor powder, and a second electrode paste containing good conductor powder and a common material (the same dielectric ceramic powder as the dielectric ceramic powder contained in the ceramic slurry) are prepared. The ceramic slurry is then applied to the surface of a carrier film and dried to produce a first green sheet. Separately, the first electrode paste is printed on the surface of the first green sheet and dried to produce a second green sheet with an internal electrode pattern set formed thereon, serving as a precursor for the first and second internal electrode layers 14 and 15.

Next, the lamination hot pressing operation is repeated until the number of unit sheets taken out from the first green sheet reaches a predetermined number, and a portion corresponding to the edge portion on one side in the height direction is produced. Furthermore, the lamination hot pressing operation is repeated until the number of unit sheets (including the internal electrode pattern group) taken out from the second green sheet reaches a predetermined number, and a portion corresponding to the capacitor portion is produced. Furthermore, the lamination hot pressing operation is repeated until the number of unit sheets taken out from the first green sheet reaches a predetermined number, and a portion corresponding to the edge portion on the other side in the height direction is produced. Finally, the entire laminate is formally hot pressed to produce an unfired laminate.

Next, the unfired laminated sheet is cut into a grid pattern to produce unfired chips. Next, the second electrode paste is impregnated onto both longitudinal surfaces of the unfired chips and dried, and the second electrode paste is printed onto one height surface of the unfired chips and dried, thereby producing unfired base films corresponding to the base films of the first external electrode 12 and the second external electrode 13.

Next, multiple unfired chips, each having an unfired base film formed thereon, are collectively fired (including a debindering process and firing process) in an atmosphere corresponding to the dielectric ceramic powder contained in the ceramic slurry and the good conductor powder contained in the first and second electrode pastes, according to a temperature profile. A secondary firing (reoxidation process) is performed as needed to produce fired chips. Subsequently, the multiple fired chips are collectively barrel-polished (polished) to round off corners and edges, thereby producing capacitor body 11.

The two longitudinal surfaces of the unfired chip obtained in the above-mentioned unfired chip manufacturing process are respectively substantially flat plane shapes. However, the unfired base film formed on the two longitudinal surfaces of the unfired chip in the above-mentioned unfired base film manufacturing process contains a common material, and no unfired base film is formed on the two width-direction surfaces and the other height-direction surface of the unfired chip. Therefore, in the above-mentioned fired chip manufacturing process, depending on the content of the common material contained in the unfired base film, a force CF is applied to compress the two longitudinal surfaces of the unfired chip inward in the width direction (see FIG. 1 ) and a force CF is applied to compress the two longitudinal surfaces of the unfired chip inward in the height direction (see FIG. 2 ). Based on these compressive forces, the two longitudinal surfaces of the unfired chip are respectively shaped into concave shapes.

In addition, the common material contained in the unfired base film (here, the same dielectric ceramic powder as the dielectric ceramic powder contained in the above-mentioned ceramic slurry) produces the above-mentioned effect, but the same shaping as above can be achieved by using a material having a thermal expansion coefficient similar to that of the common material instead of the above-mentioned common material, for example, another type of dielectric ceramic powder having a thermal expansion coefficient similar to that of the dielectric ceramic powder contained in the above-mentioned ceramic slurry, or glass powder having a thermal expansion coefficient similar to that of the dielectric ceramic powder contained in the above-mentioned ceramic slurry.

Next, a surface film, or an intermediate film and a surface film covering each base film of the fired chip is formed by a wet plating method such as electrolytic plating or electroless plating, or a dry plating method such as sputtering or vacuum evaporation, thereby producing the first external electrode 12 and the second external electrode 13 respectively.

Next, conditions, characteristics, and the like of samples 1 to 12 prepared for evaluating the above-described multilayer ceramic capacitor 10 will be described using FIG. 4 .

Samples 1 to 12 were manufactured based on the above-mentioned manufacturing method. The common and different conditions for each of Samples 1 to 12 are as follows. The values listed in the common and different conditions are design reference values and do not include manufacturing tolerances.

<Common Conditions for Samples 1 to 12 (Referring to Reference Symbols in FIG. 1 to FIG. 3 )>

The rated voltage is 6.3V and the rated capacitance is 2.2μF.

The length L is 600 μm, the width W is 300 μm, and the height H is 300 μm.

The capacitor body 11 has a longitudinal dimension (corresponding to a maximum longitudinal dimension Dmax) of 520 μm, a width dimension of 300 μm, and a height dimension of 275 μm.

The main component of the portion of the capacitor body 11 excluding the first internal electrode layer 14 and the second internal electrode layer 15 is barium titanate.

The main component of the first internal electrode layer 14 and the second internal electrode layer 15 is nickel, the thickness of each is 0.5 μm, and the number of layers is 123.

The dielectric layer 16 has a thickness of 0.5 μm and a number of 245 layers.

The thickness of the capacitor body 11 at the edge portion in the width direction is 20 μm, and the thickness of the edge portion in the height direction is 15 μm.

The thickness of the protruding portion of the first portion 12a of the first external electrode 12 and the protruding portion of the first portion 13a of the second external electrode 13 are 40 μm, and the thickness of the second portion 12b of the first external electrode 12 and the second portion 13b of the second external electrode 13 are 25 μm.

The first external electrode 12 and the second external electrode 13 each have a three-layer structure, wherein the main component of the base film is copper, the main component of the intermediate film is nickel, and the main component of the surface film is tin.

<Different Conditions of Samples 1 to 12 (Referring to Reference Symbols in Figures 1 to 3 )>

The minimum longitudinal dimension Dmin of Sample 1 is 520 μm.

The minimum longitudinal dimension Dmin of Sample 2 was 515 μm.

The minimum longitudinal dimension Dmin of Sample 3 was 510 μm.

The minimum longitudinal dimension Dmin of Sample 4 was 504 μm.

The minimum longitudinal dimension Dmin of Sample 5 was 499 μm.

The minimum longitudinal dimension Dmin of Sample 6 is 494 μm.

The minimum longitudinal dimension Dmin of Sample 7 was 489 μm.

The minimum longitudinal dimension Dmin of Sample 8 was 484 μm.

The minimum longitudinal dimension Dmin of Sample 9 was 478 μm.

The minimum longitudinal dimension Dmin of the sample 10 is 473 μm.

The minimum longitudinal dimension Dmin of the sample 11 was 468 μm.

The minimum longitudinal dimension Dmin of the sample 12 was 463 μm.

The minimum longitudinal dimension Dmin of each of the samples 1 to 12 was changed by using the second electrode paste having different contents of the common material in the above-mentioned manufacturing method example.

The "Dmin/Dmax" in Figure 4 records the value obtained by dividing the minimum longitudinal dimension Dmin by the maximum longitudinal dimension Dmax for each of Samples 1 to 12. The "Capacitance Reduction Rate (%)" in Figure 4 records the effective capacitance at the time of measuring 100 samples 1 to 12 using Agilent Technologies' precision LCR meter 4284A, applying a DC voltage (7.0V) higher than the rated voltage (6.3V) to each of Samples 1 to 12, and the value obtained by subtracting the average value of the effective capacitance of each 100 samples from the rated capacitance and dividing it by the rated capacitance. In addition, the "Delamination Generation Rate (%)" in Figure 4 records the number of delaminations generated in the internal electrode layer within the capacitor body by observing the cross-section of each of Samples 1 to 12 using an optical microscope for each of Samples 1 to 12.

As can be seen from the "Capacitance Reduction (%)" values in Figure 4, the capacitance reduction rates of Samples 3 to 12 are smaller than those of Samples 1 and 2. Furthermore, the "Delamination Occurrence (%)" values in Figure 4 show that the delamination occurrence rates of Samples 3 to 11 are smaller than those of Sample 12. In other words, when the "Capacitance Reduction (%)" values in Figure 4 are taken into account, the preferred range of Dmin/Dmax is 0.90 or higher and 0.98 or lower.

Next, the effects obtained by the above-described multilayer ceramic capacitor 10 will be described.

(1) In the above-described multilayer ceramic capacitor 10, the first surface f1 of the capacitor body 11 is concave, and the first portion 12a of the first external electrode 12 is formed so as to be in close contact with the concave first surface f1. The second surface f2 of the capacitor body 11 is concave, and the first portion 13a of the second external electrode 13 is formed so as to be in close contact with the concave second surface f2. Specifically, according to this configuration, even when a high-dielectric-constant dielectric ceramic is used for portions of the capacitor body 11 other than the first internal electrode layer 14 and the second internal electrode layer 15 in order to further increase capacitance, deterioration in the DC bias characteristics of the multilayer ceramic capacitor 10 itself can be suppressed.

While the fact that the above-described structure can suppress deterioration of DC bias characteristics is more clearly demonstrated by the description above using FIG4 , the following can be inferred as the basis for this. For example, in the firing chip manufacturing process of the above-described manufacturing method, the force CF (see FIG1 ) that compresses the longitudinal surfaces of the unfired chip inward in the width direction and the force CF (see FIG2 ) that compresses the longitudinal surfaces of the unfired chip inward in the height direction remains after manufacturing. Specifically, in the multilayer ceramic capacitor 10 shown in FIG1 to FIG3 , the first external electrode 12 and the second external electrode 13 are each substantially L-shaped. Therefore, a state is created in which the force CF (see FIG1 ) that compresses the concave first surface f1 and the concave second surface f2 of the capacitor body 11 inward in the width direction and the force CF (see FIG2 ) that compresses the concave first surface f1 and the concave second surface f2 inward in the height direction, respectively, is applied. Therefore, it is believed that the relative dielectric constant of the high-dielectric-constant dielectric ceramic is unlikely to change even when a DC voltage higher than the rated voltage is applied.

(2) In the above-described multilayer ceramic capacitor 10, the thickness of the first portion 12a of the first external electrode 12 is greater than the maximum depth of the concave first surface f1 of the capacitor body 11, and the thickness of the first portion 13a of the second external electrode 13 is greater than the maximum depth of the concave second surface f2 of the capacitor body 11. Specifically, by adopting this configuration, even when a high-dielectric-constant dielectric ceramic is used in portions of the capacitor body 11 other than the first internal electrode layer 14 and the second internal electrode layer 15 in order to further increase capacitance, deterioration in the DC bias characteristics of the multilayer ceramic capacitor 10 itself can be more reliably suppressed.

While the fact that the above-described configuration can more reliably suppress deterioration in DC bias characteristics is clear from the above description using FIG4 , the following is presumably the basis for this. For example, in the multilayer ceramic capacitor 10 shown in FIG1 to FIG3 , a state in which a force CF (see FIG1 ) compresses the concave first surface f1 and the concave second surface f2 of the capacitor body 11 inward in the width direction and inward in the height direction, respectively, is exerted. This requires thicknesses corresponding to those of the first portion 12a of the first external electrode 12 and the first portion 13a of the second external electrode 13. Therefore, it is believed that this state can be more reliably maintained if the thickness of the first portion 12a of the first external electrode 12 is greater than the maximum depth of the concave first surface f1 of the capacitor body 11, and the thickness of the first portion 13a of the second external electrode 13 is greater than the maximum depth of the concave second surface f2 of the capacitor body 11.

(3) In the above-described multilayer ceramic capacitor 10, when the maximum longitudinal dimension between the concave first surface f1 and the concave second surface f2 of the capacitor body 11 is Dmax and the minimum longitudinal dimension between the concave first surface f1 and the concave second surface f2 of the capacitor body 11 is Dmin, the maximum longitudinal dimension Dmax and the minimum longitudinal dimension Dmin satisfy the condition of 0.90 ≤ Dmin/Dmax ≤ 0.98. As described above with reference to FIG. 4 , if this condition is satisfied, even when a DC voltage higher than the rated voltage is applied, capacitance reduction is unlikely to occur. Therefore, degradation of the DC bias characteristics of the multilayer ceramic capacitor 10 itself can be more reliably suppressed. Furthermore, delamination of the first internal electrode layer 14 and the second internal electrode layer 15 within the capacitor body 11 can be suppressed, thereby providing a high-quality multilayer ceramic capacitor 10.

Claims (8)

1. A multilayer ceramic capacitor, characterized in that it comprises: The capacitor body includes: a first surface and a second surface opposite each other in the length direction; a third surface and a fourth surface opposite each other in the width direction; and a fifth surface and a sixth surface opposite each other in the height direction, and a capacitor portion having a plurality of first internal electrode layers and a plurality of second internal electrode layers stacked in a dielectric layer. A first external electrode, comprising a first portion along the first surface of the capacitor body and a second portion along the fifth surface, wherein the first portion of the first external electrode is connected to the end edges of the plurality of first internal electrode layers; and The second external electrode is formed by a first portion along the second surface of the capacitor body and a second portion along the fifth surface, wherein the first portion of the second external electrode is connected to the end edges of the plurality of second internal electrode layers. The first surface of the capacitor body is concave, and the first portion of the first external electrode is in contact with the first surface of the capacitor body. The second surface of the capacitor body is concave, and the first portion of the second external electrode is in contact with the second surface of the capacitor body. Let the maximum length direction dimension between the first and second concave surfaces of the capacitor body be Dmax, and the minimum length direction dimension between the first and second concave surfaces of the capacitor body be Dmin. Then, the maximum length direction dimension Dmax and the minimum length direction dimension Dmin satisfy the condition 0.90≤Dmin/Dmax≤0.98. 2. The multilayer ceramic capacitor as described in claim 1, characterized in that: The thickness of the first portion of the first external electrode is greater than the maximum depth of the first surface of the concave shape of the capacitor body, and the thickness of the first portion of the second external electrode is greater than the maximum depth of the second surface of the concave shape of the capacitor body. 3. The multilayer ceramic capacitor as described in claim 1 or 2, characterized in that: The number of dielectric layers is 15 or more. 4. The multilayer ceramic capacitor as described in claim 1 or 2, characterized in that: The first inner electrode layer and the second inner electrode layer contain any one of copper, palladium, platinum, silver, gold and their alloys as the main components. 5. The multilayer ceramic capacitor as described in claim 1 or 2, characterized in that: The first external electrode and the second external electrode are approximately L-shaped. 6. The multilayer ceramic capacitor as described in claim 1 or 2, characterized in that: The width of the stacked ceramic capacitor is greater than its length. 7. The multilayer ceramic capacitor as described in claim 1 or 2, characterized in that: The first external electrode and the second external electrode have a base film and a surface film, the surface film containing copper as the main component. 8. The multilayer ceramic capacitor as described in claim 1 or 2, characterized in that: The first external electrode and the second external electrode have a base film, a surface film, and an intermediate film located between the base film and the surface film, wherein the surface film and the intermediate film contain copper as the main component.