HK1222930A1 - 高帶寬存儲器和少故障差分異或 - Google Patents

高帶寬存儲器和少故障差分異或

Info

Publication number
HK1222930A1
HK1222930A1 HK16111103.3A HK16111103A HK1222930A1 HK 1222930 A1 HK1222930 A1 HK 1222930A1 HK 16111103 A HK16111103 A HK 16111103A HK 1222930 A1 HK1222930 A1 HK 1222930A1
Authority
HK
Hong Kong
Prior art keywords
glitch
high bandwidth
bandwidth memory
less differential
differential xor
Prior art date
Application number
HK16111103.3A
Other languages
English (en)
Inventor
特拉維斯．黑比希
米龍．比埃
卡爾．蒙策爾
理查德．約翰．斯特凡妮
Original Assignee
Broadcom Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Broadcom Corp filed Critical Broadcom Corp
Publication of HK1222930A1 publication Critical patent/HK1222930A1/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0638—Organizing or formatting or addressing of data
    • G06F3/064—Management of blocks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1621—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by maintaining request order
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1678—Details of memory controller using bus width
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G06F3/0613—Improving I/O performance in relation to throughput
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0629—Configuration or reconfiguration of storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0638—Organizing or formatting or addressing of data
    • G06F3/0644—Management of space entities, e.g. partitions, extents, pools
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Static Random-Access Memory (AREA)
  • Logic Circuits (AREA)
  • Dram (AREA)
HK16111103.3A 2015-02-19 2016-09-22 高帶寬存儲器和少故障差分異或 HK1222930A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201562118454P 2015-02-19 2015-02-19
US14/644,114 US9753667B2 (en) 2015-02-19 2015-03-10 High bandwidth memory and glitch-less differential XOR

Publications (1)

Publication Number Publication Date
HK1222930A1 true HK1222930A1 (zh) 2017-07-14

Family

ID=56577386

Family Applications (1)

Application Number Title Priority Date Filing Date
HK16111103.3A HK1222930A1 (zh) 2015-02-19 2016-09-22 高帶寬存儲器和少故障差分異或

Country Status (4)

Country Link
US (1) US9753667B2 (zh)
CN (1) CN105912484B (zh)
DE (2) DE102016001224A1 (zh)
HK (1) HK1222930A1 (zh)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11868804B1 (en) 2019-11-18 2024-01-09 Groq, Inc. Processor instruction dispatch configuration
US11114138B2 (en) * 2017-09-15 2021-09-07 Groq, Inc. Data structures with multiple read ports
US11243880B1 (en) 2017-09-15 2022-02-08 Groq, Inc. Processor architecture
US11360934B1 (en) 2017-09-15 2022-06-14 Groq, Inc. Tensor streaming processor architecture
US11170307B1 (en) 2017-09-21 2021-11-09 Groq, Inc. Predictive model compiler for generating a statically scheduled binary with known resource constraints
US11144316B1 (en) 2018-04-17 2021-10-12 Ali Tasdighi Far Current-mode mixed-signal SRAM based compute-in-memory for low power machine learning
US11537687B2 (en) 2018-11-19 2022-12-27 Groq, Inc. Spatial locality transform of matrices
TWI706414B (zh) * 2019-05-27 2020-10-01 國立中山大學 記憶體內運算系統及其記憶體裝置
US10915298B1 (en) 2019-10-08 2021-02-09 Ali Tasdighi Far Current mode multiply-accumulate for compute in memory binarized neural networks
US11615256B1 (en) 2019-12-30 2023-03-28 Ali Tasdighi Far Hybrid accumulation method in multiply-accumulate for machine learning
US11610104B1 (en) 2019-12-30 2023-03-21 Ali Tasdighi Far Asynchronous analog accelerator for fully connected artificial neural networks

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5040179A (en) * 1989-08-18 1991-08-13 Loral Aerospace Corp. High data rate BCH encoder
US5313475A (en) * 1991-10-31 1994-05-17 International Business Machines Corporation ECC function with self-contained high performance partial write or read/modify/write and parity look-ahead interface scheme
US5530824A (en) * 1994-04-04 1996-06-25 Motorola, Inc. Address translation circuit
US7073026B2 (en) * 2002-11-26 2006-07-04 Advanced Micro Devices, Inc. Microprocessor including cache memory supporting multiple accesses per cycle
US7254657B1 (en) * 2005-04-29 2007-08-07 Unisys Corporation Dual mode capability for system bus
US7856588B2 (en) * 2006-10-19 2010-12-21 Hewlett-Packard Development Company, L.P. Data allocation in memory chips
US9442846B2 (en) * 2009-03-17 2016-09-13 Cisco Technology, Inc. High speed memory systems and methods for designing hierarchical memory systems
US8438344B2 (en) * 2010-03-12 2013-05-07 Texas Instruments Incorporated Low overhead and timing improved architecture for performing error checking and correction for memories and buses in system-on-chips, and other circuits, systems and processes

Also Published As

Publication number Publication date
US9753667B2 (en) 2017-09-05
CN105912484A (zh) 2016-08-31
DE102016015773B3 (de) 2024-04-04
CN105912484B (zh) 2019-01-18
DE102016001224A1 (de) 2016-08-25
US20160246506A1 (en) 2016-08-25

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