HK1199552B - Image sensor with pixel units having mirrored transistor layout - Google Patents

Abstract

The subject application relates to image sensor with pixel units having mirrored transistor layout. An image sensor includes a first pixel unit horizontally adjacent to a second pixel unit. Each pixel unit includes plurality of photodiodes and a shared floating diffusion region. A first pixel transistor region of the first pixel unit has a plurality of pixel transistors. A second pixel transistor region of the second pixel unit is horizontally adjacent to the first pixel transistor region and also has a plurality of pixel transistors. A transistor layout of the second pixel transistor region is a mirror image of a transistor layout of the first pixel transistor region.

Description

Image sensor including pixel cells with mirrored transistor layout

Technical Field

The present disclosure relates generally to image sensors, and particularly, but not exclusively, to layout of Complementary Metal Oxide Semiconductor (CMOS) image sensors.

Background

Image sensors have become ubiquitous. It is widely used in digital still cameras, cellular telephones, security cameras, as well as in medical, automotive and other applications. The technology used to fabricate image sensors, and in particular complementary metal oxide semiconductor ("CMOS") image sensors, has been constantly and rapidly evolving. For example, the demand for higher resolution and lower power consumption has facilitated further miniaturization and integration of these image sensors.

Conventional CMOS image sensors typically have a configuration in which a plurality of pixels are arranged in a two-dimensional array, with each pixel including a photodiode and associated pixel transistors. Recently, as miniaturization of image sensors continues, in order to reduce an area occupied by each pixel, a pixel sharing structure in which a pixel transistor is shared among several photodiodes has been implemented. However, typical layouts of pixel sharing structures often have leakage problems between the various portions of the pixel transistors due to their close proximity.

Disclosure of Invention

The present invention provides an image sensor, comprising: a first pixel cell having a first plurality of photodiodes and a first shared floating diffusion region; a second pixel cell horizontally adjacent to the first pixel cell, having a second plurality of photodiodes and a second shared floating diffusion region; a first pixel transistor region of the first pixel unit having a plurality of pixel transistors for reading out image data from the first shared floating diffusion region; and a second pixel transistor region of the second pixel unit horizontally adjacent to the first pixel transistor region, having a plurality of pixel transistors for reading out image data from the second shared floating diffusion region; wherein the transistor layout of the second pixel transistor region is a mirror image of the transistor layout of the first pixel transistor region.

The present invention also provides a Complementary Metal Oxide Semiconductor (CMOS) image sensor, including: a first pixel cell having a first photodiode region and a first shared floating diffusion region of no more than and no less than four photodiodes; a second pixel cell horizontally adjacent to the first pixel cell, having a second photodiode region and a second shared floating diffusion region of no more than and no less than four photodiodes; a first pixel transistor region of the first pixel unit vertically displaced outside the first photodiode region and having a reset transistor, a row select transistor, and a source follower transistor; and a second pixel transistor region of the second pixel cell vertically displaced outside the second photodiode region and horizontally adjacent to the first pixel transistor region, the second pixel transistor region having a reset transistor, a row select transistor, and a source follower transistor, wherein a transistor layout of the second pixel transistor region is a mirror image of a transistor layout of the first pixel transistor region, the mirror image taken about a vertical line separating the first pixel cell from the second pixel cell.

The present invention also provides a Complementary Metal Oxide Semiconductor (CMOS) image sensor, including: a first pixel cell having a first photodiode region and a first shared floating diffusion region of no more than and no less than four photodiodes; a second pixel cell horizontally adjacent to the first pixel cell, having a second photodiode region and a second shared floating diffusion region of no more than and no less than four photodiodes; a first pixel transistor region of the first pixel unit vertically displaced outside the first photodiode region and having a row select transistor and a source follower transistor; a second pixel transistor region of the second pixel unit vertically displaced outside the second photodiode region and horizontally adjacent to the first pixel transistor region, the second pixel transistor region having a row select transistor and a source follower transistor; and a shared reset transistor shared between the first and second pixel transistor regions, wherein a transistor layout of the second pixel transistor region is a mirror image of a transistor layout of the first pixel transistor region, the mirror image taken about a vertical line bisecting the shared reset transistor.

Drawings

Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.

FIG. 1 is a block diagram illustrating an image sensor according to an embodiment of the invention.

Fig. 2 is a diagram of a pixel cell array of an image sensor according to an embodiment of the present invention.

FIG. 3 is a circuit diagram illustrating pixel circuits for two pixel cells within an image sensor according to an embodiment of the invention.

Fig. 4 is a diagram of six pixel cells of an image sensor having a mirrored transistor layout, according to an embodiment of the invention.

Fig. 5 is a diagram of the six pixel cells of fig. 4, further illustrating a number of metal routing lines.

Fig. 6 is a diagram of six pixel cells of an image sensor with a mirror transistor layout and a shared reset transistor according to an embodiment of the invention.

Fig. 7 is a circuit diagram illustrating pixel circuits for two pixel cells within an image sensor having a shared reset transistor according to an embodiment of the invention.

Fig. 8 is a diagram of the six pixel cells of fig. 6, further illustrating a number of metal routing lines.

Detailed Description

Embodiments of an image sensor including pixel cells with mirror transistor layouts are described herein. In the following description, numerous specific details are set forth to provide a thorough understanding of the embodiments. One skilled in the relevant art will recognize, however, that the techniques described herein can be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring certain aspects.

Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

Fig. 1 is a block diagram illustrating an image sensor 100 according to an embodiment of the present invention. The illustrated embodiment of image sensor 100 includes an active area (i.e., pixel array 105), readout circuitry 110, functional logic 115, and control circuitry 120.

For example, pixel array 105 may be a two-dimensional array of backside or frontside illuminated imaging pixels (e.g., pixels PD1, …, Pn). In one embodiment, each pixel is an active pixel sensor ("APS"), such as a complementary metal oxide semiconductor ("CMOS") imaging pixel. As illustrated, each pixel is arranged into a row (e.g., row R1-Ry) and a column (e.g., column C1-Cx) to acquire image data of a person, place, or object, which can then be used to render an image of the person, place, or object.

After each pixel has acquired its image data or image charge, the image data is read out by readout circuitry 110 and transferred to functional logic 115. The readout circuitry 110 may include amplification circuitry, analog-to-digital conversion circuitry, or others. Function logic 115 may simply store the image data or even manipulate the image data by applying post-image effects (e.g., crop, rotate, remove red-eye, adjust brightness, adjust contrast, or otherwise). In one embodiment, readout circuitry 110 may readout a row of image data at a time along readout column lines (illustrated) or may readout the image data using a variety of other techniques (not illustrated), such as a serial readout or a full parallel readout of all pixels simultaneously.

Control circuitry 120 is coupled to pixel array 105 to control the operating characteristics of pixel array 105. For example, the control circuit 120 may generate a shutter signal for controlling image acquisition.

FIG. 2 is a diagram of an array 200 of pixel cells (e.g., pixel cells 202, 204, 206, 208, and 210) of an image sensor according to an embodiment of the invention. In one aspect, a "pixel cell" is a grouping of one or more imaging pixels, such as the imaging pixels of pixel array 105 in image sensor 100 in fig. 1. A pixel cell may include a number of photodiodes each corresponding to a separate pixel of the pixel cell and may also include at least one pixel transistor shared among the photodiodes of the pixel cell.

Several color imaging pixels, such as red (R), green (G), and blue (B) imaging pixels, may be included in the active area of the image sensor. For example, pixel unit 202 is illustrated as including four color imaging pixels (e.g., one R pixel, one B pixel, and two G pixels) arranged in a bayer pattern. Other color imaging pixels and other color patterns not shown may be implemented into the pixel cells according to the teachings of this disclosure.

As illustrated, each pixel cell of the array 200 is arranged into a row (e.g., rows R1-Rj) and a column (e.g., columns C1-Ci). Accordingly, an image sensor according to the teachings herein may include both an imaging pixel array and a pixel cell array, where the pixel cell array is an organized grouping of imaging pixels in a pixel array. Furthermore, as will be discussed in more detail below, each pixel cell may have a pixel transistor layout that is a mirror image of the adjacent pixel cells in the next column. For example, the pixel transistor layout of pixel cell 204 may be a mirror image of the pixel transistor layout of pixel cell 202.

FIG. 3 is a circuit diagram illustrating pixel circuits for two pixel cells within an image sensor according to an embodiment of the invention. Pixel circuit 300 is one possible pixel circuit architecture for implementing each pixel cell within array 200 of fig. 2. It should be understood, however, that embodiments of the invention are not limited to the illustrated pixel architecture; rather, those skilled in the art, having the benefit of this disclosure, will appreciate that the teachings of the present disclosure are applicable to a variety of other pixel architectures as well.

In fig. 3, pixel cells 1 and pixel cells m are arranged in two rows and one column. The illustrated embodiment of each pixel circuit includes four photodiodes (PD 1-PD 4), four transfer transistors (TX 1-TX 4), a reset transistor RST, a source follower transistor SF, and a row select transistor RS. During a readout operation of the first photodiode PD1, the transfer transistor TX1 receives a transfer signal that causes the transfer transistor TX1 to transfer charge accumulated in the photodiode PD1 to the shared floating diffusion region FD.

The reset transistor RST is coupled between a reset voltage supply RSTVDD and the floating diffusion region FD to be reset (e.g., discharge or charge the FD to a preset voltage) under control of a reset signal. The floating diffusion region FD is coupled to the gate of the source follower transistor SF. The source follower transistor SF is coupled between a source follower voltage supply SFVDD and a row select transistor RS. The source follower transistor SF operates as a source follower providing a high impedance output from the floating diffusion region FD. Finally, a row select transistor RS selectively couples the output of the pixel circuit to a column bit line under control of a row select signal. In one embodiment, the transfer signal, reset signal, and row select signal are all generated by control circuit 120. The transfer signal, reset signal, row select signal, source follower voltage supply SFVDD, reset voltage supply RSTVDD, and ground may be routed in the pixel circuit by means of metal interconnect layers (i.e., wiring) included in the image sensor.

Fig. 4 is a diagram of six pixel cells (e.g., pixel cells 1-6) of an image sensor having a mirrored pixel transistor layout in accordance with an embodiment of the present invention. The six pixel cells of FIG. 4 are arranged into two rows (R1 and R2) and three columns (C1-C3) of pixel cells that include a total of 4 rows and 6 columns of pixels. Pixel cells 1-6 may represent at least some of the pixel cells included in array 200 of fig. 2. For example, pixel cell 1 may correspond to pixel cell 202 of fig. 2, pixel cell 2 may correspond to pixel cell 204, and pixel cell 4 may correspond to pixel cell 208.

As shown in fig. 4, each pixel cell includes a photodiode region and a pixel transistor region. Within the photodiode region, each illustrated pixel cell includes four photodiodes (PDn), four transfer gates (TXn), and a shared floating diffusion region FD. In the illustrated example of fig. 4, each pixel cell includes no more than and no less than four photodiodes and no more than one shared floating diffusion region FD. Furthermore, the floating diffusion regions coupled together will increase the floating diffusion capacitance, which can result in a reduction in conversion gain/sensitivity. Thus, in one embodiment, the floating diffusion region FD of each pixel cell is not coupled to any other floating diffusion region of any other pixel cell.

Within the pixel transistor area, each illustrated pixel cell includes a source follower transistor SF, a row select transistor RS, and a reset transistor RST. The source follower transistor SF includes a gate 402 and doped regions 404 and 406 (i.e., drain and source). The row select transistor RS includes a gate 408 and doped regions 406 and 410. The reset transistor RST is shown as including a gate 412 and doped regions 414 and 416. The pixel circuitry of each pixel cell is coupled and functions as described above with reference to the circuit diagram of fig. 3 to read out image data from the respective floating diffusion region. For example, during a readout operation of the first photodiode PD1, the transfer gate TX1 receives a transfer signal that causes charge accumulated in the photodiode PD1 to be transferred to the shared floating diffusion region FD of the pixel cell 1.

The reset transistor RST of pixel cell 1 is coupled to be reset (e.g., to discharge or charge the FD to a preset voltage) under control of a reset signal received at gate 412. The floating diffusion region FD of the pixel cell 1 is coupled to the gate 402 of the source follower transistor SF. The source follower transistor SF of the pixel cell 1 operates as a source follower providing a high impedance output from the associated floating diffusion region FD. Finally, the row select transistor RS of pixel cell 1 selectively couples the output of the pixel circuit of pixel cell 1 to the column bit line connection 420 under control of a row select signal received at gate 408.

Also included in the pixel transistor region are a shared source follower voltage supply connection 418, a column bit line connection 420, and a shared reset voltage supply connection 422. In one embodiment, connections 418, 420 and 422 are metal pads for connection with metal wiring (discussed below with reference to FIG. 5) that carries their respective signals among a number of pixel cells.

The pixel transistor regions of fig. 4 are shown as being vertically displaced (along the y-axis) outside of their respective photodiode regions. For example, the pixel transistor region of pixel cell 1 is vertically displaced below and outside the photodiode region of pixel cell 1 such that the pixel transistor region of pixel cell 1 is disposed between the photodiode region of pixel cell 1 and the photodiode region of the pixel cell in the lower row (i.e., pixel cell 4). In addition, the photodiode and pixel transistor regions are horizontally adjacent to the photodiode and pixel transistor regions of the pixel units in the same row. For example, pixel cell 2 is horizontally adjacent (along the x-axis) to pixel cell 1, meaning that the photodiode region of pixel cell 2 is horizontally adjacent to the photodiode region of pixel cell 1 and the pixel transistor region of pixel cell 2 is horizontally adjacent to the pixel transistor region of pixel cell 1.

The pixel transistor layout for each pixel transistor region is further shown in fig. 4 as a mirror image of the pixel transistor layout for horizontally adjacent pixel transistor regions. That is, in one embodiment, the pixel transistor layout of one pixel transistor region is identical to, but inverted from, the pixel transistor layout of a horizontally adjacent pixel transistor region. For example, the pixel transistor layout of the pixel transistor region of pixel cell 2 is a mirror image of the pixel transistor layout of the pixel transistor region of pixel cell 1. The transistor layout of pixel cell 1, viewed from left to right along the x-axis, includes a source follower voltage supply connection 408, a source follower transistor SF, a row select transistor RS, a column bit line connection 420, a reset transistor RST and a final reset voltage supply connection 422, while the transistor layout of pixel cell 2, viewed from left to right, includes a reset voltage supply connection 422, a reset transistor RST, a column bit line connection 426, a row select transistor RS, a source follower transistor SF and a final source follower voltage supply connection 428.

As shown in fig. 4, the mirror image between the pixel transistor layouts of pixel cells 1 and 2 is taken with respect to a vertical (along the y-axis) line 424 separating pixel cell 2 from pixel cell 1. In one embodiment, line 424 bisects reset voltage supply connection 422 such that the mirror is taken about the center of reset voltage supply connection 422. Thus, the reset transistor RST of pixel cell 1 is adjacent to the reset transistor RST of pixel cell 2, with both reset transistors coupled to the same reset voltage supply connection 422. Thus, the reset voltage supply connection 422 is a shared connection shared between pixel cell 1 and pixel cell 2. Having a mirror transistor layout and a shared reset voltage supply connection 422 can provide more space and better isolation between components of the pixel transistor region in order to reduce leakage. Furthermore, having a shared reset voltage supply connection 422 may require less metal routing to reduce interconnect coupling.

As mentioned above, the pixel transistor layout of each pixel transistor region is a mirror image of the pixel transistor layout of the horizontally adjacent pixel transistor region. Thus, not only the pixel transistor layout of the pixel unit 2 is a mirror image of the pixel transistor layout of the pixel unit 1, but also the pixel transistor layout of the pixel unit 3 is a mirror image of the pixel transistor layout of the pixel unit 2. Thus, pixel cell 3 shares the source follower voltage supply connection 428 with pixel cell 2, where the source follower transistor SF of pixel cell 2 is disposed adjacent to the source follower transistor SF of pixel cell 3. As shown in fig. 4, the mirror image between the pixel transistor layouts of pixel cells 2 and 3 is taken with respect to a vertical (along the y-axis) line 430 separating pixel cell 3 from pixel cell 2. In one embodiment, the line 430 bisects the source follower voltage supply connection 428 such that the mirror image is taken about the center of the source follower voltage supply connection 428.

Having a mirror transistor layout and a shared source follower voltage supply connection 428 between pixel cells may provide further space and better isolation between the components of the pixel transistor region to further reduce leakage. Furthermore, having a shared source follower voltage supply connection 422 may require less metal routing to further reduce interconnect coupling.

In one embodiment, the mirror transistor layout and shared connections (e.g., connections 422 and 428) provide additional pixel area that can be allocated to other additional features within the pixel transistor region. For example, the additional pixel area may be used to provide a ground node (i.e., a ground contact), an anti-blooming node (i.e., a doped well to collect blooming excess signals), or may be used to allow for a larger source follower transistor SF to provide lower Random Telegraph (RTG) noise.

Fig. 5 is a diagram of the six pixel cells of fig. 4, further illustrating a number of metal routing lines. As mentioned above, the six pixel cells are arranged into two rows (R1 and R2) and three columns (C1-C3) of pixel cells that include a total of 4 rows and 6 columns of pixels. Vertical (along the y-axis) metal routing 504-512 and horizontal (along the x-axis) metal routing 516-526 are shown in fig. 5. In one embodiment, each metal routing is one or more metal layers included in the image sensor for routing signals to and from the connections previously discussed (e.g., connections 418, 420, 422, 426, and 428 of FIG. 4).

Each column of pixel cells can include respective column bitline wiring (column bitline wiring 504, 508, and 512) for outputting image data from the respective column. However, the source follower voltage supply wiring (SFVDD) and the reset voltage supply wiring (RSTVDD) are shared wirings shared among adjacent columns. For example, RSTVDD506 is shared among pixel cells of both the first column C1 and the second column C2, while SFVDD 510 is shared among pixel cells of both the second column C2 and the third column C3. In one embodiment, the source follower voltage supply is separate from the reset voltage supply so that each can be set independently.

As mentioned above, the transistor layout of a pixel cell is a mirror image of the transistor layout of a horizontally adjacent pixel cell. Thus, in one embodiment, the mirror image may be taken with respect to vertical metal routing. For example, the transistor layout of pixel cell 1 (i.e., row R1, column C1) is a mirror image of the transistor layout of pixel cell 2 (i.e., row R1, column C2) taken with respect to the reset voltage supply wiring RSTVDD506 running vertically (along the y-axis) between the first and second pixel cells. Similarly, the transistor layout of pixel cell 2 is a mirror image of the transistor layout of pixel cell 3 (i.e., row R1, column C3), taken with respect to the source follower voltage supply wiring SFVDD 510 running vertically between the second and third pixel cells.

Having shared wiring may provide more space and better isolation between components of the pixel cell in order to reduce leakage. Furthermore, having shared metal wiring reduces interconnect coupling, simplifies fabrication, and reduces cost.

Horizontal metal routing 516-526 is also shown in fig. 5. The metal wirings 516 to 522 are used to provide transfer signals (TX _1A to TX _1D) for controlling transfer gates included in the first row R1 of pixel cells. The metal wirings 524 and 526 are used to supply a reset signal (RST _1) and a row selection signal (RS _1) to the reset transistor RST and the row selection transistor RS of the first row R1 of the pixel unit, respectively.

Fig. 6 is a diagram of six pixel cells of an image sensor with a mirror transistor layout and a shared reset transistor RST, in accordance with an embodiment of the present invention. The six pixel cells of FIG. 6 are arranged into two rows (R1 and R2) and three columns (C1-C3) of pixel cells that include a total of 4 rows and 6 columns of pixels. Pixel cells 1-6 may represent at least some of the pixel cells included in array 200 of fig. 2. For example, pixel cell 1 may correspond to pixel cell 202 of fig. 2, pixel cell 2 may correspond to pixel cell 204, and pixel cell 4 may correspond to pixel cell 208.

The pixel cell of fig. 6 is similar in structure and function to the pixel cell of fig. 4 described above. However, the pixel cell of FIG. 6 includes a shared reset transistor shared between horizontally adjacent pixel transistor regions. For example, fig. 6 illustrates a shared reset transistor RST shared between the pixel transistor regions of pixel cell 1 and pixel cell 2. The shared reset transistor RST is shown as including a gate 612 and doped regions 614 and 616. Also shown in fig. 6 is a shared reset voltage supply connection 622. As with the pixel cell of fig. 4, the pixel transistor layout of each pixel transistor region illustrated in fig. 6 is a mirror image of the pixel transistor layout of the horizontally adjacent pixel transistor region. That is, in one embodiment, the pixel transistor layout of one pixel transistor region is identical to, but inverted from, the pixel transistor layout of a horizontally adjacent pixel transistor region. For example, the pixel transistor layout of the pixel transistor region of pixel cell 2 is a mirror image of the pixel transistor layout of the pixel transistor region of pixel cell 1. The transistor layout of the pixel cell 1, viewed from left to right along the x-axis, includes a source follower voltage supply connection 618, a source follower transistor SF, a row select transistor RS, a column bit line connection 620, and a shared reset transistor RST and a reset voltage supply connection 622. This transistor layout is mirrored by the transistor layout of the pixel cell 2. That is, still looking from left to right, the transistor layout of the pixel cell 2 includes a reset voltage supply connection 622 and a shared reset transistor RST, a column bit line connection 626, a row select transistor RS, a source follower transistor SF, and a last shared source follower voltage supply connection 628.

As shown in fig. 6, the mirroring between the pixel transistor layouts of pixel cells 1 and 2 is taken with respect to the vertical (along the y-axis) line 624 separating pixel cell 2 from pixel cell 1. In one embodiment, line 624 bisects reset voltage supply connection 622 such that the mirror is taken about the center of reset voltage supply connection 622. In another embodiment, line 624 bisects the shared reset transistor RST such that the mirror is taken about the center of the reset transistor RST.

Having a mirror transistor layout with a shared reset transistor RST and a shared reset voltage supply connection 622 may provide more space and better isolation between components of the pixel transistor area to further reduce leakage. Furthermore, having a shared reset voltage supply connection 622 and a shared reset transistor RST may require less metal routing to reduce interconnect coupling.

As mentioned above, the pixel transistor layout of each pixel transistor region is a mirror image of the pixel transistor layout of the horizontally adjacent pixel transistor region. Thus, not only the pixel transistor layout of the pixel unit 2 is a mirror image of the pixel transistor layout of the pixel unit 1, but also the pixel transistor layout of the pixel unit 3 is a mirror image of the pixel transistor layout of the pixel unit 2. Thus, pixel cell 3 shares a source follower voltage supply connection 628 with pixel cell 2, where the source follower transistor SF of pixel cell 2 is disposed adjacent to the source follower transistor SF of pixel cell 3. As shown in fig. 6, the mirror image between the pixel transistor layouts of pixel cells 2 and 3 is taken with respect to a vertical (along the y-axis) line 630 separating pixel cell 3 from pixel cell 2. In one embodiment, the line 630 bisects the source follower voltage supply connection 628 such that the mirror image is taken about the center of the source follower voltage supply connection 628.

Fig. 7 is a circuit diagram illustrating pixel circuits for two pixel cells within an image sensor having a shared reset transistor according to an embodiment of the invention. Pixel circuit 700 is one possible pixel circuit architecture for implementing each pixel cell within array 200 of fig. 2. It should be understood, however, that embodiments of the invention are not limited to the illustrated pixel architecture; rather, those skilled in the art, having the benefit of this disclosure, will appreciate that the teachings of the present disclosure are applicable to a variety of other pixel architectures as well.

In fig. 7, pixel cells 1 and 4 are arranged in two rows and one column. The illustrated embodiment of each pixel circuit includes four photodiodes (PD 1-PD 4), four transfer transistors (TX 1-TX 4), a source follower transistor SF, and a row select transistor RS. Also shown in fig. 3 is a shared reset transistor RST shared among horizontally (along the x-axis) adjacent pixel cells. During a readout operation of the first photodiode PD1, the transfer transistor TX1 receives a transfer signal that causes the transfer transistor TX1 to transfer charge accumulated in the photodiode PD1 to the shared floating diffusion region FD.

The shared reset transistor RST is coupled between a reset voltage supply RSTVDD and the floating diffusion region FD to be reset (e.g., to discharge or charge the FD to a preset voltage) under control of a reset signal. The floating diffusion region FD is coupled to the gate of the source follower transistor SF. The source follower transistor SF is coupled between a source follower voltage supply SFVDD and a row select transistor RS. The source follower transistor SF operates as a source follower providing a high impedance output from the floating diffusion region FD. Finally, a row select transistor RS selectively couples the output of the pixel circuit to a column bit line under control of a row select signal.

Fig. 8 is a diagram of the six pixel cells of fig. 6, further illustrating a number of metal routing lines. The metal wiring of fig. 8 is similar in structure and function to the metal wiring of fig. 5 described above. However, the vertical reset voltage supply wiring RSTVDD806 is disposed to bisect the reset voltage supply connection 622 and also to bisect the shared reset transistor RST itself.

The above description of illustrated embodiments of the invention, including what is described in the Abstract of the disclosure, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes, various modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize.

These modifications can be made to the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific embodiments disclosed in the specification. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.

Claims (14)

1. An image sensor, comprising

A first pixel cell having a first plurality of photodiodes and a first shared floating diffusion region;

a second pixel cell horizontally adjacent to the first pixel cell, having a second plurality of photodiodes and a second shared floating diffusion region;

a first pixel transistor region of the first pixel unit having a plurality of pixel transistors for reading out image data from the first shared floating diffusion region; and

a second pixel transistor region of the second pixel cell horizontally adjacent to the first pixel transistor region, having a plurality of pixel transistors for reading out image data from the second shared floating diffusion region;

wherein a transistor layout of the second pixel transistor region is a mirror image of a transistor layout of the first pixel transistor region, and wherein the pixel transistor regions each comprise a row select transistor and a source follower transistor, the image sensor further comprising a shared reset transistor shared between the first and second pixel transistor regions, and wherein the mirror image is taken with respect to a vertical line bisecting the shared reset transistor.

2. The image sensor of claim 1, wherein the mirror image is taken with respect to a vertical line separating the first pixel cell from the second pixel cell.

3. The image sensor of claim 1, wherein each pixel cell has no more than one shared floating diffusion region.

4. The image sensor of claim 1, wherein the first pixel transistor region is vertically displaced outside of a first photodiode region that includes the first plurality of photodiodes, and wherein the second pixel transistor region is vertically displaced outside of a second photodiode region that includes the second plurality of photodiodes.

5. The image sensor of claim 1, wherein each of the plurality of photodiodes includes no more than and no fewer than four photodiodes.

6. The image sensor of claim 1, further comprising:

a third pixel cell horizontally adjacent to the second pixel cell, having a third plurality of photodiodes and a third shared floating diffusion region; and

a third pixel transistor region of the third pixel cell, horizontally adjacent to the second pixel transistor region, having a plurality of pixel transistors for reading out image data from the third shared floating diffusion region,

wherein a transistor layout of the third pixel transistor region is a mirror image of the transistor layout of the second pixel transistor region.

7. The image sensor of claim 6, wherein a source follower transistor of the second pixel transistor region is disposed adjacent to a source follower transistor of the third pixel transistor region.

8. A CMOS image sensor includes

A first pixel cell having a first photodiode region and a first shared floating diffusion region of no more than and no less than four photodiodes;

a second pixel cell horizontally adjacent to the first pixel cell, having a second photodiode region and a second shared floating diffusion region of no more than and no less than four photodiodes;

a first pixel transistor region of the first pixel unit vertically displaced outside the first photodiode region; and

a second pixel transistor region of the second pixel unit vertically displaced outside the second photodiode region and horizontally adjacent to the first pixel transistor region,

wherein the transistor layout of the second pixel transistor region is a mirror image of the transistor layout of the first pixel transistor region, the mirror image taken with respect to a vertical line separating the first pixel cell from the second pixel cell, and wherein the pixel transistor regions each include a row select transistor and a source follower transistor, the image sensor further comprising a shared reset transistor shared between the first and second pixel transistor regions.

9. The image sensor of claim 8, wherein each pixel cell has no more than one shared floating diffusion region.

10. The image sensor of claim 8, further comprising:

a third pixel cell horizontally adjacent to the second pixel cell, having a third photodiode region and a third shared floating diffusion region of no more than and no less than four photodiodes; and

a third pixel transistor region of the third pixel cell vertically displaced outside the third photodiode region and horizontally adjacent to the second pixel transistor region, the third pixel transistor region having a reset transistor, a row select transistor, and a source follower transistor,

wherein a transistor layout of the third pixel transistor region is a mirror image of the transistor layout of the second pixel transistor region, the mirror image taken about a vertical line separating the second pixel cell from the third pixel cell.

11. The image sensor of claim 10, wherein the source follower transistor of the second pixel transistor region is disposed adjacent to the source follower transistor of the third pixel transistor region.

12. A CMOS image sensor includes

A first pixel cell having a first photodiode region and a first shared floating diffusion region of no more than and no less than four photodiodes;

a second pixel cell horizontally adjacent to the first pixel cell, having a second photodiode region and a second shared floating diffusion region of no more than and no less than four photodiodes;

a first pixel transistor region of the first pixel unit vertically displaced outside the first photodiode region and having a row select transistor and a source follower transistor;

a second pixel transistor region of the second pixel unit vertically displaced outside the second photodiode region and horizontally adjacent to the first pixel transistor region, the second pixel transistor region having a row select transistor and a source follower transistor; and

a shared reset transistor shared between the first and second pixel transistor regions, wherein a transistor layout of the second pixel transistor region is a mirror image of a transistor layout of the first pixel transistor region, the mirror image taken about a vertical line bisecting the shared reset transistor.

13. The image sensor of claim 12, further comprising:

a third pixel cell horizontally adjacent to the second pixel cell, having a third photodiode region and a third shared floating diffusion region of no more than and no less than four photodiodes; and

a third pixel transistor region of the third pixel unit vertically displaced outside the third photodiode region and horizontally adjacent to the second pixel transistor region, the third pixel transistor region having a row select transistor and a source follower transistor,

wherein a transistor layout of the third pixel transistor region is a mirror image of the transistor layout of the second pixel transistor region, the mirror image taken about a vertical line separating the second pixel cell from the third pixel cell.

14. The image sensor of claim 13, wherein the source follower transistor of the second pixel transistor region is disposed adjacent to the source follower transistor of the third pixel transistor region.