WO2023092248A1

WO2023092248A1 - Solid-state imaging device having tunable conversion gain, driving method, and electronic device

Info

Publication number: WO2023092248A1
Application number: PCT/CN2021/132225
Authority: WO
Inventors: Seiji Takahashi
Original assignee: Huawei Technologies Co.,Ltd.
Priority date: 2021-11-23
Filing date: 2021-11-23
Publication date: 2023-06-01
Also published as: CN117999796A

Abstract

This application provides a solid-state imaging device comprising: a pixel array in which one or more pixels form a pixel unit, wherein each pixel unit comprises: one or more photodiodes to convert electromagnetic radiation into an electrical charge; one or more transfer gate devices each corresponding to one of the one or more photodiodes, and to selectively transfer the electrical charge; a floating diffusion to accumulate the electrical charge transferred from the one or more transfer gate devices; a selector to selectively output an output signal corresponding to the electrical charge accumulated in the floating diffusion; a first switching device to selectively switch between two types of conversion gain; and a reset device connected to a power supply voltage, and to selectively reset the electrical charge accumulated in the floating diffusion; wherein a first node between the first switching device and the reset device in a first pixel unit is connected to one or more second nodes between a first switching device and a reset device in one or more second pixel units.

Description

SOLID-STATE IMAGING DEVICE HAVING TUNABLE CONVERSION GAIN, DRIVING METHOD, AND ELECTRONIC DEVICE

TECHNICAL FIELD

This application relates to the field of a solid-state imaging device. More particularly, the invention relates to a tunable conversion gain structure, its driving methods and a related electronic devicewhich enhance a signal-to-noise ratio and a dynamic range.

BACKGROUND

One key performance indicator related toa solid-state imaging device is a full well capacity whichis an upper limit of a capacity capable of accumulating charges generated by convertingdetected electromagnetic radiation into electrons. Since charges that exceed the full well capacity cannot be detected as a signal, alower full well capacity results in alower dynamic range (DR) and lower SNR (signal to noise ratio) under a high amount of electromagnetic radiation. Conversely, ahigher full well capacity contributes to reproducingahigher definition image that is animage more faithful to detected electromagnetic radiation. Therefore, the higher full capacity is always preferred and there is a strong demandto increase full well capacity as much as possible with a limited area in the solid-state imaging device.

In order to increase a signal-to-noise ratio and a dynamic range, a binning switch is introduced to connect multiple floating diffusion nodes in different pixels, and thereby increase a capacity of a floating diffusion. For example, US 9,961,262 B2 discloses a solid-state imaging device in which one or two binning switches (BIN1, BIN2) is applied to change the capacity of the floating diffusion. The binning switch electrically shorts floating diffusions in two different rows to increase the capacity of the floating diffusion. Accordingly, more charges can be accumulated in the floating diffusion, and thereby a low conversion gain mode used for a high dynamic range is realized.

However, even if the capacitance of the floating diffusion is increased by utilizing the binning switch such as in relatedart, it is not enough to store all charges transferred into the floating diffusion. In addition, the relatedart is not compatible forreading out two rows in parallel. Furthermore, the relatedart is not suitable for a Bayer filter with a multi-pixel (such as quad) Bayer arrangement.

SUMMARY

Embodiments of this application provide a solid-sate imaging device, its driving method, and a related apparatus to realize more capacity of the floating diffusion. Some of embodiments of this application further provide a solid-sate imaging device, its driving method, and related apparatus to resolve one or more problems in the relatedarts.

According to a first aspect, an embodiment of the present invention provides a solid-state imaging device comprising: a pixel array in which one or more pixels form a pixel unit, whereineach pixel unit comprises:

one or more photodiodes toconvert electromagnetic radiation into an electrical charge;

one or more transfer gate devices each corresponding to oneof the one or more photodiodes, and toselectively transfer the electrical charge;

a floating diffusion toaccumulate the electrical charge transferred from the one or more transfer gate devices;

a selector toselectively output an output signal corresponding to the electrical charge accumulated in the floating diffusion;

a first switching device toselectively switch between two types of conversion gain; and

a reset device connected to a power supply voltage, and toselectively reset the electrical charge accumulated in the floating diffusion;

wherein a first node between the first switching device and the reset device in a first pixel unit is connected to one or more second nodes between afirst switching device and areset device in one or more second pixel units.

With reference to the first aspect, in a first possible implementation of the first aspect, the first pixel unit and the one or more second pixel units thatare connected to the first pixel unit share an output signal line.

With reference to the first aspect, in a second possible implementation of the first aspect, the transfer device and the reset device in each of the one or more second pixel units are turned off throughout a first period in which a readout operation of the first pixel unit is performed.

With reference to the first aspect, in a third possible implementation of the first aspect, the first switching device in the one or more second pixel units is turned on, throughout a first predetermined period that begins after the first period begins and ends before the first period ends.

With reference to the first aspect, in a fourth possible implementation of the first aspect, each of the pixel units further comprises:

a second switching device connected between the first node and the second node in one of the one or more second pixel units;

wherein the second switching devices in the first pixel unit and the one or more second pixel units are turned on throughout the first predetermined period.

With reference to the first aspect, in a fifth possible implementation of the first aspect, a threshold voltage of the second switching device is equal to or higher than a threshold voltage of the reset device or the first switching device.

With reference to the first aspect, in a sixth possible implementation of the first aspect, in a high conversion gain mode, the reset device in the first pixel unit is turned on throughout the first period, and the electrical charge accumulated in the floating diffusion is reset by turning on the first switching device in the first pixel unit;

in a middle conversion gain mode, the first switching device in the first pixel unit is turned on throughout the first period, and the electrical charge accumulated in the floating diffusion is reset by turning on the reset device in the first pixel unit; and

in a low conversion gain mode, the first switching device and the one or more second switching devices in the first pixel unit are turned on throughout the first period, and the electrical charge accumulated in the floating diffusion is reset by turning on the selectors in the one or more second pixel units.

With reference to the first aspect, in a seventh possible implementation of the first aspect, in the LCG mode and in the MCG mode, all or some of the one or more selectors in the one or more second pixel units are turned on throughout a first predetermined period that begins after the first periodbegins and ends before the first period ends.

With reference to the first aspect, in an eighth possible implementation of the first aspect, the second switching device in the first pixel unit and the second switching devices in the one or more second pixel units are connected in series; or the second switching device in the first pixel unit and the second switching devices in the one or more second pixel units are connected in parallel.

With reference to the first aspect, in a ninth possible implementation of the first aspect, the first pixel unit is arranged in asame row as and a different column from the one or more second pixel units; or

the first pixel unit is arranged in a different row from and asame column as the one or more second pixel units; or

the first pixel unit is arranged in a different row from and a different column from the one or more second pixel units.

With reference to the first aspect, in a tenth possible implementation of the first aspect, the first pixel unit and the one or more second pixel units are arranged consecutively in asame row or in asame column.

With reference to the first aspect, in an eleventh possible implementation of the first aspect, the first pixel unit and the one or more second pixel units are arranged at regular intervals in asame row or in asame column.

With reference to the first aspect, in a twelfth possible implementation of the first aspect, the pixel units are arranged in a Bayer color filter pattern, and wherein the first pixel unit and the one or more second pixel units have asame color filter.

With reference to the first aspect, in a thirteenth possible implementation of the first aspect, the source terminal or the drain terminal of the second switching device shares an active area with the source terminal or the drain terminal of the first switching device.

With reference to the first aspect, in a fourteenth possible implementation of the first aspect, a length or a width of the second switching device is equal to or less than a length or a width of one or more of the first switching device, the reset device, and the selector.

With reference to the first aspect, in a fourteenth possible implementation of the first aspect, the solid-state imaging device further comprising one or more shielding elements among a wire connecting the first node and the one or more second nodes in one set of the first pixel unit and the one or more second pixel units, a wire connecting the first node and the one or more second nodes in one or more other sets of the first pixel unit and the one or more second pixel units, the power supply voltage, a ground voltage, and an output voltage.

According to a second aspect, an embodiment of the present invention provides an image sensor comprising the solid-state imaging device according to any one of the first aspect and its possible implementations.

According to a third aspect, an embodiment of the present invention provides anelectronic apparatus comprising the solid-state imaging device according to any one of the first aspect and its possible implementations.

According to a fourth aspect, an embodiment of the present invention providesa method for driving solid-state imaging device comprising: a pixel array in which one or more pixels form a pixel unit, whereineach pixel unit comprises:

one or more photodiodes toconvert electromagnetic radiationinto an electrical charge;

wherein a first node between the first switching device and the reset device in a first pixel unit is connected to one or more second nodes between afirst switching device and areset device in one or more second pixel units;

the method comprising:

turning off the transfer device and the reset device in each of the one or more second pixel units throughout a first period in which a readout operation of the first pixel unit is performed;

turning on the first switching device in the one or more second pixel units, throughout a first predetermined period that begins after the first period begins and ends before the first period ends.

With reference to the fourth aspect, in a first possible implementation of the fourth aspect, each of the pixel units further comprises:

the method further comprising:

turning on the second switching devices in the first pixel unit and the one or more second pixel units throughout the first predetermined period.

With reference to the fourth aspect, in a second possible implementation of the fourth aspect, the method further comprising:

in a high conversion gain mode, turning on the reset device in the first pixel unit throughout the first period, and resetting the electrical charge accumulated in the floating diffusion by turning on the first switching device in the first pixel unit;

in a middle conversion gain mode, turning on the first switching device in the first pixel unit throughout the first period, and resetting the electrical charge accumulated in the floating diffusion by turning on the reset device in the first pixel unit; and

in a low conversion gain mode, turning on the first switching device and the one or more second switching devices in the first pixel unit throughout the first period, and resetting the electrical charge accumulated in the floating diffusion by turning on the selectors in the one or more second pixel units.

BRIEF DESCRIPTION OF DRAWINGS

To describe the technical solutions in the embodiments of this application or in the background more clearly, the following describes the accompanying drawings for describing the embodiments of this application or the background. Apparently, the accompanying drawings in the following description show some embodiments of this application, and a person of ordinary skilled in the art may still derive another drawing from these accompanying drawings without creative efforts.

FIG. 1 is a block diagram of an example of a solid-state imaging device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram comprisingtwo pixels connected via a wire according to an embodiment of the present invention.

FIG. 3A to FIG. 3Cshow different ways of connecting multiple pixels for parallel readout according to an embodiment of the present invention.

FIG. 4 is a circuit diagram comprising multiple pixels connected via switching devices arranged in series according to an embodiment of the present invention.

FIG. 5 is a timingchartduring a readout operation based on the circuit diagram shown in FIG. 4.

FIG. 6 is a circuit diagram comprising multiple pixels connected via switching devices arranged in parallel according to an embodiment of the present invention.

FIG. 7 is a circuit diagram comprising multiple pixels connected in a way that a source terminal of a switching device is connected to a drain terminal of another switching device according to an embodiment of the present invention.

FIG. 8 is a circuit diagram comprising all the pixels in the same column connected via switching devices according to an embodiment of the present invention.

FIG. 9 is a circuit diagram comprising multiple pixels connected via switching devices in multiple rows and columns according to an embodiment of the present invention.

FIG. 10 is a circuit diagram comprising four sets of photodiodes and transfer devices share pixel devices according to an embodiment of the present invention.

FIG. 11 is a circuit diagram in which the embodiment shown in FIG. 10 is applied to a quad Bayer color filter pattern.

FIG. 12 is a top view of an example circuit layout formed on a semiconductor substrate for a pixel unit comprising a photodiode according to an embodiment of the present invention.

FIG. 13 is a top view of an example circuit layout formed on a semiconductor substrate for a pixel unit comprising four photodiodes according to an embodiment of the present invention.

FIG. 14 is a top view of an example circuit layout in which a switching device is placed isolatedly according to an embodiment of the present invention.

FIG. 15 is a circuit diagram in which shielding among wires between switching devices are added to the embodiment shown in FIG. 4 according to an embodiment of the present invention.

FIG. 16 is a top view of an example circuit layout for the circuit diagram shown in FIG. 15 according to an embodiment of the present invention.

FIG. 17 is a cross-sectional view of a part of a pixel array according to an embodiment of the present invention.

FIG. 18 is schematic diagrams of a solid-sate imaging device according to an embodiment of the present invention.

FIG. 19 is a diagram illustrating an exemplary configuration of an electronic apparatus having an imaging element to which the present technology is applied.

FIG. 20 shows examples of technologies to which the present technology is applied.

DESCRIPTION OF EMBODIMENTS

The terms used in this application are merely intended to describe a particular possible implementation rather than to limit this application. The terms "a" , "said" and "the" for a singular form used in this application including the attached claims are also intended to include a case of a plural form, unless otherwise clearly stated. It should be further understood that the term "and/or" used in this specification means any or all possible combinations of one or more listed related items. It should be further understood that, the term "include" used in this specification specifies presence of the features, data, information, entities, steps, operations, devices, units, elements and/or components, without excluding presence or attachment of one or more other features, data, information, entities, steps, operations, devices, units, elements, components, and/or a combination thereof.

It should be understood that, although terms such as "first" and "second" may be used in the embodiments of this application to describe various devices or units, these devices or units should not be limited by the terms. These terms are merely used to differentiate the devices or units from each other. For example, a first device and a first unitmay be referred to as a second device and a second unitrespectively without departing from the scope of the embodiments of this application. Similarly, a second device and a second unit may be referred to as a first device and a first unit respectively.

It should be noted that an order of steps in this application may be freely arranged. That is, the order of stepsis not limited in this application.

The following describes technical solutions in the embodiments of this application with reference to the accompanying drawings.

FIG. 1 shows a block diagram of an example of a solid-state imaging deviceaccording to an embodiment of the present invention. In FIG. 1, a solid-state imaging device 100includesa pixel array 101, a control circuit 102, a readout circuit 103, and a signal processing circuit 104. The pixel array 101 is a two-dimensional (2D) array of pixels, in which the pixels are arranged in rows (R1 to Ry in FIG. 1) and columns (C1 to Cx in FIG. 1) and each pixel detects electromagnetic radiation. The control circuit 102controls the pixel array 101 by generating various signals such as a shutter signal, a row select signal, and other control signals, such that each pixel in the pixel array 101 outputsa digital signal corresponding to the detected electromagnetic radiation to the readout circuit 103 via bit lines. The readout circuit 103 sends the digital signal to the signal processing circuit 104 for further processing. The pixel array maybe configured for frontside illuminations and/or backside illuminations.

FIG. 2 is a circuit diagram comprising two pixels connected via a wire according to an embodiment of the present invention. FIG. 2 illustrates further details of two pixelswhich may be a part of the pixel array 101 of FIG. 1. Elements with <n> in an upper half of FIG. 2, that is, a photodiode PD<n>, a transfer gate device TX<n>, a reset device RST<n>, a dual conversion gain device DCG<n> (which may be also referred to as a first switching device) , a floating diffusion node FD<n>, a source follower device SF<n>, and a selector (for example, a row selector device) SEL<n>, form a nth pixel (which may be referred to as a pixel unit) in the pixel array 101. Similarly, elements with <n+1> in a bottom half of FIG. 2, that is, PD<n+1>, TX<n+1>, RST<n+1>, DCG<n+1>, FD<n+1>, SF<n+1>, and SEL<n+1>, form a (n+1) th pixel in the pixel array 101. These elements forming a pixel may be referred to as pixel devices correctively. Some pixel devices such as TX, RST, DCG, SF, and SEL may be implemented by CMOS (Complementary Metal Oxide Semiconductor) transistors.

Now, the nth pixel in the upper half of FIG. 2 is described in detail. The PD<n>is connected to an AVSS1 which may be a ground or negative voltage in a range of -5.0 V to 0 V, for example. The PD<n> detects electromagnetic radiation and converts the electromagnetic radiation into electrons. The electrons stay between the PD<n> and the TX<n> unless the TX<n> is placed in a conductive state. When the TX<n> receives a transfer signal on its gate from the control circuit 102, and is placed in a conductive state (turned on) , the TX<n> transfers the electrons to the FD<n>. The FD<n> receives the electrons and accumulates charges produced by the electrons.

The FD<n> is connected to a gate of the SF<n>realizing an amplifier which amplifies a change in charges accumulated in the FD<n>. Further, a current source (Icolumn) is connected between the SEL and a ground. When the SEL<n> receives a row select signal on its gate from the control circuit 102, and is placed in a conductive state (turned on) , an output signal Vout which is a voltage corresponding to the charges accumulated in the FD<n>is transmitted to anoutput signal line Vout<m> via the SEL. Accordingly, when the gates of the TX<n> and the SEL<n> are turned on, the output signal corresponding to the electronsgenerated by the PD is obtained on the output signal line Vout<m>.

The reset device RST<n> selectively resets charges accumulated in the FD<n>when the DCG<n> is turned on, and the RST<n> receives a reset signal on its gate from the control circuit 102, and is connected (turned on) to a power supply voltage AVDD.

The DCG<n> may be connected between the RST<n> and the FD<n> and selectively may be turned on or off to switch between two types of conversion gains: one is a low conversion gain (LCG) mode for low dynamic range (LDR) realized by connecting the FD<n> and another FD, e.g., FD<n+1> in another pixel, e.g., (n+1) th pixel; andthe other one is a high conversion gain mode (HCG) for a high dynamic range (HDR) realized by disconnecting the FD<n> and other FD in other pixels.

A node 202<n> between a source terminal of the RST <n> and a drain terminal of the DCG<n> in the nth pixel may be connected to a node 202<n+1> between a source terminal of the RST <n+1> and a drain terminal of the DCG<n+1> in the (n+1) th pixel via a wire 201. The nth pixel and the (n+1) th pixel are both connected to (in other words, share) the same output signal line Vout<m>, that is, the both of these pixels output their output signals to the same output signal line Vout<m>.

A readout operation of the nth pixel is now described.

In a low conversion gain (LCG) mode of the solid-state imaging device, the SEL<n> is turned onduring the readout operation to select the nth pixel, and the RST<n> is turned on during a predetermined period at the beginning of the readout operation, to discharge the charges accumulated in the FD<n> (areset operation) . At the same time orthereafter, the DCG<n> and the DCG<n+1> are turned on to connect the FD<n> to the FD<n+1> through the DCG<n>, the node 202<n>, the wire 201, the node 202<n+1>, and the FD<n+1>. As a result, the capacity of the FD<n> is increased by a capacity of the FD<n+1>and a parasitic capacitance due to a wiring from the node 202<n>through the node 202<n+1>.

Sometimes after the reset operation, the TX<n> is turned on to transfer the electrons produced by the PD<n> to FD<n>. It should be noted that the TX<n+1> is turned off during the readout operation of the nth pixel to protect the TX<n+1> from transferring electrons produced by the PD<n+1> to FD<n>. Then, accumulated charge in the FD<n>with the capacity increased by the capacity of the FD<n+1> and the parasitic capacitance due to the wiring is converted into a voltage signal to be output to the output signal line Vout<m>.

In some embodiments, both of the SEL<n> and the SEL<n+1> may be turned on to form a parallel connection of the source follower devices (SF<n> and SF<n+1>) . This decreases random noise and random telegraph signal noise of the amplifier used in converting the charges accumulated in the FD<n> and FD<n+1> into a voltage signal to be output to the Vout<m>.

In some embodiments, other sets of pixels configured to be similar to the nth pixel and the (n+1) th pixel may be placed repeatedly in any periodic pattern in the pixel array. Some sets of pixels may be configured to be connected and output to their common output signal line (e.g., Vout<m>) , while some of other sets of pixels may be configured to be connected and output to their common output signal line (e.g., Vout<m+1>) . There may be two or more such sets of pixels and correspondingly, there may be two or more such common output signal lines. Accordingly, parallel readout operations are enabled while realizing the increased capacity of the FD.

FIG. 3A to FIG. 3C show different ways of connecting multiple pixels for parallel readout according to an embodiment of the present invention.

In some embodiments, the nth pixel may be connected to one or more pixels, in other words, the node 202<n> may be connected to one or more nodes 202 in one or more pixels in the same and/or different row and/or column. In this case, the nth pixel may operate as the nth pixel described with respect to FIG. 2, and the one or more pixels other than the nth pixel may operate as the (n+1) th pixel described with respect to FIG. 2. Reference numbers such as 202 and FD may be omitted to avoid making figures complicated.

In FIG. 3A, a nth pixel and a (n+1) th pixel are connected via a wire 301, a (n+2) th pixel and a (n+3) th pixel are connected via a wire 302, and a (n+4) th pixel and a (n+5) th pixel are connected via a wire 303. The

wires

301, 302, and 303 are equivalentto the wire 201 in FIG. 2. Each pair of connected pixels is configured in a similar manner described with respect to FIG. 2. Respective pixels connected to different output signal lines Vout<m> and Vout<m+1> may be readout in parallel.

In FIG. 3B, a nth pixel and a (n+1) th pixel are connected via a wire 301, a (n+2) th pixel and a (n+3) th pixel are connected via a wire 302, and a (n+4) th pixel and a (n+5) th pixel are connected via a wire 303. The

wires

301, 302, and 303 are equivalentto the wire 201 in FIG. 2. Each pair of connected pixels is configured in a similar manner described with respect to FIG. 2. There are three output signal lines and respective pixels connected to different output signal lines Vout<m>, Vout<m+1>, and Vout<m+2> may be readout in parallel.

In FIG. 3C, three pixels which are a nth pixel, a (n+1) th pixel, and a (n+2) th pixel are connected via a wire 304, and the other three pixels which are a (n+3) th pixel, a (n+4) th pixel and a (n+5) th pixel are connected via a wire 305. The wires 304 and 305are equivalentto the wire 201 in FIG. 2. As illustrated in FIG. 3C, the wire 304 connects three nodes: a node 202<n> between a source terminal of the RST<n> and a drain terminal of the DCG<n> in the nth pixel, a node 202<n+1> between a source terminal of the RST<n+1>and a drain terminal of the DCG<n+1> in the (n+1) th pixel, and a node 202<n+2> between a source terminal of the RST<n+2> and a drain terminal of the DCG<n+2> in the (n+2) th pixel. Also as illustrated in FIG. 3C, the wire 305 connects three nodes: a node 202<n+3>between a source terminal of the RST<n+3> and a drain terminal of the DCG<n+3> in the nth pixel, a node 202<n+4> between a source terminal of the RST<n+4> and a drain terminal of the DCG<n+4> in the (n+4) th pixel, and a node 202<n+5> between a source terminal of the RST<n+5> and a drain terminal of the DCG<n+5> in the (n+5) th pixel. Each pair of connected pixels is configured in a similar manner described with respect to FIG. 2. There are three output signal lines, and therefore, respective pixels connected to different output signal lines Vout<m>, Vout<m+1>, and Vout<m+2> may be readout in parallel. The number of output signal lines which are readout in parallel may be more than 2. The maximum number of output signal lines which are readout in parallel may depend on an implementation, configuration, or design rule.

According to the embodiments described with reference to FIG. 2 to FIG. 3C, multiple FDs in multiple pixels are connected via only a wire and there is no need to provide any specific device such as a capacitor to increase the capacity of FD. This enables an increace in a capacity of the FD whileconsuming minimal space in a limited area in the solid-state imaging device.

FIG. 4 is a circuit diagram comprising multiple pixels connected via switching devices arranged in series according to an embodiment of the present invention. The switching device also may be referred to as a second switching device or a tunable conversion gain device (TCG) , and illustrated in figures as TCG<n>, TCG<n+1>, …, and the like. Athreshold voltage of the second switching device (or TCG) may be equal to or higher than a threshold voltage of the reset device (RST) or the first switching device (DCG) such that any charges are protected from leaking to a connected pixel via the TCG.

A topology of a circuitof FIG. 4 is similar to that of FIG. 2 to FIG. 3C except for the TCGs. In addition to the pixel devices illustrated in FIG. 2 to FIG. 3C, each pixel illustrated in FIG. 4 further comprises aTCG.

A nth pixel comprises the TCG<n>, and a (n+2) th pixel comprises the TCG<n+2>. A node 202<n> between a source terminal of the RST<n> and a drain terminal of the DCG<n> in the nth pixel may be connected to a source terminal of TCG<n>, and a drain terminal of the TCG<n> may be connected to a drain terminal of TCG<n+2> in the (n+2) th pixel. Further, a source terminal of TCG<n+2> may be connected to a node 202<n+2> between a source terminal of the RST<n+2> and a drain terminal of the DCG<n+2> in the (n+2) th pixel. Consequently, the TCG<n> and the TCG<n+2> are connected in series, and when the TCG<n> and the TCG<n+2> both are turned on, the FD<n> is connected to the FD<n+2>. This increases the capacity of the FD<n>.

The nth pixel and the (n+2) th pixel are both connected to (in other words, share) the same output signal line Vout<0>, that is, the both of these pixels output their output signals to the same output signal line Vout<0>.

Similarly, a (n+1) th pixel comprises the TCG<n+1>, and a (n+3) th pixel comprises the TCG<n+3>, and the FD<n+1> is connected to the FD<n+3> through DCG<n+1>, node 202<n+1>, TCG<n+1>, TCG <n+3>, node 202<n+3>, and DCG<n+3>. Both of these pixels are connected and share the same output signal line Vout<1>.

Since each pixel comprises aTCG in addition to the DCG, the solid-device imaging device can operate in a middle conversion gain (MCG) mode which has a conversion gain between a low conversion gain (LCG) used for a high dynamic range (HDR) and a high conversion gain (HCG) used for a low dynamic range (LDR) . This allows the solid-device imaging device to be used in a wide range of applications.

FIG. 5 is a timing chart during a readout operation based on the circuit diagram shown in FIG. 4. Althoughnot shown in FIG. 5, a shutter operation is done by turning on the RST, DCG, TCG, and TX so that the charge accumulated in the PD is discharged. The nth row including the nth pixel connected to the output signal line Vout<0> and the (n+1) th row including the (n+1) th pixel connected to the output signal line Vout<1> are read at the same time, and therefore, timings charts for these rows (pixels in these rows) are the same. This means that readout operations for these rows can be done in parallel. Similarly, the (n+2) th row including the (n+2) th pixel connected to the output signal line Vout<0> and the (n+3) th row including the (n+3) th pixel connected to the output signal line Vout<1> are read at the same time, and therefore, the parallel readout can be done on these rows (pixels) .

A readout operation of the nthpixel whose FD<n> is connected to the FD<n+2> of the (n+2) the pixel is now described with a reference to FIG. 5.

In response to a row select signal SEL (n) from the control circuit 102 (FIG. 1) , a SEL<n> in the nth pixel included in the nth row is turned on during the readout operation to select the nth pixel.

In each of a low conversion gain (LCG) mode, a middle conversion gain (MCG) mode, and a high conversion gain (HCG) mode, a signal is obtained by carrying out a correlating double sampling (CDS) which uses a difference between a reset leveland a signal level, the reset level beingsampled after the reset operation and before the TX<n> is turned on, and thesignal levelbeingsampled after the TX<n> is turned off and before the SEL<n> is turned off.

In the LCG mode, the DCG<n> and the TCG<n> in the nth pixel, and the TCG<n+2> and the DCG<n+2> in the (n+2) th pixel whose FD<n+2> is connected to the FD<n> are always on. During a predetermined time period after the SEL<n> is on, the RST<n> is turned on to discharge charges accumulated in the FD<n> (areset operation) . At LCG Reset in FIG. 5, a voltage output to the output signal line Vout<0> is detected as V (LCG Reset) . This voltage level is referred to as a reset level. Next, the TX<n> is turned on for a predetermined time periodto transfer electrons produced by the PD<n> to FD<n>. At LCG Signal in FIG. 5, a voltage output to the Vout<0> is detected as V (LCG Signal) . This voltage level is referred to as a signal level. Then, a difference ΔVsignal = V (LCG Signal) -V (LCG Reset) is calculated and used to represent an intensity of electromagnetic radiation detected by the PD<n>.

In the MCG mode, the DCG<n> in the nth pixel and the DCG<n+2> in the (n+2) th pixel whose FD<n+2> is connected to the FD<n> is always on. During a predetermined time period after the SEL<n> is on, the RST<n> is turned on to discharge charges accumulated in the FD<n> (areset operation) . At MCG Reset in FIG. 5, a voltage output to the output signal line Vout<0> is detected as V (MCG Reset) . This voltage level is referred to as a reset level. Next, the TX<n> is turned on for a predetermined time period to transfer electrons produced by the PD<n> to FD<n>. At MCG Signal in FIG. 5, a voltage output to the Vout<0> is detected as V (MCG Signal) . This voltage level is referred to as a signal level. Then, a difference ΔVsignal = V (MCG Signal) -V (MCG Reset) is calculated and used to represent an intensity of electromagnetic radiation detected by the PD<n>.

In the HCG mode, the RST<n> in the nth pixel and the DCG<n+2> in the (n+2) th pixel whose FD<n+2> is connected to the FD<n>are always on and the DCG<n> is responsible for a reset operation. During a predetermined time period after the SEL<n> is on, the DCG<n> is turned on to discharge charges accumulated in the FD<n> (areset operation) . At HCG Reset in FIG. 5, a voltage output to the output signal line Vout<0> is detected as V (HCG Reset) . This voltage level is referred to as a reset level. Next, the TX<n> is turned on for a predetermined time period to transfer electrons produced by the PD<n> to FD<n>. At HCG Signal in FIG. 5, a voltage output to the Vout<0> is detected as V (HCG Signal) . This voltage level is referred to as a signal level. Then, a difference ΔVsignal = V (HCG Signal) -V (HCG Reset) is calculated and used to represent an intensity of electromagnetic radiation detected by the PD<n>.

In this way, accumulated charge in the FD<n> with the capacity increased by the capacity of the FD<n+2> and the parasitic capacitance due to the wiring between the FD<n> and the FD<n+2> is converted into a voltage signal representing an intensity of electromagnetic radiation detected by the PD<n>.

It should be noted that in any of LCG, MCG, and HCG mode, the TX<n+2> is turned off during the readout operation of the nth pixel to protect the TX<n+2> from transferring electrons produced by the PD<n+2> to FD<n+2> which is connected to the FD<n>.

FIG. 6 is a circuit diagram comprising multiple pixel devices connected via switching devices arranged in parallel according to an embodiment of the present invention. Similar to the circuit diagram illustrated in FIG. 4, each pixel illustrated in FIG. 6 further comprises aTCG in addition to the pixel devices illustrated in FIG. 2 to FIG. 3C.

A nth pixel comprises the TCG<n>, and a (n+2) th pixel comprises the TCG<n+2>. A node 202<n> between a source terminal of the RST<n> and a drain terminal of the DCG<n> in the nth pixel may be connected to a source terminal of TCG<n> and a source terminal of the TCG<n+2>. Further, a node 202<n+2> between a source terminal of the RST<n+2> and a drain terminal of the DCG<n+2> in the (n+2) th pixel may be connected to a drain terminal of TCG<n> in the nth pixel and a drain terminal of TCG<n+2> in the (n+2) th pixel. Consequently, the TCG<n> and the TCG<n+2> are connected in parallel, and when either or both of the TCG<n> and the TCG<n+2> are turned on, the FD<n> is connected to the FD<n+2>. This increases the capacity of the FD<n> and further reduces on-resistance of the TCG devices compared with the embodiment described with a reference to FIG. 4.

FIG. 7 is a circuit diagram comprising multiple pixel devices connected in a way that a source terminal of a switching device is connected to a drain terminal of another switching device according to an embodiment of the present invention. Similar to the circuit diagrams illustrated in FIG. 4 and FIG. 6, each pixel illustrated in FIG. 7 further comprises aTCG in addition to the pixel devices illustrated in FIG. 2 to FIG. 3C. A difference from FIG. 6 is that a drain terminal of the TCG<n> in the nth pixel is connected to a drain terminal of TCG<n+2> in the (n+2) th pixel in FIG. 7. Similar to the embodiments described above, this embodiment also enables any of a tunable conversion gain (that is, any of LCG/MCG/HCG modes) , an increased capacity of the FD, and a parallel readout operation, or any combination of those.

FIG. 8 is a circuit diagram comprising all the pixel devices in the same column connected via switching devices according to an embodiment of the present invention. Similar to the circuit diagrams illustrated in FIG. 4, FIG. 6 and FIG. 7, each pixel illustrated in FIG. 8 further comprises aTCG in addition to the pixel devices illustrated in FIG. 2 to FIG. 3C. The circuit diagram of FIG. 8 is relatively simple as compared toFIG. 4, FIG. 6, and FIG. 7. In FIG. 8, all the pixels in the same column are connected via the TCGs. Specifically, the TCG<n>in the nth pixel is connected between a node 202<n> anda node 202<n+1>of an adjacent pixel. This configuration is repeated throughout the same column. Consequently, the capacity of the FD is largely increased compared with the configurations in FIG. 2 to FIG. 4, and FIG. 6 to FIG. 7.

FIG. 9 is a circuit diagram comprising multiple pixel devices connected via switching devices in multiple rows and columns according to an embodiment of the present invention. Similar to the circuit diagrams illustrated in FIG. 4, FIG. 6 to FIG. 8, each pixel illustrated in FIG. 9 further comprises aTCG in addition to the pixel devices illustrated in FIG. 2 to FIG. 3C. FIG. 9 shows 16 pixels arranged in 4 rows and 4 columns which may be a part of the pixel array 101.

Referring to the leftmost column near the output signal lines Vout<n> and Vout<n+1>, a node 202<n> between the RST<n> and the DCG<n> is connected to a source terminal of the TCG<n> of the nth pixel. A drain terminal of the TCG<n> is connected to a node 202<n+2> and a source terminal of the TCG<n+2> of the (n+2) th pixel. Referring to a second column from the left near output signal lines Vout<n+2> and Vout<n+3>, a nth pixel and a (n+2) th pixel are connected in a similar way to those in theleftmost column. Further, a drain terminal of the TCG<n+2>in the leftmostcolumn is connected to a source terminal of a TCG<n+2> in a different column, that is, thethird column from the left. Consequently, 4 pixels are connected via their TCGs, and by turning on all of these TCGs, 4 FDs are connected to increase the capacity of FD.

There are other sets of 4 pixels which are connected via TCGs. For example, a nth pixel and a (n+2) th pixel in a second column from the left and a (n+1) th pixel and a (n+3) th pixel in a third column from the left are connected together. A (n+1) th pixel and a (n+3) th pixel in a second column from the left and a (n+1) th pixel and a (n+3) th pixel in a fourth column from the left are connected together.

It is noted that pixels which are connected via TCGs and are located in the same column should be connected to the same signal output line. For example, the nth pixel and the (n+3) th pixel in the leftmost column are connected to the same signal output line Vout<n+1>. It is also noted that only one TX of one of the pixels whose FDs are connected is turned on and the remaining TXs of the remaining pixels are turned off, during a readout operation of the one of the pixels.

Although the number of pixels connected is only four in this embodiment, the number of pixels connected may vary depending on implementation.

The pixels thatare connected via the TCGs may be applied with the same color of filter. As a result, a pixel binning in a charge domain can be performed on the same color of pixels with an increased capacity of the FD. What colors are used, how many colors are used, and what color pattern is used may vary depending on implementations.

FIG. 10 is a circuit diagram comprising four sets of photodiodes and transfer devices share pixel devices according to an embodiment of the present invention. 4 FDs, 4 corresponding TX1 to TX4, corresponding RST, DCG, SEL, and TCG form a pixel unit. In other words, a pixel unit includes a plurality of pixels (each pixel corresponds to one PD) , 4 pixels in this embodiment, and the plurality of pixels share pixel devices except for TX.

A pixel unit shown on the top in FIG. 10 is connected to a third pixel unit from the top. Specifically, a node 202<n>in the pixel unit on the top is connected to a source terminal of the TCG<n>, a drain terminal of the TCG<n> is connected to a drain terminal of the TCG<n+2> of the third pixel from the top. The similar pattern may be repeated in the pixel array 101 of FIG. 1. In this embodiment, since some of pixel devices such as RST, DCG, SEL, and TCG are shared within a pixel unit, the number of pixels to be implemented in the pixel array 101 in the solid-state imaging device 100 can be increased while the capacity of the FDs is also increased.

FIG. 11 is a circuit diagram in which the embodiment shown in FIG. 10 is applied to a quad Bayer color filter pattern. For example, a green filter may be applied to

pixel units

1101, 1103 whose FDs are connected, and

pixel units

1106, 1108 whose FDs are connected. A red filter may be applied to

pixel units

1105, 1107 whose FDs are connected, and a blue filter may be applied to pixel units 1102, 1104whose FDs are connected. These patterns may be repeated in the pixel array 101. As a result, a RGGB Bayer color filter pattern in which each pixel unit comprises 4 pixels is implemented. In other example, a RGGB Bayer color filter pattern in which each pixel unit comprises 9 or more pixels may be implemented. An RGB color filter is only an example, and it is possible to use any other color filter such as CYGM (Cyan, Yellow, Green, and Magenta) , RGBE (Red, Green, Blue, and Emerald) filter, or any other color filters existing or to be developed in the future.

FIG. 12 is a top view of an example circuit layout formed on a semiconductor substrate for a pixel unit comprising a photodiode according to an embodiment of the present invention. The circuit layout shown in FIG. 12 corresponds to the circuit diagrams shown in FIG. 2 to FIG. 4 and FIG. 6 to FIG. 9, in which each pixel comprises one FD and one TX and corresponding pixel devices. As shown in FIG. 12, a source terminal or a drain terminal of the DCG and a source terminal or a drain terminal of the TCG may share an active area. There may be a single SF or a plurality of SFs connected in series or in parallel. The AVSS1 may be located inside or outside the PD. Any of nodes shown in FIG. 12 may be isolated from its surrounding material/components/devicesusing a STI (Shallow trench isolation) or a p-n junction isolation.

FIG. 13 is a top view of an example circuit layout formed on a semiconductor substrate for a pixel unit comprising four photodiodes according to an embodiment of the present invention. A difference from FIG. 12 is that the circuit layout shown in FIG. 13 corresponds to the circuit diagrams shown in FIG. 10 to FIG. 11, in which each pixel unit comprises 4 FDs and corresponding 4 TXs and corresponding pixel devices, and the pixel devices are shared within the pixel unit.

FIG. 14 is a top view of an example circuit layout in which a switching device is placed isolatedly according to an embodiment of the present invention. A difference from FIG. 13 is that the TCG is placed isolatedly from other pixel devices such as the DCG, RST, SF, and SEL in the circuit layout shown in FIG. 14. In this embodiment, since the TCG does not share an active area with other pixel devices, a size (alength or a width) of the TCG may be equal to or less than that of the DCG, the RST, the SF, and/or the SEL. In an example, a gate length of the TCG may be equal to or shorter than that of the SF. In another example, a gate width of the TCG may be equal to or shorter than that of the SF. Accordingly, the TCG can besmaller than that in FIG. 13. As a result, the space used for implementing the pixel array can be reduced.

FIG. 15 is a circuit diagram in which shielding among wires between switching devices are added to the embodiment shown in FIG. 4 according to an embodiment of the present invention. In this embodiment, vertical wires are shielded. For example, a wire connecting the nth pixel and the (n+2) th pixel is shielded by

shields

1501 and 1502, and a wire connecting the (n+1) th pixel and the (n+3) th pixel is shielded by

shields

1502 and 1503. In this embodiment, the wires connecting TCGs (or nodes 202) are protected against various potentials such as AVSS1which is the same as a pixel well voltage, AVSS2, ground, AVDD, or any other fixed voltage, and further electrical crosstalk among pixels can be reduced. Shielding wires may be placed on the same level as the wiring from a TCG to other TCG (or a node 202 to other node 202) , such as in any metal layer in a semiconductor chip on which the solid-state imaging device is implemented.

FIG. 16 is a top view of an example circuit layout for the circuit diagram shown in FIG. 15 according to an embodiment of the present invention. Shields may be added as needed. For example, when the circuit diagram shown in FIG. 9 is used, vertical shields may be added in the same metal layer as the shields shown in FIG. 15 or any other metal layers.

FIG. 17 is a cross-sectional view of a part of a pixel array according to an embodiment of the present invention. This embodiment shows backside deep trench isolation (DTI) . In other embodiments, a frontside DTI may be used. A color filter is placed under a microlens, a PD is implemented under the color filter, and a TX is placed near the PD.Other pixel devices may be implemented on the same layer (layer 1) as the TX or any other layers. The control circuit 102, readout circuit 103, and signal processing circuit 104 also may be implemented on the same layer (layer 1) as the TX or any other layers. Any other layouts are possible depending on implementations.

FIG. 18 is schematic diagrams of a solid-sate imaging device according to an embodiment of the present invention. The A to E in FIG. 18 are schematic diagrams illustrating the solid-state imaging device according to the embodiment of the present invention.

First, a typical solid-state imaging device will be described with reference to A in FIG. 18. The typical solid-state imaging device includes a pixel array, a control circuit, and a signal processing circuit, which are mounted on a single semiconductor chip. In general, a solid-state imaging device includes the pixel array and the control circuit. The pixel array may be illuminated on its frontside, or may be illuminated on its backside. The semiconductor substrate may consist of semiconductor material such as silicon or germanium. In some embodiments, the substrate may consist of at least one or more of other radiation sensitive materials, such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium, antimonide, semiconductor on insulator or combinations thereof.

As shown in B in FIG. 18, in contrast to the above, a solid-state imaging device according to the embodiment of the present invention includes a pixel array and a control circuit mounted on a first semiconductor chip section and a signal processing circuit mounted on a second semiconductor chip section. The first semiconductor chip section and the second semiconductor chip section are electrically connected to each other, and can form a single semiconductor chip of the solid-state imaging device.

As shown in C in FIG. 18, in a solid-state imaging device according to another embodiment of the present invention, a pixel array is mounted on a first semiconductor chip section. Also, a control circuit and a signal processing circuit are mounted on a second semiconductor chip section. The first semiconductor chip section and the second semiconductor chip section are electrically connected to each other, and can form a single semiconductor chipof the solid-state imaging device.

As shown in D in FIG. 18, in a solid-state imaging device according to another embodiment of the present invention, a pixel array is mounted on a first semiconductor chip section. Also, a memory circuit ismounted on a second semiconductor chip section. Then, a control circuit and a signal processing circuit are mounted on a third semiconductor chip section. The first semiconductor chip section and the second semiconductor chip section and the third semiconductor chip section are electrically connected, and can form a single semiconductor chip or two semiconductor chips ofthe solid-state imaging device.

As shown in E in FIG. 18, in a solid-state imaging device according to another embodiment of the present invention, a pixel array is mounted on a first semiconductor chip section. Also, a pixel circuit ismounted on a second semiconductor chip section. Then, a control circuit and a signal processing circuit are mounted on a third semiconductor chip section. The first semiconductor chip section, the second semiconductor chip section, and the third semiconductor chip section are electrically connected, and can form a single semiconductor chip or two semiconductor chips of the solid-state imaging device.

Although not illustrated in figures, an embodiment of the present invention further provides an image sensor. The image sensormay comprise the solid-state imaging device 100 of FIG. 1, a lens, an aperture partwhich may be located between the lens and the solid-state imaging device 100 and may be controlled by the control circuit 102, a memory for storing data from the signal processing circuit 104, and any other devices needed for operating the image sensor.

An embodiment of the present invention further provides a method for driving the solid-state imaging device 100 according to the present invention. The solid-state imaging device 100 may comprise a pixel array 101 in which one or more pixels form a pixel unit. Each of the pixel units may comprise: one or more photodiodes (PD) for converting electromagnetic radiationinto an electrical charge; one or more transfer gate devices (TX) each corresponding to each of the one or more photodiodes (PD) , and for selectively transferring the electrical charge; a floating diffusion (FD) for accumulating the electrical charge transferred from the one or more transfer gate devices (TX) ; a selector (SEL) for selectively outputting an output signal corresponding to the electrical charge accumulated in the floating diffusion (FD) ; a first switching device (DCG) selectively switchingbetweentwo types of conversion gain; anda reset device (RST) connected to a power supply voltage (AVDD) , and for selectively resetting the electrical charge accumulated in the floating diffusion (FD) . A first node (202<n>) between the first switching device (DCG) and the reset device (RST) in a first pixel unit is connected to one or more second nodes (202<n+1>, 202<n+2>, or the like, depending on embodiments) between the first switching device (DCG) and the reset device (RST) in one or more second pixel units.

The method may be performed by the control circuit 102 of the solid-state imaging device 100. The method may comprise the following steps.

Step 1: Turning off the transfer device (TX) and the reset device (RST) in each of the one or more second pixel units throughout a first period in which a readout operation of the first pixel unit is performed.

Step 2: Turning on the first switching device (DCG) in the one or more second pixel units, throughout a first predetermined period that begins after the first period begins and ends beforethe first periodends.

Each of the pixel units may further comprises a second switching device (TCG) connected between the first node (202<n>) and the second node (202<n+1>, 202<n+2>, or the like, depending on embodiments) in one of the one or more second pixel units. The method may further comprise the following step.

Step 3: Turning on the second switching devices (TCG) in the first pixel unit and the one or more second pixel units during the first predetermined period.

Step 4:

in a high conversion gain mode, turning on the reset device (RST) in the first pixel unit throughout the first period, and resetting the electrical charge accumulated in the floating diffusion (FD) by turning on the first switching device (DCG) in the first pixel unit;

in a middle conversion gain mode, turning on the first switching device (DCG) in the first pixel unit throughout the first period, and resetting the electrical charge accumulated in the floating diffusion (FD) by turning on the reset device (RST) in the first pixel unit; and

in a low conversion gain mode, turning on the first switching device (DCG) and the one or more second switching devices (TCG) in the first pixel unit throughout the first period, and resetting the electrical charge accumulated in the floating diffusion (FD) by turning on the selectors (SEL) in the one or more second pixel units. In the above descriptions, the embodiment was described using an example in which pixel charges each stored in each of all the pixels included in the pixel array 101 are sequentially read out by using the row selectors (SEL) , and the data is read out as a frame composed of all the pixels in the pixel array 101. In another embodiment, instead of reading out the data as a frame, an “event driven” type of an image sensor may be implemented by using the solid-state imaging device according to the present invention. The event driven type of the image sensor may output data in an asynchronous way, in other words, at any time in response to changes in the intensity of electromagnetic radiation incident on one or more pixels. Specifically, for example, if pixel charges generated by electromagnetic radiation incident on one or more photodiodes (PD) (or one or more pixels) and stored in the one or more photodiodes (PD) exceed a predetermined threshold value, an event of anintensity of the electromagnetic radiation exceeding the threshold value or data representing the intensity of the electromagnetic radiation may be output along with coordinates of the one or more pixels (for example, x and y coordinates in the pixel array 101) and timing information.

FIG. 11 is a diagram illustrating an exemplary configuration of an electronic apparatus 1900 having an imaging element 1902 to which the present technology is applied. The electronic device 1900 is, for example, an imaging device such as a digital still camera and a video camera, a mobile terminal device such as a smartphone and a tablet type terminal, and the like.

In FIG. 19, the electronic device 1900 includes a lens 1901, an imaging element 1902, a digital signal processing (DSP) circuit 1903, a frame memory 1904, a display unit 1905, a recording unit 1906, an operation unit 1907, and a power source unit 1908. Furthermore, in the electronic device 1900, the DSP circuit 1903, the frame memory 1904, the display unit 1905, the recording unit 1906, the operation unit 1907, and the power source unit 1908 are connected to each other via a bus line 1909.

For example, the imaging element 1902 corresponds to the solid-stateimaging device 100 (FIG. 1) . The DSP circuit 1903 is a camera signal processing circuit for processing a signal supplied from the imaging element 1902. The DSP circuit 1903 outputs image data obtained by processing the signal from the imaging element 1902. The frame memory 1904 temporarily holds the image data processed by the DSP circuit 1903 in frame units. The display unit 1905 includes, for example, a panel type display device such as a liquid crystal panel and an organic Electro Luminescence (EL) panel and displays a moving image or a still image imaged by the imaging element 1902. The recording unit 1906 records the image data of the moving image or the still image imaged by the imaging element 1902 to a recording medium such as a semiconductor memory or a hard disk.

The operation unit 1907 outputs an operation instruction regarding various functions of the electronic device 1900 according to a user's operation. The power source unit 1908 appropriately supplies various power sources to be an operation power source of the DSP circuit 1903, the frame memory 1904, the display unit 1905, the recording unit 1906, and the operation unit 1907 to these components which are supply targets.

FIG. 20 shows examples of technologies to which the present technology is applied. For example, an electronic apparatus, an image sensor, or any other devicescomprising the solid-state imaging device 100 (or an electronic apparatus, an image sensor, or any other devicescomprising the solid-state imaging device 100 according to the present invention may be applied to a wide variety of technologies. For example, the solid-state imaging device 100 may be applied to a wide variety of fields including sport gear such as a wearable camera; medical devices such as an endoscope; cosmetic equipment; vehicles or transport equipment such as a truck; equipment for driving support or autonomous/automatic driving; entertainment devices such as a mobile phone, a game console, a digital camera, and a video camcorder; the agricultural field such as a farmland surveillance camera; home appliances such as a television and a refrigerator; the security field such as a monitoring camera, a network camera, a machine vision camera, a broadcast camera, a disaster notification system such as a river/dam/ocean/road/construction site monitoring camera; and any other fields.

The embodiments according to the present invention provide many beneficial effects and advantages. Some are listed below.

A dynamic range in a pixel binning mode improves because a floating capacitance increases.

A signal-to-noise ratio in a pixel binning mode improves because a photon shot noise is reduced.

A random telegraph signal noise in a pixel binning mode improves because an effective source follower noise is reduced.

Signal crosstalk among different FD nodes is suppressed by a TCG.

Compatible with a parallel readout mode (readout of at least two rows in parallel) .

A TCG does not directly connect to a floating diffusion, and thusthe TCG does not increase a parasitic capacitance of the floating diffusion node, meaning that there is no sacrifice for an HCG mode.

Three different conversion gains realize a high dynamic operation with a single exposure.

An area advantage because a large capacitance device is not necessary.

In this application, the embodiments each may be implemented partly or completely in a form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instruction is loaded and executed on a computer, some or all of the procedures or functions according to the embodiments of this application are generated. The computer may be a controller included in a solid-state imaging device, an image sensor, or an electronic apparatus, a general-purpose computer, a special purpose computer, a computer network, or another programmable apparatus. The computer instruction may be stored in a computer-readable storage medium, or may be transmitted from a computer-readable storage medium to another computer-readable storage medium. For example, the computer instruction may be transmitted from a website, computer, server, or data center to another website, computer, server, or data center in a wired (for example, a coaxial cable, an optical fiber, or a digital subscriber line (DSL) ) or wireless (for example, infrared, radio, or microwave) manner. The computer-readable storage medium may be any usable medium accessible by a computer, or a data storage device, such as a server or a data center, integrating one or more usable media. The usable medium may be a magnetic medium (for example, a floppy disk, a hard disk, or a magnetic tape) , an optical medium (for example, a DVD) , a semiconductor medium (for example, a solid-state drive/Solid State Disk (SSD) ) , or the like. The storage medium may be integrated into a specific device, module, or processor, or may be separately disposed.

Obviously, a person skilled in the art may make various modifications and variations to this application without departing from the scope of this application. In this way, this application is also intended to cover these modifications and variations of this application provided that these modifications and variations fall within the protection scope defined by the following claims and their equivalent technologies.

Claims

A solid-state imaging device comprising:

a pixel array in which one or more pixels form a pixel unit, wherein

each pixel unit comprises:

one or more photodiodes toconvert electromagnetic radiation into an electrical charge;

one or more transfer gate devices each corresponding to oneof the one or more photodiodes, and toselectively transfer the electrical charge;

a floating diffusion toaccumulate the electrical charge transferred from the one or more transfer gate devices;

a selector toselectively output an output signal corresponding to the electrical charge accumulated in the floating diffusion;

a first switching device toselectively switch between two types of conversion gain; and

a reset device connected to a power supply voltage, and toselectively reset the electrical charge accumulated in the floating diffusion;

wherein a first node between the first switching device and the reset device in a first pixel unit is connected to one or more second nodes between afirst switching device and areset device in one or more second pixel units.
The solid-state imaging device according to claim 1, wherein the first pixel unit and the one or more second pixel units thatare connected to the first pixel unit share an output signal line.
The solid-state imaging device according to claim 1 or 2, wherein the transfer device and the reset device in each of the one or more second pixel units are turned off throughout a first period in which a readout operation of the first pixel unit is performed.
The solid-state imaging device according to claim 3, wherein the first switching device in the one or more second pixel units is turned on, throughout a first predetermined period that begins after the first period begins and ends before the first period ends.
The solid-state imaging device according to claim 4, wherein each of the pixel units further comprises:

a second switching device connected between the first node and the second node in one of the one or more second pixel units;

wherein the second switching devices in the first pixel unit and the one or more second pixel units are turned on throughout the first predetermined period.
The solid-state imaging device according to claim 5, wherein a threshold voltage of the second switching device is equal to or higher than a threshold voltage of the reset device or the first switching device.
The solid-state imaging device according to claim 5 or 6, wherein,

in a high conversion gain mode, the reset device in the first pixel unit is turned on throughout the first period, and the electrical charge accumulated in the floating diffusion is reset by turning on the first switching device in the first pixel unit;

in a middle conversion gain mode, the first switching device in the first pixel unit is turned on throughout the first period, and the electrical charge accumulated in the floating diffusion is reset by turning on the reset device in the first pixel unit; and

in a low conversion gain mode, the first switching device and the one or more second switching devices in the first pixel unit are turned on throughout the first period, and the electrical charge accumulated in the floating diffusion is reset by turning on the selectors in the one or more second pixel units.
The solid-state imaging device according to claim 7, wherein in the LCG mode and in the MCG mode, all or some of the one or more selectors in the one or more second pixel units are turned on throughout a first predetermined period that begins after the first period begins and ends before the first period ends.
The solid-state imaging device according to any one of claims 5 to 7,

wherein the second switching device in the first pixel unit and the second switching devices in the one or more second pixel units are connected in series; or

wherein the second switching device in the first pixel unit and the second switching devices in the one or more second pixel units are connected in parallel.
The solid-state imaging device according to any one of claims 1 to 9,

wherein the first pixel unit is arranged in asame row as and a different column from the one or more second pixel units; or

wherein the first pixel unit is arranged in a different row from and asame column as the one or more second pixel units; or

wherein the first pixel unit is arranged in a different row from and a different column from the one or more second pixel units.
The solid-state imaging device according to any one of claims 1 to 10, wherein the first pixel unit and the one or more second pixel units are arranged consecutively in asame row or in asame column.
The solid-state imaging device according to any one of claims 1 to 10, wherein the first pixel unit and the one or more second pixel units are arranged at regular intervals in asame row or in asame column.
The solid-state imaging device according to any one of claims 1 to 12, wherein the pixel units are arranged in a Bayer color filter pattern, and wherein the first pixel unit and the one or more second pixel units have asame color filter.
The solid-state imaging device according to any one of claims 1 to 13, wherein the source terminal or the drain terminal of the second switching device shares an active area with the source terminal or the drain terminal of the first switching device.
The solid-state imaging device according to any one of claims 1 to 13, wherein a length or a width of the second switching device is equal to or less than a length or a width of one or more of the first switching device, the reset device, and the selector.
The solid-state imaging device according to any one of claims 1 to 15, further comprising one or more shielding elements among a wire connecting the first node and the one or more second nodes in one set of the first pixel unit and the one or more second pixel units, a wire connecting the first node and the one or more second nodes in one or more other sets of the first pixel unit and the one or more second pixel units, the power supply voltage, a ground voltage, and an output voltage.
An image sensor comprising the solid-state imaging device according to any one of claims 1 to 16.
Anelectronic apparatus comprising the solid-state imaging device according to any one of claims 1 to 16.
A method for driving a solid-state imaging device comprising:

a pixel array in which one or more pixels form a pixel unit, wherein

each pixel unit comprises:

one or more photodiodes toconvert electromagnetic radiationinto an electrical charge;

one or more transfer gate devices each corresponding to oneof the one or more photodiodes, and toselectively transfer the electrical charge;

a floating diffusion toaccumulate the electrical charge transferred from the one or more transfer gate devices;

a selector to selectively output an output signal corresponding to the electrical charge accumulated in the floating diffusion;

a first switching device to selectively switch between two types of conversion gain; and

a reset device connected to a power supply voltage, and to selectively reset the electrical charge accumulated in the floating diffusion;

wherein a first node between the first switching device and the reset device in a first pixel unit is connected to one or more second nodes between afirst switching device and areset device in one or more second pixel units;

the method comprising:

turning off the transfer device and the reset device in each of the one or more second pixel units throughout a first period in which a readout operation of the first pixel unit is performed;

turning on the first switching device in the one or more second pixel units, throughout a first predetermined period that begins after the first period begins and ends before the first period ends.
The method according to claim 19, wherein each of the pixel units further comprises:

a second switching device connected between the first node and the second node in one of the one or more second pixel units;

the method further comprising:

turning on the second switching devices in the first pixel unit and the one or more second pixel units throughout the first predetermined period.
The method according to claim 20 further comprising:

in a high conversion gain mode, turning on the reset device in the first pixel unit throughout the first period, and resetting the electrical charge accumulated in the floating diffusion by turning on the first switching device in the first pixel unit;

in a middle conversion gain mode, turning on the first switching device in the first pixel unit throughout the first period, and resetting the electrical charge accumulated in the floating diffusion by turning on the reset device in the first pixel unit; and

in a low conversion gain mode, turning on the first switching device and the one or more second switching devices in the first pixel unit throughout the first period, and resetting the electrical charge accumulated in the floating diffusion by turning on the selectors in the one or more second pixel units.