HK1178989A1 - A method of and an arrangement for automatically measuring electric connections of electronic circuit arrangements mounted on printed circuit boards pcb - Google Patents

A method of and an arrangement for automatically measuring electric connections of electronic circuit arrangements mounted on printed circuit boards pcb

Info

Publication number
HK1178989A1
HK1178989A1 HK13105737.2A HK13105737A HK1178989A1 HK 1178989 A1 HK1178989 A1 HK 1178989A1 HK 13105737 A HK13105737 A HK 13105737A HK 1178989 A1 HK1178989 A1 HK 1178989A1
Authority
HK
Hong Kong
Prior art keywords
arrangement
electric connections
automatically measuring
measuring electric
printed circuit
Prior art date
Application number
HK13105737.2A
Other languages
English (en)
Chinese (zh)
Inventor
Den Van Eijnden
Petrus Marinus
Cornelis Maria
Original Assignee
Jtag Technologies Bv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jtag Technologies Bv filed Critical Jtag Technologies Bv
Publication of HK1178989A1 publication Critical patent/HK1178989A1/xx

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318536—Scan chain arrangements, e.g. connections, test bus, analog signals
    • G01R31/318538—Topological or mechanical aspects
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318544—Scanning methods, algorithms and patterns
    • G01R31/31855—Interconnection testing, e.g. crosstalk, shortcircuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test input/output devices or peripheral units
HK13105737.2A 2011-05-10 2013-05-14 A method of and an arrangement for automatically measuring electric connections of electronic circuit arrangements mounted on printed circuit boards pcb HK1178989A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL2006759A NL2006759C2 (en) 2011-05-10 2011-05-10 A method of and an arrangement for automatically measuring electric connections of electronic circuit arrangements mounted on printed circuit boards.

Publications (1)

Publication Number Publication Date
HK1178989A1 true HK1178989A1 (en) 2013-09-19

Family

ID=46017756

Family Applications (1)

Application Number Title Priority Date Filing Date
HK13105737.2A HK1178989A1 (en) 2011-05-10 2013-05-14 A method of and an arrangement for automatically measuring electric connections of electronic circuit arrangements mounted on printed circuit boards pcb

Country Status (6)

Country Link
US (1) US8775883B2 (fr)
EP (1) EP2523114B1 (fr)
JP (1) JP6050025B2 (fr)
CN (1) CN102778629B (fr)
HK (1) HK1178989A1 (fr)
NL (1) NL2006759C2 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10866283B2 (en) * 2018-11-29 2020-12-15 Nxp B.V. Test system with embedded tester
US11293979B2 (en) * 2019-10-22 2022-04-05 Peter Shun Shen Wang Method of and an arrangement for analyzing manufacturing defects of multi-chip modules made without known good die

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62280667A (ja) * 1986-05-30 1987-12-05 Omron Tateisi Electronics Co 故障診断装置
US5202625A (en) * 1991-07-03 1993-04-13 Hughes Aircraft Company Method of testing interconnections in digital systems by the use of bidirectional drivers
US5448166A (en) 1992-01-03 1995-09-05 Hewlett-Packard Company Powered testing of mixed conventional/boundary-scan logic
US5471481A (en) 1992-05-18 1995-11-28 Sony Corporation Testing method for electronic apparatus
GB9217728D0 (en) * 1992-08-20 1992-09-30 Texas Instruments Ltd Method of testing interconnections between integrated circuits in a circuit
US5497378A (en) 1993-11-02 1996-03-05 International Business Machines Corporation System and method for testing a circuit network having elements testable by different boundary scan standards
US5448525A (en) 1994-03-10 1995-09-05 Intel Corporation Apparatus for configuring a subset of an integrated circuit having boundary scan circuitry connected in series and a method thereof
CA2213966C (fr) 1995-12-27 2004-10-26 Koken Co., Ltd. Dispositif de controle
US5717701A (en) * 1996-08-13 1998-02-10 International Business Machines Corporation Apparatus and method for testing interconnections between semiconductor devices
US5757820A (en) * 1997-01-17 1998-05-26 International Business Machines Corporation Method for testing interconnections between integrated circuits using a dynamically generated interconnect topology model
US6622108B1 (en) 1998-02-02 2003-09-16 Koninklijke Philips Electronics N.V. Circuit with interconnect test unit and a method of testing interconnects between a first and a second electronic circuit
US6389565B2 (en) 1998-05-29 2002-05-14 Agilent Technologies, Inc. Mechanism and display for boundary-scan debugging information
US6634005B1 (en) 2000-05-01 2003-10-14 Hewlett-Packard Development Company, L.P. System and method for testing an interface between two digital integrated circuits
CN1180270C (zh) * 2001-09-12 2004-12-15 明基电通股份有限公司 检查多层印刷电路板内层短路的方法
US6988229B1 (en) * 2002-02-11 2006-01-17 Folea Jr Richard Victor Method and apparatus for monitoring and controlling boundary scan enabled devices
US7055113B2 (en) 2002-12-31 2006-05-30 Lsi Logic Corporation Simplified process to design integrated circuits
EP1595156B1 (fr) 2003-02-10 2006-11-29 Koninklijke Philips Electronics N.V. Test de circuits integres
JP2005214957A (ja) * 2004-02-01 2005-08-11 Ryuji Naito バウンダリスキャン可視化方法
TWI320485B (en) * 2007-03-08 2010-02-11 Test Research Inc Open-circuit testing system and method
US7737701B2 (en) * 2007-09-26 2010-06-15 Agilent Technologies, Inc. Method and tester for verifying the electrical connection integrity of a component to a substrate
EP2344897B1 (fr) * 2008-11-14 2015-06-17 Teradyne, Inc. Procédé et appareil pour tester les connexions électriques sur une carte de circuit imprimé
NL1037457C2 (en) * 2009-11-10 2011-05-12 Jtag Technologies Bv A method of and an arrangement for testing connections on a printed circuit board.
WO2012053063A1 (fr) * 2010-10-19 2012-04-26 富士通株式会社 Circuit intégré et procédé d'essai

Also Published As

Publication number Publication date
US8775883B2 (en) 2014-07-08
CN102778629A (zh) 2012-11-14
NL2006759C2 (en) 2012-11-13
JP6050025B2 (ja) 2016-12-21
EP2523114B1 (fr) 2014-06-11
US20120290890A1 (en) 2012-11-15
EP2523114A1 (fr) 2012-11-14
CN102778629B (zh) 2016-09-07
JP2012237756A (ja) 2012-12-06

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