HK1069004A - System for and method of four-conductor magnetic random access memory cell and decoding scheme - Google Patents

Description

System and method for four-wire magnetic random access memory unit and decoding scheme

RELATED APPLICATIONS

This application is related to commonly assigned U.S. patent application serial No. attorney docket No.100203976-1 entitled system and method for accessing magnetic random access memory, filed on even date herewith, the disclosure of which is hereby incorporated by reference.

Technical Field

The present invention relates to memory devices for general purpose computer applications, and more particularly to an increase in the area efficiency ratio of magnetic random access memory for general purpose computer applications.

Background

Magnetic Random Access Memory (MRAM) may be used to store information encoded as one or more bits in a binary representation for subsequent retrieval and use. While conventional memory technologies such as flash memory, Static Random Access Memory (SRAM), and Dynamic Random Access Memory (DRAM) utilize stored charges or flip-flops to store information, MRAM may utilize magnetization to indicate the presence of a stored "1" or a stored "0". Two main types of cell structures can be used to implement MRAM, resistive cross point arrays and three-conductor memory cell arrays.

The simplest form of a resistive cross-point memory array is the two-wire memory cell structure shown in fig. 1. In this configuration, each MRAM cell is connected in parallel with each other cell in the array.

Referring to fig. 1, a resistive cross-point array includes an array of rows (X-direction) of metal conductors constituting word lines 101 and columns of metal conductors (Y-direction) forming bit lines 102. An MRAM cell, or MRAM "bit" 103, is located at each vertical intersection of a word line and a bit line. MRAM is typically composed of thousands or millions of MRAM cells. MRAM can also divide MRAM cells into groups or blocks.

Each MRAM cell 103 is typically comprised of at least five layers. These layers include first and second conductive lines, first and second magnetic layers, and a high resistance thin film spacer or medium located intermediate the first and second magnetic layers. The first conductive line is part of the bit line 102. The first magnetic layer 104 is electrically connected to the first conductive line and is typically made primarily of a nickel-iron alloy or a nickel-iron-cobalt alloy, and may include a crystalline structure and possibly other components, other elements, or compounds. The first magnetic layer may be a free ferromagnetic layer, referred to as the free layer, the data layer, or the soft layer. The second conductive line may be a portion of the word line 101. Second magnetic layer 105 is electrically connected to the second conductive line and may also have a nickel-iron primary composition, including crystalline structures and other elements that may be different from the first magnetic layer. The second magnetic layer 105 may be a pinned layer, referred to as a pinned layer, pinning layer, or reference layer. The second magnetic layer 105 may have slightly different characteristics than the first magnetic layer 104. A high resistance thin film spacer layer or medium 106 is located between the first and second magnetic layers.

The magnetization in the data layer can be established by an induced magnetic field caused by a current flowing through the respective conductor. The strength and/or direction of the induced magnetic field can be varied by varying the strength or direction of the current flowing through the respective wires. The resulting magnetic field may be a function of the current flowing through the word line (row conductor) that establishes the first magnetic field and the current flowing through the bit line (column conductor) that establishes the second magnetic field. To store a value in the data layer, the vector sum of the two magnetic fields caused by the currents through the word and bit lines must be large enough to overcome the coercivity of the data layer in order to change the magnetization direction of the data layer. In addition, the currents in the word and bit lines must be small enough to ensure that the magnetic field established does not affect the value stored by the nearby MRAM cell. In contrast to a selected MRAM bit, which receives a magnetic field induced by both the selected bit line and the selected word line, when the MRAM cell is exposed to a magnetic field induced by either the word line or the bit line (as opposed to both the word line and the bit line), the state is referred to as a half-selected state.

Writing to a memory cell in the cell structure requires a relatively high magnetic field. Writing information into an MRAM cell requires that current flow through both the word line and the bit line of the selected memory cell. The current flowing through the bit line 102 creates a magnetic field around the bit line. Similarly, current flowing through word line 107 creates a magnetic field around the word line. The magnetic field in the free, data, or soft layers may be established by an induced magnetic field generated by coupling currents flowing through the respective conductors. The strength and/or direction of the induced magnetic field may be varied by varying the strength or direction of the current flowing through the respective wires. Specifically, the magnetization on each side of the medium 106 affects the tunneling current (leakage current) through the medium of the MRAM cell. The current in the bit line in the direction of arrow 108 and the current in the word line 107 in the direction of arrow 109 are added, causing magnetization of the free layer in the MRAM cell 103. The current in the bit line induces a magnetic field in a direction called the easy axis and the current in the word line induces a magnetic field in a direction called the hard axis. When a read voltage is applied across a selected MRAM cell from a bit line to a word line, a tunneling current flows through the barrier layers of the MRAM cell, the strength of the current depending on the relative direction of magnetization between the free magnetic layer and the fixed magnetic layer.

When a current in the direction 108 is present in the bit line 102 and a current in the direction 109 is present on the word line 107, a magnetic field is induced in the data layer, resulting in a magnetization in the same direction as the magnetic field in the fixed layer, and the two magnetizations are then parallel and the resistance of the memory cell is a first value. Such a configuration may be used to represent, for example, a stored "1". Conversely, when the direction of current flow 110 in the bit line 102 and word line 101 induces a magnetic field in the data layer, causing a magnetization in the opposite direction to that of the fixed layer magnetic field, the two magnetizations are antiparallel and the resistance of the memory cell is a second value slightly greater than the first value. This configuration may be used to represent a stored "0".

As described above, the memory state is determined by the resistive state of the selected MRAM cell, which in turn is determined by the magnitude of the current flowing between the selected word line and the selected bit line. For example, parallel magnetization states produce a current that is greater than the current of the anti-parallel state. A higher current level indicates that the magnetization direction in the free layer is the same as the magnetization direction of the fixed magnetic layer (referred to as the parallel state), which may represent a stored "1", while a lower current level indicates the anti-parallel state, which is opposite the magnetization direction of the fixed magnetic layer, which may represent a stored "0". No isolation devices are included in the resistive cross-point array to isolate the memory cells from each other. This requires that the sensing scheme include adjustments to compensate for the parallel nature of the memory cells. One type of detection is equipotential isolation.

An MRAM cell array that includes common read and write bit line conductors and common read and write word line conductors is referred to as a two-conductor MRAM cell array. In a two-wire cell array, there is one set of write circuits for each group or "block" of memory cells. A memory cell block includes, for example, one to two thousand rows and 500 to 4000 columns. For each block, write current drive circuits are required on all four sides of the array. These current drive circuits take up a large amount of area, thereby reducing the capacity of the MRAM memory device. With the dual conductor structure, each array block requires a separate set of column write drivers. With such a configuration, the difficulty of reading and writing individual MRAM cells increases as the size of the array increases.

One type of three-conductor memory cell array includes a switch or "steering" device associated with each MRAM cell. In practice, this steering means (typically a transistor) is located in the silicon layer, i.e. on the silicon substrate, below the memory layer. Although diodes have been proposed as steering devices, they have not been successfully demonstrated. The three-wire memory cell array includes low-resistance bit lines, low-resistance word lines, and inter-cell thin wires. In this configuration, each memory cell is connected to a low resistance bit line and an inter-cell thin conductor line. The inter-cell conductors are also connected to switching transistors located within the silicon substrate. Alternatively, the metal word line or low resistance word line is electrically insulated from the cell, but is processed to pass close enough physically to the memory cell to allow the induced magnetic field from the low resistance word line to control the data to be stored in the free magnetic layer of the MRAM cell. A second wordline formed within the silicon substrate may be connected to the gate of the silicon switch. When data is written to a memory cell, the silicon switching transistor is deselected (by being turned off by the second word line) and a write current flows through the selected bit line and word line, magnetizing the free layer of the selected memory cell. When the memory cell is read, no current flows through the first metal word line while the second word line is asserted to select the silicon switch (which is turned on by the second word line) and apply a read potential to the selected bit line. To retrieve data, a read current flows through a selected bit line, memory cell, intercell conductor, and selected silicon switching transistor. A sense amplifier connected to the selected bit line is then used to determine the resistance state of the memory cell based on the resulting bit line current.

In a three-conductor memory cell array, the metal word lines typically extend over the entire memory chip. By stretching the metal word lines across the entire memory chip, the entire chip requires only two write circuits, one on the left side of the chip and one on the right side thereof. This is in contrast to a two-conductor MRAM, which requires a write current driver for each memory cell block. With a three conductor memory cell array, fewer word line write drivers are required, and thus more space is available for the memory cells, resulting in a larger memory capacity.

A second type of three-conductor MRAM cell includes a low resistance bit line, a low resistance word line, and a thin sense line. In this configuration, the low resistance metal bit line passes through the thin sense line but may be electrically isolated from the thin sense line. The sense line is connected to one terminal of the memory cell, and the other terminal of the memory cell is connected to a low resistance metal word line. The sense line is connected to a small group of memory cells and to a switching transistor formed in the silicon substrate. The switching transistor is controlled by the metal bit line and is activated only during a read process. In such a configuration, a write operation generates a current through a selected bit line and word line to establish a magnetization direction of the free magnetic layer corresponding to write data given to the selected memory cell. The read operation applies a read potential to the selected word line while turning on the switching transistor, allowing a read current to flow from the selected word line, through the selected memory cell, the thin read line, the switching transistor, and into a sense amplifier located within the substrate.

In the second type of three-wire memory cell array, the metal bit line wires extend over the entire length of the memory chip. Since the conductive lines are spread over the entire length of the chip, only two write circuits are required, one at the top and one at the bottom of the chip, unlike two-conductor MRAM, which requires one write circuit per memory cell block. Thus, with a three-wire memory cell array, more memory cells can be included on the chip, resulting in more efficient use of chip resources.

The memory cells are not limited to any particular device type. For example, the memory cell may be a spin-dependent tunneling (SDT) device. A typical SDT device includes a "fixed" magnetic layer and a "free" magnetic layer. The pinned layer has a magnetization whose direction is in-plane, but is fixed so that it does not rotate in the presence of an applied magnetic field in the range of interest. The magnetization direction of the free magnetic layer is not fixed. But may be magnetized in any direction along an axis in the plane (the "easy" axis). If the free and fixed layers are magnetized in the same direction, the orientation is referred to as a "parallel" orientation. If the magnetization directions of the free and fixed layers are opposite, the orientation is referred to as an "antiparallel" orientation. The free layer and the fixed layer are separated by an insulating tunnel barrier layer. The insulating tunnel barrier layer allows quantum-mechanism tunneling to occur between the free layer and the fixed layer. This tunneling phenomenon is electron spin dependent, making the resistance of the SDT device a function of the relative orientation of the magnetization of the free and fixed layers.

For example, if the magnetization orientations of the free layer and the fixed layer are parallel, the resistance of the memory cell takes a first value R. If the magnetization orientations of the free layer and the fixed layer are antiparallel, the resistance of the memory cell increases to a second value R + Δ R. Typical resistance values are about one megaohm. A typical resistance change Δ R is about 10% of the resistance value R.

Fig. 2 shows a three conductor memory cell structure in which a sense conductor 201 is added to a two conductor memory cell structure. In this configuration, word line 101 and bit line 102 are used to write data to the selected MRAM cell. The sense conductor may be used to read data from the MRAM cell. In this configuration, the sense line is connected to one terminal of the MRAM memory cell and is typically formed in the form of a very thin conductive layer, where the word line 101 may be a relatively thick, low resistance conductive line electrically insulated from the sense line, running parallel to the sense line. A relatively high current may be applied to the word line for writing.

With the second type of three-wire memory cell structure, the column write driver bank is reduced to a unique bank (across many memory array blocks) at the top and bottom of the memory chip, eliminating column write drivers from between memory array blocks. The three-wire cell structure thus improves the area efficiency ratio by making the memory chip smaller, eliminating the inter-block column write drivers. In addition, the column decoding circuit can be arranged below the three-conductor memory cell array, so that the space requirement is further reduced. However, three-wire memory cells do not reduce or alleviate the space requirements for increasing current in the row direction.

Disclosure of Invention

One embodiment of the present invention includes a four-conductor MRAM device, comprising: an array of memory cells, each memory cell comprising a first magnetic layer, a medium, and a second magnetic layer; a plurality of local column readout lines, one of which is electrically connected to the first magnetic layer of the memory cell array; a plurality of local row sense lines, wherein one of the local sense lines is electrically connectable to the second magnetic layer of the memory cell array; a plurality of global column write lines parallel to the plurality of local column read lines; a plurality of global row write lines parallel to the plurality of local row read lines; wherein the plurality of local column read-out lines and the plurality of local row read-out lines are connected to read data from the array of memory cells, and the plurality of global column write lines and the plurality of global row write lines are used to write data to the array of memory cells.

Another embodiment of the present invention includes a method of applying a read potential in an array of four-conductor MRAM cells, the method comprising the steps of: applying a first logic level to the selected global row line; applying a second logic level to the selected global column line; selecting a first group of memory cells using the selected global column line and global row line; using the unselected global column lines and the unselected global row lines to deselect the second group of memory cells; applying control potentials through row and column taps to control gates within the row and column taps; controlling potentials applied to selected local column readout lines and local row readout lines; wherein the first potential is applied to selected local column readout lines and the second potential is applied to selected local row readout lines; the unselected local word lines are connected to a third logic level and the unselected local column lines are disconnected from the input terminals of the sense amplifiers.

Another embodiment of the present invention includes a method of applying a write current in an array of four-conductor MRAM cells, the method comprising the steps of: applying a first current to the selected global row line; applying a second current to the selected global column line; selecting a memory cell by using the selected global column line and global row line; applying a control voltage to all local read row lines; and applying a row block control signal to deactivate all sense amplifiers.

Drawings

FIG. 1 illustrates a two-conductor resistive cross-point MRAM architecture;

FIG. 2 is a schematic diagram of a three conductor MRAM architecture;

FIG. 3 is a partial view of a four conductor MRAM architecture of a first embodiment of the invention;

FIG. 4 is a circuit schematic of the four conductor MRAM of FIG. 3 accessed using monolithic row and column taps;

FIG. 5 is a schematic diagram of an alternative embodiment for accessing the row taps of the MRAM of FIG. 3;

FIG. 6 is a detailed schematic diagram of one embodiment of row circuitry for accessing the MRAM of FIG. 3;

FIG. 7 is a detailed schematic diagram of one embodiment of a column circuit for accessing the MRAM of FIG. 3;

FIG. 8 is a block diagram of an MRAM chip showing row and column taps and their relationship to the array and decoder;

FIG. 9 is a flow chart for applying a read potential to an array comprising four conductor MRAM cells; and

FIG. 10 is a flow chart for applying a write current to an array including four conductor MRAM cells.

Detailed Description

The use of MRAM in electronic devices is expected to improve electronic devices in many ways. These improvements include reducing the power required to store and read data, the ability to "turn on momentarily" and "turn off momentarily" and reducing data loss that may result from a power loss before data is transferred from volatile Random Access Memory (RAM) to non-volatile long term memory such as a hard disk or fixed disk. The present invention provides a greatly increased area efficiency ratio (memory available per unit of space required) associated with MRAM. One embodiment of the present invention includes a four-conductor MRAM design that increases the area efficiency ratio of the MRAM. Another embodiment of the present invention includes a circuit for reading from and writing to a four-conductor MRAM cell.

One embodiment of the present invention includes attaching a fourth conductive line to the MRAM and having a structure with row taps and column taps for reading data from and writing data to the MRAM cells. The taps include small active circuits between the arrays that serve as an efficient means of connecting the signals passing along the write conductor to the appropriate row and column to be read. The use of write conductors across a full chip with row and column taps makes it possible to more efficiently utilize MRAM.

The four conductor cell includes connections and/or conductors that serve as (1) local column readout lines; (2) a local row read line; (3) a global column write line; and (4) a global row write line. In one embodiment of the invention, a single global row and column decoder is used to access the memory array. The local row taps may support potential level sensitive or "V (voltage) mode" sense amplifiers or current sensitive or "I (current) mode" sense amplifiers. In one embodiment of the invention, the local column tap selects one of the columns for input to the sense amplifier. Similarly, the local row tap selects one of the rows to be electrically connected to the sense amplifier. The local row and column taps are first arranged outside the sub-array "footprint". The area under the subarray may be dedicated to the routing of the sense amplifiers. The row group control signal (1) applies the second potential to only the rows of the selected group and (2) selectively gates or gates off the sense amplifiers associated with the selected row group. In the read mode, the row/column decoder applies row/column information (logic signals) to the third and fourth conductors. In the write mode, write currents are applied to the circuits 609, 610, 702, and 801 of fig. 8 that are turned on at the periphery of the global array. In the preferred embodiment, one local row tap and one local column tap is required per row/column/plane.

The fourth conductor is used to access the MRAM cells while reducing the hardware resources required on the chip. The fourth line may be a thin line running parallel to the thicker row line with very low resistance. By utilizing a set of row write drivers on each side of the chip, the MRAM memory chip area efficiency ratio can be improved, allowing for the inclusion of additional memory cells on the chip. One embodiment of the present invention also includes a method of using a four-conductor MRAM.

FIG. 3 is a partial perspective view of a portion of a four conductor MRAM architecture in accordance with one embodiment of the invention. A complete MRAM architecture may include thousands of bit lines and thousands of word lines and MRAM cells at each bit line and word line intersection. Fig. 3 illustrates a four-conductor MRAM in a resistive cross-point MRAM architecture. The four conductors of the MRAM include global column write conductor 301, local column read conductor 302, local row read conductor 303, and global row write conductor 304. The global column write conductor 301 may be similar to the bit line 102 of fig. 1. The local column read conductors required with a relatively low current carrying can be very high resistance and very thin conductor layers. The local column read conductors 302 are electrically insulated from the global column write conductors 301. Local row sense conductor 303 may be a "thinned" version of the word line connected to each MRAM cell. The global row write conductors 304 may be very low resistance metal conductors applied over the local row read conductors 303 with an appropriate intervening insulating layer.

The four-conductor MRAM cell used in fig. 3 can be described in the form of a cubic structure. On top of the cube is a data layer or data magnet. Below the data layer is a thin layer of insulating cells. At the bottom of the cubic structure is a reference layer or a fixed layer. It should be noted that the data layer or the reference layer may be inverted.

The top data layer of each four-conductor MRAM cell of a particular row of memory may be wired or connected to a bit line running in a vertical direction. Similarly, the bottom of each four-conductor MRAM cell reference layer for a particular row of memory may be wired or connected to a word line running in the horizontal direction. A typical MRAM may consist of one to two thousand rows of MRAM cells and two to four thousand columns of MRAM cells. The two conductors (local column sense conductor 302 and local row sense conductor 303 of fig. 3) that are actually connected to and/or in contact with each MRAM cell are relatively thin conductors. This is because the twin conductor lines must be made thin so that the spacing of the MRAM data layer to the two write conductors remains small for the magnetic field generated in the write conductors to maximize coupling to the data layer. The twin wires can be thin because they carry a smaller sense current and therefore can have a higher resistance. The local row sense lines are sometimes referred to as word sense lines or word lines. The local word sense lines may be referred to as bit sense lines or bit lines. Partial word sense lines and partial row sense lines are used in the read process.

It should be noted that terms indicating absolute directions, such as "horizontal" and "vertical", are used only for convenience of the present description. These terms, however, are merely intended to facilitate reference to the figures, in which the respective structures are described in a reference orientation. Embodiments may provide other orientations, including but not limited to structural orientations relative to each other consistent with the absolute orientation described.

Parallel to these read-out conductors (local column read-out conductors and local row read-out conductors) is a set of relatively thick conductors constituting the interconnect conductor with a relatively low resistance. These parallel conductors (global column write conductor and global row write conductor) are used for both the write process and the read process. The writing process typically affects one row at a time, but may affect more than one column at a time, typically 16 columns or less at a time. As previously described, during a write process, write currents are passed through both the respective columns and the respective rows so that cells at the intersections of the rows and columns establish magnetic fields that selectively orient data in the data layer with the magnetic fields. Providing a positive or negative current in the bit line enables the magnetic field within the data layer to change between parallel and anti-parallel states. As used herein, "positive" and "negative" refer to the relative directions of current flow; the terms "parallel" and "anti-parallel" refer to opposite directions of magnetic flux. These conductors are referred to as global row write conductors and global column write conductors. During read-out, parallel conductors (global column write conductors and local column read conductors or global row write conductors and local row read conductors) carry address-decoding logic signals to the gates or row and column taps.

One embodiment of a four conductor MRAM device can include an array of memory cells, where each memory cell includes a first conductor, a first magnetic layer, a medium, a second magnetic layer, and a second conductor. The first conductive line of the memory cell array may be electrically connected to one of a plurality of local column sense lines 302. The second conductive line of the memory cell array may be electrically connected to one of the plurality of partial row sense lines 303. A plurality of global column write lines 301 may be parallel to the plurality of local column read out lines 302. The plurality of global row write lines 304 may be parallel to the plurality of local row read out lines 303. A plurality of local column read-out lines 302 and a plurality of local row read-out lines 303 are used to read data from the array of memory cells 103, while a plurality of global column write lines 301 and a plurality of global row write lines 304 are used to write data to the array of memory cells 103. Each of the plurality of local column read-out lines 302 and each of the plurality of local row read-out lines 302 are relatively thin and may be comprised of a material having a relatively high resistivity. Each of the plurality of global column write lines 301 and global row write lines 304 may be a low resistance, thicker conductive line having a thickness from 5 to 50 nanometers (including 50) and electrically insulated from the plurality of local column read lines 302 and the plurality of local row read lines 303. The memory cell array 103 may include a stack of planes of multiple memory cells, one on top of another, in order to increase the storage density or resource efficiency of the storage structure.

As described, this embodiment of the invention includes support circuitry for writing data to and reading data from a four-conductor MRAM, including a row decoder, a first read/write row driver connected to the row decoder, a plurality of global row write conductors 402, 403 (fig. 4) connected to the first read/write row driver; a plurality of row taps connected to each of the global row write conductors; and a second read/write row driver connected to the global row write conductor.

One feature of this structure is the relatively close spacing between the conductive lines required for weak coupling from the conductive lines to the MRAM cells. The vertical distance between the conductive lines is maintained by the thickness of the read conductive line, which is typically on the order of 200 angstroms, and the thickness of the medium (on the order of 200 angstroms) separating the parallel write conductive lines from the read conductive lines.

The proposed method of writing information to and reading information from a four-conductor MRAM, as described, may utilize the write conductors (global row write line 304 and global column write line 301) as the path for transferring decoded data. The decode circuitry receives the address and applies select voltages to the appropriate columns and rows and deselect voltages to the remaining unselected columns and rows in the memory configuration. Decoding the data includes selecting the row and column of MRAM cells that define the target of the read/write operation. The select voltage may propagate along row and column low resistance conductors, also referred to as write conductors.

Fig. 4 is a circuit schematic for accessing the four-conductor MRAM of fig. 3 using monolithic row and column taps. In one embodiment of the present invention, taps are fabricated at the edges of the MRAM array to (1) global column write line 301 and global row write line 304 to control the access transistors, to connect the selected local row line to the appropriate selected read potential and to connect all unselected row lines to the second unselected read potential and (2) to connect the selected sense lines 302 and 303 to the sense amplifiers, leaving all unselected sense lines in a high impedance or "float" state. This implementation avoids the necessity of circuitry previously associated with accessing the MRAM cells from beneath the MRAM array. Instead, the area under the MRAM cell array can be used for the required sense amplifiers. The MRAM array 401 may be an area where memory cell sub-arrays are arranged. Such arrays are typically 512 to 4096 (i.e., 4K) columns "wide" by 1024(1K) to 2048(2K) rows "high", although this is typically only a range required based on current fabrication methods and current devices. Sense amplifier 408 circuitry is formed in a portion of the silicon substrate below the memory cell array. Fig. 4 also includes four parallel horizontal lines including two global row write conductors 402, 403 and two local row conductors, i.e., row sense lines 404 and 405. Two global row write conductors 402 and 403 form a fourth conductor row line that is added to the previously described three conductor MRAM cell. The signal present on global row write conductor 402 is connected to inverter 406 which is connected to voltage levels V1 and V2. Inverter 406 is responsive to signals on global row write conductor 402 to selectively apply either V1 or V2 to local row conductor 405.

Fig. 4 shows that P-channel transistors and N-channel transistors can be used as inverting circuits to connect to signals V1 and V2. For example, in response to a high level on global row write conductor 402, inverter circuit 406 connects the local row conductor to V1. At the same time, all other row lines are deselected and a low signal (i.e., low voltage) is provided to the associated unselected row write conductors. The low level signal present on row write conductor 403 electrically connects the respective local row conductor to V2 through inverter 407. Sense amplifier 408 also uses V2 as a detection reference level. A relatively simple device located outside the array is used to provide row lines from the fourth conductor (running on top of the array) and to direct signals read from the selected MRAM to the local row lines for detection.

Fig. 4 also includes four vertically parallel signal lines, including two global column write lines 411, 412 and two local sense lines 409, 410. The global column write lines 411, 412 and the read conductors 409, 410 operate in a similar manner to the global row write conductors and row read lines described above. The global column write conductors 411, 412 are third conductor column lines, which are low resistance lines, running above the top of the entire MRAM cell array. The global column write lines 411, 412 also conduct column select data from the respective column decode circuits. The signals referred to herein are the output signals of the column decoder, the selected column data signals are logic "Hi", and the unselected column decoded data are logic "Lo". Column select transistors 413, 414 are connected to local read lines 409, 410, respectively. The column lines and bit lines may be selected by applying a logic high signal to the third global column write line to turn on the column select transistor to connect a local sense line to the input of the sense amplifier 406. The remaining unselected local read lines are associated with respective global column write conductor lines and have a logic low signal to turn off the column select transistors. For example, column select transistor 413 is biased to turn on when a high level signal is present on conductor 411, thereby electrically connecting detection column 409 to signal line 406 and the input of sense amplifier 408.

The unselected bit lines are associated with a logic low signal on the global column write line; only the selected column has a global column line with a logic high signal. For example, when a signal of logic high is present on conductor 411, other conductors, such as global column write conductor 412, are electrically connected to a signal of logic low. The electrical connection ensures that the column select crystals are biased off, insulating the detection column 410 from the sense amplifiers 408. All other select transistors associated with unselected column lines are connected to a logic low signal to ensure that the respective transistors are biased off, while the associated local sense lines are electrically disconnected from the associated sense amplifiers. In any one set of columns, only one local sense line is connected to the sense amplifier at a time.

In a preferred embodiment, a single sense amplifier may be associated with several columns, typically corresponding to a grouping of columns, such as 64, 128 or 256 columns. The column groups are located close to each other, e.g. immediately adjacent. In a column group of 256 columns, a single MRAM array comprising 2K (i.e. 2048) column cells is connected to a single sense amplifier, so that only 8 sense amplifiers in total are needed below the 2K column array. Fig. 4 illustrates signals of the low-resistance third conductors 402 and 403 and fourth conductors 411 and 412 for passing selected and unselected memory cells both in rows and columns, thereby simplifying the circuitry required for connection to the sense amplifiers. The operations are performed in the decoder circuits 608 and 703 and the write driver circuits 609, 610, 702, and 801 of fig. 8.

The sub-array organization of the overall larger array may be determined by the lengths of the local bit lines (sense lines) and local word lines. The sensitivity and noise of the sense amplifier generally determine the maximum length of the local line that is operated in the sense mode. The local lines are preferably of sufficient length to accommodate all of the sense amplifiers/integrators/comparators and some additional support circuitry located entirely beneath the sub-array "ground". In fig. 4, two readout potentials are shown: v1 is the sense potential applied to the selected word sense line 405 and V2 is the potential applied to the unselected word sense line 404 and serves as a reference for the sense amplifier. V2 is part of an equipotential method of detecting MRAM.

Fig. 5 is a schematic diagram of another embodiment for accessing two taps of the MRAM of fig. 3. In fig. 5, two N-channel transistors 506 and 511 are used to provide the select function. In one embodiment, the N-channel transistor 506 is connected between the local row readout line 501 and the first readout potential V1509, while the second N-channel transistor 511 is connected between the local row readout line 502 and the first readout potential V1504. Fig. 5 illustrates a relatively efficient apparatus for providing the selection function. The area required for integration of circuits having both P-channel and N-channel transistors is larger than that required for circuits having similar functionality but using only N-channel transistors, because in a more typical CMOS process, the N-channel transistors are disposed within a P-type substrate, which is common to all N-channel transistors, and the P-channel transistors must be disposed within an N-type diffusion (referred to as an N-well) of the P-type substrate. The N-well is deeply diffused and requires a considerable amount of area compared to an N-channel transistor. Therefore, designs that utilize only N-channel transistors are always placed in areas that are much smaller than designs that include both N-channel and P-channel transistors. Two long channel, low current, N-channel transistors 510 and 512 are connected to local sense lines 501 and 502 and to a second sense potential V2507. The gate control for long channel transistors 510 and 512 is row block control signal 508 routed from row decoder 608 of fig. 6 through the interior of the substrate.

The selected row sense line 501 is connected to V1, and the unselected partial row 502 is connected to V2. During read out, the selected global row 503 is connected to a logic high signal and the unselected global row 505 is connected to a logic low signal. The unselected local rows 502 are each connected to V2507 through a long channel N-channel transistor 512 having a gate controlled by a row block decode signal 508. Long channel transistors are used wherever low current drivers or high resistance circuit elements are required. In this case, all long channel transistors are turned on by signal 508 and the unselected local sense line 502 is connected to V2507 through transistor 512 (note that transistor 511 is off). While the unselected local row 501 is connected to V2 through 510 and to V1 through 506, however 510 is a long-channel transistor that is weakly current driven and 506 is a short-channel transistor that is strongly current driven, and even when the long-channel transistor is on, the net effect is that transistor 506 is active in pulling the selected local row sense line 501 up to V1509. In this configuration, long channel transistor 512 provides a limited current through transistor 512 in an attempt to connect the unselected local row 502 to V2507, and through long channel transistor 510 in an attempt to connect the selected local row line 501 to V2507. The unselected row select transistor 511 is turned off and the unselected local row 502 provides a finite current pull to V2507 through the long channel transistor 512. However, the selected row transistor 506 has a larger capacity, causing the selected row 501 to be "pulled" to V1509 and passing current both from the selected row 501 and from the pull-up transistor. In this configuration, the long-channel transistors 510, 512 are effective in interconnection and wiring. In a preferred embodiment, a fourth conductor 503 electrically connects the selected row transistor 506 to a logic high signal. A fourth conductor 505 connects each unselected row transistor 511 to a logic low level signal. The selected local sense line 501 may be activated to read data from the cell with transistor 506, effectively pulling the local sense line to V1 while long channel transistor 510 conducts limited current from V2.

Gate line 508 controls the gates of long channel transistors 510, 512 and may generate signals during a read operation to connect unselected row sense lines 502 to V2507. In the example, transistors 510 and 506 are both turned on and connected to the selected row sense line 501. The long-channel transistor 510 will cause the short-channel transistor 506 to dominate the control of the selected local row sense line 501, such that the resulting potential on the local row sense line 501 is maintained at V1509, depending on the size of the short-channel transistor 506. Selected local read row 501 is activated and all other local read rows 501 turn all transistors 511 off and transistor 512 on. The unselected word lines 502 in the unselected groups are electrically connected to V2507. Only the selected local wordline 501 may be electrically connected to V1509. During a sensing operation, transistors 506 and 510 are turned on, and selected local sense line 501 is set to a first sensing potential V1509, and transistor 511 is turned off, transistor 512 is turned on, and unselected local sense line 502 is set to a second sensing potential V2507.

Transistors 510 and 512 are long channel transistors, which ensure that the unselected local sense line 502 is connected to the second sense potential V2507 through a low current device. The selected local row sense device 506 has a relatively high current capacity device to pull the selected low row line to V1509. Note that the current drive capability of transistor 506 is much larger than the drive capability of transistor 510, but is driven by the current required for the sense current on the local sense line, which is thus controlled by short-channel transistor 506 and pulled down to V1509.

FIG. 6 is a schematic diagram of row circuitry for accessing the MRAM of FIG. 3. Fig. 6 includes a main row decoder 608 that multiplexes the received binary address signals to specify the row being addressed. The master read/write row driver 609 and the slave read/write driver 610 both function similarly. Note that the row write drivers are simple current sources, with the master read/write row driver 609 being a current source and the slave read/write row driver 610 being a current sink. A row write current flows from the master read/write row driver 609 to the slave read/write row driver 610. Row decoder 608 is a true decoder that selects a row from n rows as the active row and the rest as the inactive row. n is the total number of rows in the array. The MRAM cells are located within memory array blocks 612 and 613. Two adjacent memory blocks 612 and 613 share a row tap 610 to apply a sensing potential V1607 or V2606 to a local sense line 614 of the memory array block 612 and the memory array block 613. Memory blocks 612 and 613 share a common row tap circuit. The memory block 612 and row taps 616 comprise a component block 618 for the array, and are repeated to include the entire array. Although FIG. 6 shows two rows of memory block groups, a similar configuration may be constructed to support a memory structure comprising several memory blocks.

Only one row 605 of the memory array may be selected for a read operation while all remaining rows 601 and 604 are unselected. Rows 601 and 604 are illustrated as unselected and thus do not affect the read operation. Row 605 may be selected while all other rows in the storage group are unselected. Row block control signals 602 and 603 from decoder 608 are transmitted to row taps of the bank of memory cells containing selected and unselected rows. Row control signals 604 and 605 and row block control signal 603 add a first readout potential V1607 to the selected local readout row and a second readout potential V2606 to all the unselected local readout rows. Fig. 6 includes the row tap circuit of fig. 5, which constitutes block 618, shared with the two MRAM array blocks 612 and 613. The rows in memory group 612 are illustrated as unselected and thus do not affect the read operation. Within storage group 615, row 605 may be selected while all other rows within storage group 615 are unselected. Fig. 6 illustrates the relationship of long channel transistors and short channel transistors in selected row 605. At location 618, a shared row tap and two memory blocks are shown.

FIG. 7 is a schematic diagram of one embodiment of a column circuit for accessing the MRAM of FIG. 3. Fig. 7 is similar to fig. 6, but illustrates column circuitry. In the lower part of the figure, column decoder 70 provides a select signal to main column read/write drivers 702 through the addressed column select lines. Although not shown, a second column decoder and associated slave column read/write drivers are also located at the top of the memory array. The embodiment shown in FIG. 7 includes two columns of MRAM memory blocks 703 and 704. Each memory array block includes a number of columns of MRAM memory cells. In each column of the memory array block, the column decoder selects one column 706 to activate, and all remaining columns in the columns of the array block are unselected. Each column of the array block is organized into a pair of MRAM array blocks 708 separated by a shared column tap 705. It should be noted that the array blocks 703, 704 may be repeated in order to form a large MRAM array. Each column of MRAM array blocks (703 and 704) may be considered a column stripe, with one such column stripe 704 being illustrated in fig. 7. The column stripes may be 64, 128, 256, 512 or more columns wide, with each column stripe corresponding to one bit of a memory word, and the memory may be expanded by repeating the column stripes to achieve the desired memory configuration. Typically, the words stored in memory are arranged in groups of 8 bits. Examples of typical word sizes include 8 bits, 16 bits, 32 bits, 64 bits, 512 bits, 1024 bits, 2048 bits, and 4096 bits.

In the embodiment of FIG. 7, the selected column 706 is connected to the gate of a switching transistor 709, which connects a local column sense conductor 712 to an input sense amplifier IA/B711. The sense amplifiers are shown as two blocks 1A and 1B to generally appreciate that the physical configuration of the sense amplifier 1 may be separated and located beneath two groups of MRAM memory cells 708 separated by a shared column tap circuit 705. In addition, the unselected columns 707 can be connected to a logic low signal or the unselected local column readout lines need not be connected to the second potential, but rather are allowed to "float". In this embodiment, the column tap 705 may be a single transistor, or a selected column transistor (Q)_SC)709 or unselected column transistors (Q)_US)710. Each timeA plurality of column stripes, such as column stripe 703, comprise a plurality of groups 708 of MRAM arrays, with shared column taps 705 and sense amplifiers 711. At the same time, the third conductor 707 of the unselected column receives a logic low signal, causing transistor Q to be turned on_UC710 remain off. The row block control signal turns on only the sense amplifiers associated with the selected column, e.g., sense amplifiers 711 of column 706. The MRAM arrays are arranged in MRAM array rows and through the MRAM arrays, the arrays being grouped into column stripe cells. All other sense amplifiers remain off. A local column tap circuit ideally splits the local read lines (minimizing the effect of local column read line resistance). In one embodiment, the column tap is physically located at the center of the local sense line such that half the sense line resistance is seen from the point of the column tap to the other point of the sense line. In this embodiment, the performance of the sense amplifier is sensitive to the sense line resistance, the smaller the better. The local column tap circuit is also configured between the local sub-arrays, resulting in an efficient layout while requiring a minimum number of transistors. The local column tap circuit also enables the entire sense amplifier to be configured below two sub-array blocks (including sense amplifiers 711 and 711 of SAIA and SAIB).

Fig. 8 is a block diagram of the overall arrangement of an MRAM chip, showing the row and column taps and their relationship to the array and decoder. Although a sized array is presented in fig. 8 for purposes of illustration, the array may be larger, include larger and/or more sub-arrays and supporting circuitry, or vice versa. The MRAM chip includes a column decoder 703, a master column read/write driver 702, a slave column read/write driver 801, a row decoder 608, a master row read/write driver 609, a slave row write driver 610, local row taps 802, local column taps 803, and a memory sub-array 804. Column decoder 703 and row decoder 608 receive respective portions of the address signal and, in response thereto, select a column or column group (column decoder 703) and a row (row decoder 608) that specify the cell to be read. Typically, a separate row is selected than the group of rows. Columns may also be selected individually or in groups. The master read/write drivers 609 and 702 are associated with slave write drivers for the rows 610 and columns 801, respectively. Located between these drivers in this embodiment are a sub-array of MRAM cells 804, associated local column taps 803 and associated row taps 802. As discussed, the column tap or column select circuitry includes column select transistors and is disposed between two array blocks 804. The array will be constructed in the form of a cell sub-array 804, column taps 803, cell sub-array 804, array block 804, column taps 803, array block 804. Similarly row selection circuitry or local row taps 802 are also provided between the array blocks 804. The arrangement of local row taps 802 to memory array blocks may be an array block 804, a row tap 802, an array block 804, a row tap 802, an array block 804. In practical implementations, the taps 802 require relatively little chip resources, resulting in a very efficient array packaging of sub-arrays surrounded by support circuitry for driving the write circuits.

This embodiment of the invention comprises a support circuit for writing and reading a four-conductor MRAM, said four-conductor MRAM comprising a row decoder 608, a first read/write row driver 609 connected to the row decoder 608, a plurality of global row write conductors (601, 604 and 605 of fig. 6) connected to the first read/write row driver 609; a plurality of row taps 802 connected to each global row write conductor; a second read/write row driver 610 connected to the global row write conductor; a column decoder 703; a first read/write column driver 702 connected to the column decoder 703; a plurality of global column conductors (706 and 707 of FIG. 7) connected to the first read/write column driver 702; a plurality of column taps 803 connected to each global column write conductor; and a second read/write column driver 801 connected to the global column write conductor.

The global row write conductor may be connected to a control gate in the row tap support circuit and the control gate connects the selected local row sense line to the sense first potential. The control gate also connects all unselected local row sense lines to the unselected second potential. The global column write conductor is connected to the transistor control gates of the column tap support circuits which connect the selected local column sense line to a second sense potential generated via the sense amplifiers. A second global column write conductor of the plurality of global column write conductors is connected to a second control gate of the transistor of the column tap support circuit, and the control gate may connect a second selected local sense line to a second sense potential generated by a second sense amplifier. The global row write conductor constitutes the first conductor of a four-conductor memory cell, which forms an MMRAM cell. The global column row write conductor is the second conductor of the four conductor memory cell, which forms the MMRAM cell.

Fig. 9 is a flowchart for applying a readout potential in an array constituting a four-conductor MRAM. The method starts at step 900 and supplies a first logic potential to a selected global row while simultaneously applying a second logic potential to unselected global rows at step 901. A first logic potential is applied to the selected global column and a second logic potential is applied to the unselected global column at step 902. The first readout potential is applied to the selected row and readout line along with the first global row logic potential at step 903. At step 904, a second sense potential is applied to the unselected row and sense lines along with a second global column logic potential. In step 905, a second sense potential is applied to the unselected row and sense lines along with the logic potential of the first global column. At step 906, the input terminals of the sense amplifiers are disconnected from the unselected column sense conductors with the second global column logic potential. In step 907, the sense amplifiers are activated using the row block detect control signal. Step 908 selects the memory cell with the appropriate connection and sense potentials to initiate a sense operation and the method ends at step 906.

FIG. 10 is a flow chart of a method of applying write currents to an array comprising a four conductor MRAM. Beginning at step 1000, all sense amplifiers are deactivated at step 1001 using a row block control signal. A write operation is performed at step 1002 and a row is selected at step 1003 to which a write current is applied. A column of each column bar is selected at step 1004. The write data signals are provided to the column master and slave write drivers in step 1005. A row write current is applied to the selected global write conductor using row master/slave write drivers at step 1006. A column write current is applied at step 1007 and the global column write conductor is selected in the direction determined by the data provided at step 1005 using the column master/slave write drivers. The write operation is ended by turning off the write current in the appropriate sequence at step 1008 to end the write operation and the method ends at step 1009.

Although the circuit has been described in connection with a four-conductor MRAM cell, the circuit can be modified to support and control other MRAM configurations.

Claims (10)

1. A four-conductor MRAM device, comprising:

an array of memory cells, each of the memory cells comprising a first magnetic layer 104, a medium 106, and a second magnetic layer 105;

a plurality of local column sense lines 302, one of which is electrically connected to the first magnetic layer 104 of the memory cell array;

a plurality of local row sense lines 303, wherein one of the local sense lines is electrically connected to the second magnetic layer 105 of the memory cell array;

a plurality of global column write lines 301, which are parallel to the plurality of local column read out lines 302,

a plurality of global row write lines 304 parallel to the plurality of local column readout lines 303, an

Wherein (i) the plurality of local column read out lines 302 and the plurality of local row read out lines 303 are connected to read data from the array of memory cells, and (ii) the plurality of global column write lines 301 and the plurality of global row write lines 304 are connected to write data to the array of memory cells.

2. The apparatus of claim 1, further comprising:

one or more transistors connected between one or more of the local row sense lines and a local sense potential voltage.

3. The apparatus of claim 2, further comprising:

one or more transistors connected to the local row sense line and to a second sense potential voltage.

4. The apparatus of claim 3, wherein the one or more transistors coupled to the second sensing potential voltage further comprise:

gate control, which is a row block signal from the row decoder.

5. The apparatus of claim 1, wherein: the plurality of global column write lines are low resistance thicker conductive lines and are electrically insulated from the plurality of local column read lines.

6. The apparatus of claim 1, wherein: each of the plurality of global row write lines is a low resistance conductive line and is electrically insulated from the plurality of local row read lines.

7. The apparatus of claim 1, wherein: the memory cell array includes a stack of multiple planes of memory cells.

8. A method for applying a write current in an array comprising four-conductor MRAM cells, the method comprising the steps of:

applying a first current to the selected global row line 304;

applying a second current to the selected global column line 301;

selecting a memory cell using the selected global column line 301 and global row line 304;

applying a control voltage to all local sense row lines 303; and

the row block control signal is applied to deactivate all sense amplifiers.

9. The method of claim 8, further comprising:

said first and said second current are cancelled according to a suitable switching-off sequence.

10. The method of claim 8, further comprising:

current is supplied through the transistor to connect the selected row sense line to a voltage level.