CN2757293Y - Magnetic resistance type storage unit and magnetic resistance type random access storage circuit - Google Patents
Magnetic resistance type storage unit and magnetic resistance type random access storage circuit Download PDFInfo
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- CN2757293Y CN2757293Y CN 200420084310 CN200420084310U CN2757293Y CN 2757293 Y CN2757293 Y CN 2757293Y CN 200420084310 CN200420084310 CN 200420084310 CN 200420084310 U CN200420084310 U CN 200420084310U CN 2757293 Y CN2757293 Y CN 2757293Y
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Abstract
The utility model relates to a magnetic reluctance type RAM circuit. A magnetic reluctance type memory unit has a fixed magnetic axis layer, a first free magnetic axis layer, a second free magnetic axis layer and insulating layers respectively arranged between the fixed magnetic axis layer and the first free magnetic axis layer and between the first and the second free magnetic axis layers. A bit line is coupled to the magnetic reluctance type memory unit for providing a first magnetic field. A first programming line and a second programming line respectively provide a second magnetic field and a third magnetic field to be combined with the first magnetic field for respectively changing the magnetic axis direction of at least one of the first free magnetic axis layer and the second free magnetic axis layer. A switching device is coupled between the magnetic reluctance type memory unit and one of the first programming line and the second programming line, and has a control brake. A character line is coupled to the control brake for providing signals to conduct the switching device.
Description
Technical field
The utility model is relevant for a kind of memory circuitry, particularly relevant for a kind of circuit that stores the magnetic random access memory of long numeric data.
Background of invention
Magnetic random access memory (Magnetic Random Access Memory, be designated hereinafter simply as MRAM) be a kind of metallicl magnetic material, its radiation resistance is more high than semiconductor material, belong to non-volatility memorizer (Non-volatilc Random Access Memory), in the time of computer circuit breaking, shutdown, still can keep Memorability.
MRAM utilizes magnetoresistance characteristics store recording information, has low power consuming, the non-volatile and characteristic of not having read-write number of times restriction.The ultimate principle of its running is the same with storage data on hard disk, and data are foundation with the direction of magnetic, save as 0 or 1, and stored data have permanent, after by extraneous influence of magnetic field, just can change this magnetic data.
The disclosed MRAM array of conventional art is to be framework with the corresponding mram cell of a transistor mostly, United States Patent (USP) numbering US 6055178 for example, and US 6331943, and disclosed technology such as US 6335890.The disclosed framework of above-mentioned conventional art needs a large amount of transistors, therefore causes the circuit volume excessive.In addition, United States Patent (USP) numbering US 5930164 discloses a kind of storage unit of the serial connection mram cell formation of different resistances of utilizing and stores the data with 4 kinds of configurations, utilizes the mram cell with different magnetic resistance ratios to store the data with 4 kinds of configurations but disclose.
Fig. 1 is the Organization Chart that shows traditional MRAM array.The top of mram cell 10A and 10B is to be coupled to bit line Bn, and its bottom is to be coupled to electrode 12.The grid of transistor 14 is to be coupled to character line (W
m, W
M+1), source electrode is a ground connection, and its drain is to be respectively coupled to corresponding electrode 12.In order to have an insulation course 13 between the line program (16A, 16B) that writes data and the electrode 12, in order to isolate line program 16A, 16B and electrode 12.
Fig. 2 A and Fig. 2 B are the detailed structure view that shows mram cell 10.Electric current can vertically see through insulation course (tunnel junction) 104 by a free magnetic axis layer 102 and flow through (or passing) fixedly magnetic axis layer 106.The magnetic axis direction of free magnetic axis layer 102 can be subjected to the influence in other magnetic field and change, and fixedly the magnetic axis direction of magnetic axis layer 106 is fixed, and its magnetic axis direction is respectively shown in the label 108A and 108B of Fig. 2 A and Fig. 2 B.As free magnetic axis layer 102 when fixedly the magnetic axis direction of magnetic axis layer 106 is same direction (shown in Fig. 2 A), mram cell has low-resistance situation, and when free magnetic axis layer 102 when fixedly magnetic axis layer 106 is different directions, then mram cell just has and has high-resistance speciality.Consult Fig. 1, the magnetic axis direction of the free magnetic axis layer 102 of mram cell 10A and 10B is the magnetic field that produces by magnetic field that line program 16A, 16B produced and in conjunction with bit line Bn respectively and changing.
The spin flip conversion magnetic field of each mram cell is by the bit line B that flows through
nWith the current field of line program common synthetic.Then have only the magnetic axis of selecteed mram cell to reverse through moving thus, and the action of smooth record.As for non-selected storage unit part, one of them that then have only bit line or line program can be applied in current field, therefore can't form enough reversing magnetic fields, so can't carry out the information write activity.
The magnetic field that electric current produced of above-mentioned bit line and line program must can make the MRAM array normally carry out the programming action through accurate design.Consult Fig. 3, Fig. 3 shows the magnetic field that bit line and line program are provided and the graph of a relation of MRAM switching condition.Transverse magnetic field H
tBe that electric current by bit line is provided, and longitudinal magnetic field H
1Be that electric current by line program is provided, and do not having transverse magnetic field H
tCondition under, longitudinal magnetic field H
1Be H
0The time, will cause mram cell to switch its conducting degree.If transverse magnetic field H is arranged
tExistence, the critical value that switch mram cell this moment will reduce, and therefore, apply than H
0Little longitudinal magnetic field H
1Can make mram cell switch its conducting state.
In the formed regional A of dotted line, mram cell is first conducting state (is example with the high impedance), and the part beyond regional A, mram cell will be subjected to the influence in magnetic field and switch to another conducting state (is example with the Low ESR).
When reading the MRAM data, be example with mram cell 10A, this moment character line W
mTurn-on transistor 14, and, can change bit line B according to the conducting state of mram cell 10A
nVoltage level after the electric current that provides flow to earth point via mram cell 10A, transistor 14 is by detecting bit line B
nVoltage level, promptly can read the stored data of mram cell 10A.
In write step, by in the program current of line program 16A and select bit line B
nThe magnetic field that electric current produced, can change the conducting state of mram cell 10A.
In the circuit as shown in Figure 1, each mram cell corresponds respectively to a MOS transistor, the volume shared owing to MOS transistor is quite big, under the framework of traditional reluctance type storage unit circuit, a large amount of MOS transistor numerical limitations the closeness of circuit, simultaneously, also cause remembering the size of array thereby become big, under the harsh gradually trend of the integration of semiconductor product now and dimensional requirement, must effectively reduce the required transistor size of traditional reluctance type storage unit circuit.
Summary of the invention
In view of this, in order to address the above problem, the utility model fundamental purpose is to provide a kind of circuit of magnetic random access memory, has the storage unit that constitutes by a plurality of mram cell, mram cell in each storage unit has different magnetic resistance ratios, therefore, each storage unit can store the data of a plurality of characters.Moreover, a plurality of mram cells in the said memory cells are to share single switchgear, and MOS transistor for example is in conventional art, the number of switchgear must with the same number of situation of mram cell, significantly improve the integration of circuit and the size of storer.
For obtaining above-mentioned purpose, the utility model proposes a kind of magnetic random access memory circuit.The reluctance type storage unit has fixedly magnetic axis layer, first free magnetic axis layer, second free magnetic axis layer, and is arranged at fixedly between the magnetic axis layer and first free magnetic axis layer respectively and the insulation course between first and second free magnetic axis layer.Bit line is coupled to the reluctance type storage unit, in order to first magnetic field to be provided.First line program and second line program provide second magnetic field and the 3rd magnetic field to change at least one magnetic axis direction of first free magnetic axis layer and second free magnetic axis layer respectively to combine first magnetic field respectively.Switchgear is coupled between reluctance type storage unit and one of first line program and the second line program person, has a control sluice.Character line is coupled to control sluice, in order to provide signal with the actuating switch device.
In addition, the utility model proposes another kind of magnetic random access memory circuit.The reluctance type storage unit of a plurality of serial connections has fixedly magnetic axis layer, free magnetic axis layer respectively, and is arranged at the insulation course between fixing magnetic axis layer and the free magnetic axis layer, and at this, the reluctance type storage unit has different magnetic resistance ratios.Bit line is coupled to the reluctance type storage unit of serial connection, in order to first magnetic field to be provided.A plurality of line program are arranged near the reluctance type storage unit separately, in order to provide second magnetic field with in conjunction with first magnetic field to change the impedance of corresponding reluctance type storage unit.Switchgear is coupled between one of reluctance type storage unit and the line program person, has a control sluice.The character linear system is coupled to control sluice, in order to provide signal with the actuating switch device.
In addition, the utility model proposes another kind of magnetic random access memory circuit.The first reluctance type storage unit has first fixedly magnetic axis layer, first free magnetic axis layer, and is arranged at first fixing first insulation course between magnetic axis layer and first free magnetic axis layer.The second reluctance type storage unit has second fixedly magnetic axis layer, second free magnetic axis layer, and is arranged at second fixing second insulation course between magnetic axis layer and second free magnetic axis layer.Direct and first and second reluctance type storage unit electric connection of bit line is in order to provide first magnetic field.Two programming linear systems are arranged near first and second free magnetic axis layer separately, in order to provide second magnetic field and the 3rd magnetic field with the magnetic axis direction of corresponding first and second free magnetic axis layer of change respectively in conjunction with first magnetic field respectively.Switchgear is coupled between one of first and second reluctance type storage unit and the line program person, has a control sluice.Character line is coupled to control sluice, in order to provide signal with the actuating switch device.
Description of drawings
Fig. 1 is the Organization Chart that shows traditional MRAM array;
Fig. 2 A and Fig. 2 B are the detailed structure view that shows mram cell 10;
Fig. 3 shows the magnetic field that bit line and line program are provided and the graph of a relation of MRAM switching condition;
Fig. 4 is the circuit framework figure that shows according to the described magnetic random access memory circuit of the utility model first embodiment;
Fig. 5 is the detailed structure view that shows according to the described reluctance type storage unit of the utility model first embodiment;
Fig. 6 is in the reluctance type storage unit that shows as shown in Figure 5, and the combination of each ferromagnetic layer magnetic axis direction is for the influence of total resistance;
Fig. 7 is the structural drawing that shows according to the storage unit of the described magnetic random access memory circuit of the utility model second embodiment;
Fig. 8 is in a plurality of reluctance type storage unit that show as shown in Figure 7, and the combination of different ferromagnetic layer magnetic axis directions is for the influence of the total resistance of serial connection;
Fig. 9 is the structural drawing of the storage unit of demonstration;
Figure 10 is that the combination of different ferromagnetic layer magnetic axis directions is for the influence of the total resistance of parallel connection in a plurality of reluctance type storage unit that show as shown in Figure 9;
Figure 11 is an example that shows according to the ferromagnetic layer structure of the described reluctance type storage unit with synthetic anti-ferromagnetic layer SAF of the utility model embodiment.
Symbol description:
10A, 10B, 41,51A, 51B, 61A, 61B～mram cell
12～electrode
14,46,55,66～transistor
13,104,45A, 45B, 55A, 55B, 61A, 61B～insulation course
16A, 16B, PL1, PL2～line program
102,42A, 42B, 52A, 52B, 62A, 62B～free magnetic axis layer
106,43, the magnetic axis layer of 53A, 53B, 63A, 63B～fixedly
108A, 108B～magnetic axis direction
40～storage unit
44,54A, 54B, 64A, 64B～inverse ferric magnetosphere
70,71A, 71B～ferromagnetic layer
72～conductive spacer
Bn, BL, BL1, BL2～bit line
H
t～transverse magnetic field
H
1, H
0～longitudinal magnetic field
W
m, W
M+1, WL1, WL2, WL～character line
Embodiment
The utility model proposes a kind of magnetic random access memory circuit.The reluctance type storage unit has fixedly magnetic axis layer, first free magnetic axis layer, second free magnetic axis layer, and is arranged at fixedly between the magnetic axis layer and first free magnetic axis layer respectively and the insulation course between first and second free magnetic axis layer.Bit line is to be coupled to the reluctance type storage unit, in order to first magnetic field to be provided.First line program and second line program provide second magnetic field and the 3rd magnetic field to change at least one magnetic axis direction of first free magnetic axis layer and second free magnetic axis layer respectively to combine first magnetic field respectively.Switchgear be coupled to reluctance type storage unit and first line program and second line program one between, have a control sluice.Character line is to be coupled to control sluice, in order to provide signal with the actuating switch device.
In addition, the utility model proposes another kind of magnetic random access memory circuit.The reluctance type storage unit of a plurality of serial connections has fixedly magnetic axis layer, free magnetic axis layer respectively, and is arranged at the insulation course between fixing magnetic axis layer and the free magnetic axis layer, and at this, the reluctance type storage unit has different magnetic resistance ratios.Bit line is the reluctance type storage unit that is coupled to serial connection, in order to first magnetic field to be provided.A plurality of line program are to be arranged at separately near the reluctance type storage unit, in order to provide second magnetic field with in conjunction with first magnetic field to change the impedance of corresponding reluctance type storage unit.Switchgear be coupled to reluctance type storage unit and line program one between, have a control sluice.Character line is to be coupled to control sluice, in order to provide signal with the actuating switch device.
In addition, the utility model proposes another kind of magnetic random access memory circuit.The first reluctance type storage unit has first fixedly magnetic axis layer, first free magnetic axis layer, and is arranged at first fixing first insulation course between magnetic axis layer and first free magnetic axis layer.The second reluctance type storage unit has second fixedly magnetic axis layer, second free magnetic axis layer, and is arranged at second fixing second insulation course between magnetic axis layer and second free magnetic axis layer.Bit line is direct and first and second reluctance type storage unit electrically connects, in order to first magnetic field to be provided.Two line program are to be arranged at separately near first and second free magnetic axis layer, in order to provide second magnetic field and the 3rd magnetic field to change the magnetic axis direction of first and second corresponding free magnetic axis layer respectively in conjunction with first magnetic field respectively.Switchgear be coupled to first and second reluctance type storage unit and line program one between, have a control sluice.Character line is to be coupled to control sluice, in order to provide signal with the actuating switch device.
First embodiment:
Consult Fig. 4, Fig. 4 is the circuit framework figure that shows according to the described magnetic random access memory circuit of the utility model first embodiment.Wherein, WL1 and WL2 are character line, and PL1～PL2 is a line program, and BL1～BL2 is a bit line.
At this framework with storage unit 40 is the example explanation, and all the other each storage unit have identical structure, do not repeat them here to simplify explanation.Storage unit 40 has reluctance type storage unit 41, and its detailed structure as shown in Figure 5.Fig. 5 is the detailed structure view that shows according to the described reluctance type storage unit of the utility model first embodiment.In reluctance type storage unit 41, have a plurality of ferromagnetic layers, comprise a plurality of free magnetic axis layer 42A and 42B and fixing magnetic axis layer 43.And inverse ferric magnetosphere 44 is the magnetic axis directions in order to fixed ferromagnetic layer 43, makes it become fixedly magnetic axis layer.At this, the material of above-mentioned ferromagnetic layer is all made by ferronickel or ferro- cobalt.Insulation course 45A and 45B are arranged at respectively between above-mentioned ferromagnetic layer 42A and 42B and 42B and 43, and its material can be aluminium oxide (Al
2O
3).According to the utility model embodiment, each the reluctance type storage unit in the storage unit 40 has different impedances under identical conducting state.In first embodiment, the ferromagnetic layer 42A of reluctance type storage unit and 42B and the formed passage of insulation course 45A meet magnetic resistance ratio (the magnetroresistance ratio that the magnetic resistance ratio of face and ferromagnetic layer 42A and 42B and the formed passage of insulation course 45A connect face, the MR ratio) also inequality, suppose to be respectively 30% and 60%, and it is also inequality to switch critical magnetic field.The MR ratio is defined as the ratio of reluctance type storage unit in the resistance value of the impedance value difference of high impedance status and low impedance state and low impedance state, and the MR ratio value is material and the processing procedure that is decided by ferromagnetic layer and therebetween insulation course.
Consult Fig. 4, bit line BL1 is direct and reluctance type storage unit 41 electrically connects, and reads the electric current and first program current in order to provide.Line program PL1 is arranged near the reluctance type storage unit 41, and in order to one second magnetic field to be provided, first magnetic field that is produced with first program current that is provided in conjunction with bit line BL1 is with the magnetic axis direction of the free magnetic axis layer that changes the reluctance type storage unit.Can be connected by an insulation course between line program and the reluctance type storage unit.
Switchgear 46 is a nmos pass transistor, and its drain is to be coupled to above-mentioned reluctance type storage unit 41, and its source electrode is to be coupled to line program PL1.Character line WL1 is the grid that is coupled to switchgear 46, in order to provide Continuity signal with actuating switch device 46.
Fig. 6 is in the reluctance type storage unit that shows as shown in Figure 5, the combination of each ferromagnetic layer magnetic axis direction is for the influence of total resistance, resistance value described in the figure is only for illustrating, suppose that free magnetic axis layer 2, insulation course 2 and free magnetic axis layer 1 are when the magnetic axis direction is identical, its resistance value is 1 ohm, when the magnetic axis direction was opposite, its resistance value was 1.3 ohm; Free magnetic axis layer 1, insulation course 1 and fixedly magnetic axis layer is when the magnetic axis direction is identical, its resistance value is 1 ohm, when the magnetic axis direction was opposite, its resistance value was 1.6 ohm; Wherein, free magnetic axis layer 2 is represented the free magnetic axis layer 42A of reluctance type storage unit, free magnetic axis layer 1 is represented the free magnetic axis layer 42B of reluctance type storage unit, and fixedly magnetic axis layer is represented the fixedly magnetic axis layer 43 of reluctance type storage unit, and insulation course 2 is represented insulation course 45A, insulation course 1 is represented insulation course 45B, has 30% and 60% MR ratio respectively.Therefore, above-mentioned as can be known ferromagnetic layer has different resistance values when different magnetic axis direction configurations.
When will be when reluctance type storage unit 41 writes data, reach the purpose that write data by the magnetic axis direction that bit line BL and line program PL1 provide first program current and the second program current specific free magnetic axis layer to produce enough magnetic field and change reluctance type storage unit 41 respectively this moment.At this moment, the lead of character line WL1 and other storage unit ground connection all.As mentioned above, to connect the switching field of face also inequality because ferromagnetic layer 42A and 42B and the formed passage of insulation course 45A meet the magnetic resistance ratio of face and ferromagnetic layer 42A and 42B and the formed passage of insulation course 45A, therefore by the size of adjusting second program current, can adjust the magnetic axis direction of corresponding free magnetic axis layer.As shown in Figure 6, suppose that default magnetic axis direction configuration is a configuration 1, free magnetic axis layer 1 is all to the right with 2 magnetic axis direction, and the critical magnetic field of switching free magnetic axis layer 2 magnetic axis directions is the critical magnetic field less than switching free magnetic axis layer 1 magnetic axis direction.Therefore, if will write the data of configuration 2 time, switch the magnetic axis direction of free magnetic axis layer 2 by first total magnetic field of adjusting line program and bit line and being provided.Because the switching field of the magnetic axis direction of free magnetic axis layer 1 is bigger, therefore this moment, its magnetic axis direction can't change, and promptly write the data of configuration 2.If will write the data of configuration 3 time, switch the magnetic axis direction of free magnetic axis layer 1 by second total magnetic field of adjusting line program and bit line and being provided.Because the switching field of the magnetic axis direction of free magnetic axis layer 1 is bigger, therefore second total magnetic field is greater than first total magnetic field.When applying second total magnetic field, can switch the magnetic axis direction of free magnetic axis layer 1 simultaneously, therefore can directly write the data of configuration 3 by applying second total magnetic field by configuration 1.If in the time of will writing the data of configuration 4, must carry out twice data write activity this moment.That is, applying second total magnetic field earlier the reluctance type storage unit is switched to configuration 3 by configuration 1, the magnetic axis direction that provides the first anti-phase total magnetic field to change free magnetic axis layer 2 during again by configuration 3 can be finished the data write activity of configuration 4.
When wanting the stored data of reading cells 40, the voltage level of character line WL1 is pulled up to high levels, and with line program PL1 ground connection, in addition, other lead is suspension joint all.Provide one to read electric current in bit line BL1 this moment.Reading electric current flows through bit line BL1, reluctance type storage unit 41, switchgear 46 and line program PL1 and flow to earth point.Then, by the voltage level of detecting position BL1, can reading cells 40 stored data.
According to shown in Figure 6, because the resulting impedance of reluctance type storage unit 41 has nothing in common with each other under different configuration, when reading electric current and flow to earth point by bit line, the accurate difference in position of bit line that different configuration causes can be learnt by general circuit for detecting, die, can store the data of a plurality of characters according to the described storage unit of the utility model first embodiment.
Second embodiment:
Consult Fig. 7, Fig. 7 is the structural drawing that shows according to the storage unit of the described magnetic random access memory circuit of the utility model second embodiment.Wherein, WL is a character line, and BL is a bit line.At this, the circuit structure of single memory cell only is discussed, entire circuit framework and Fig. 4 are similar, and difference only is the difference of storage unit inner structure.According to the utility model second embodiment, the position of line program PL1 and PL2 is arranged at respectively near a plurality of reluctance type storage unit 51A and the 51B, the mode of its setting can be by being arranged on the different metal layer, to obtain independently applying the effect of magnetic field to corresponding reluctance type storage unit.In addition, each reluctance type storage unit has a plurality of ferromagnetic layers respectively, comprises free magnetic axis layer 52A and 52B and fixedly magnetic axis layer 53A and 53B.And inverse ferric magnetosphere 54A and 54B are respectively in order to the magnetic axis direction of fixed ferromagnetic layer 53A and 53B, make it become fixedly magnetic axis layer.In addition, in free magnetic axis layer 52A and 52B and fixedly have insulation course 55A and 55B respectively between magnetic axis layer 53A and the 53B.
Switchgear 55 is a nmos pass transistor, and its drain is to be coupled to above-mentioned reluctance type storage unit 51B, and its source electrode is to be coupled to line program PL2.Character line WL is the grid that is coupled to switchgear 55, in order to provide Continuity signal with actuating switch device 55.
According to the utility model embodiment, each the reluctance type storage unit in the storage unit has different MR ratios.Fig. 8 is in a plurality of reluctance type storage unit that show as shown in Figure 7, the combination of different ferromagnetic layer magnetic axis directions is for the influence of the total resistance of serial connection, resistance value described in the figure is only for illustrating, suppose that free magnetic axis layer 2 and fixing magnetic axis layer are when the magnetic axis direction is identical, its resistance value is 1 ohm, when the magnetic axis direction was opposite, its resistance value was 1.3 ohm; Free magnetic axis layer 1 is with fixedly magnetic axis layer is when the magnetic axis direction is identical, and its resistance value is 1 ohm, and when the magnetic axis direction was opposite, its resistance value was 1.6 ohm; Wherein, free magnetic axis layer 2 is represented the free magnetic axis layer 52A of reluctance type storage unit, free magnetic axis layer 1 is represented the free magnetic axis layer 52B of reluctance type storage unit, and fixedly magnetic axis layer is represented the fixedly magnetic axis layer 53A and the 53B of reluctance type storage unit, and insulation course 2 is represented insulation course 55A, insulation course 1 is represented insulation course 55B, has 30% and 60% MR ratio respectively.Therefore, above-mentioned as can be known ferromagnetic layer has different resistance values when different magnetic axis direction configurations.
When will be when writing data according to the described storage unit of the utility model second embodiment, respectively provide first program current and second program current or three program current to produce magnetic field respectively to change the free magnetic axis layer 52A of reluctance type storage unit 51A or reluctance type storage unit 51B and the magnetic axis direction of 52B by bit line BL and line program PL1 or line program PL2 this moment, reaches the purpose that writes data.At this moment, the lead of character line WL1 and other storage unit ground connection all.As shown in Figure 8, suppose that default magnetic axis direction configuration is a configuration 1, free magnetic axis layer 1 and 2 magnetic axis direction are all to the right.Therefore, if will write the data of configuration 2 time, the magnetic axis direction of free magnetic axis layer 2 is switched in first total magnetic field that is provided by line program PL1 and bit line BL, promptly writes the data of configuration 2.If will write the data of configuration 3 time, switch the magnetic axis direction of free magnetic axis layer 1 by adjusting line program PL2 with second total magnetic field that bit line BL is provided, so can directly write the data of configuration 3 by applying second total magnetic field by configuration 1.If will write the data of configuration 4 time, only need to change the magnetic axis direction of free magnetic axis layer 1 and 2 this moment respectively at the magnetic field that line program PL1 and PL2 provide program current to combine bit line to provide, can finish the data write activity of configuration 4.
When will be when storage unit writes with reading of data, its action be identical with first embodiment, does not repeat them here to simplify explanation.
According to shown in Figure 8, because the reluctance type storage unit 51A with different MR ratios of serial connection and the resulting impedance of 51B have nothing in common with each other under different configuration, when reading electric current and flow to earth point by bit line, the accurate difference in position of bit line that different configuration causes can be learnt by general circuit for detecting, die, can store the data of a plurality of characters according to the described storage unit of the utility model second embodiment.
The 3rd embodiment:
Consult Fig. 9, Fig. 9 is the structural drawing that shows according to the storage unit of the described magnetic random access memory circuit of the utility model the 3rd embodiment.Wherein, WL is a character line, and BL is a bit line.At this, the circuit structure of single memory cell only is discussed, entire circuit framework and Fig. 4 are similar, and difference only is the difference of storage unit inner structure.According to the utility model the 3rd embodiment, a plurality of reluctance type storage unit 61A and 61B directly are coupled to bit line BL, have a plurality of ferromagnetic layers respectively, comprise free magnetic axis layer 62A and 62B and fixedly magnetic axis layer 63A and 63B.And inverse ferric magnetosphere 64A and 64B are respectively in order to the magnetic axis direction of fixed ferromagnetic layer 63A and 63B, make it become fixedly magnetic axis layer.In addition, in free magnetic axis layer 62A and 62B and fixedly have insulation course 65A and 65B respectively between magnetic axis layer 63A and the 63B.
The position of line program PL1 and PL2 is arranged at respectively near reluctance type storage unit 61A and the 61B, changes the magnetic axis direction of the free magnetic axis layer of reluctance type storage unit 61A and 61B in order to corresponding magnetic field to be provided respectively.In addition, switchgear 66 is a nmos pass transistor, and its drain is to be coupled to above-mentioned reluctance type storage unit 61A and 61B, and its source electrode is to be coupled to line program PL2.Character line WL is the grid that is coupled to switchgear 66, in order to provide Continuity signal with actuating switch device 66.
According to the utility model the 3rd embodiment, each the reluctance type storage unit in the storage unit has different MR ratios.Figure 10 is in a plurality of reluctance type storage unit that show as shown in Figure 9, the combination of different ferromagnetic layer magnetic axis directions is for the influence of the total resistance of parallel connection, resistance value described in the figure is only for illustrating, suppose that free magnetic axis layer 2 and fixing magnetic axis layer are when the magnetic axis direction is identical, its resistance value is 1 ohm, when the magnetic axis direction was opposite, its resistance value was 1.25 ohm; Free magnetic axis layer 1 is with fixedly magnetic axis layer is when the magnetic axis direction is identical, and its resistance value is 1 ohm, and when the magnetic axis direction was opposite, its resistance value was 1.58 ohm; Wherein, free magnetic axis layer 2 is represented the free magnetic axis layer 62A of reluctance type storage unit, free magnetic axis layer 1 is represented the free magnetic axis layer 62B of reluctance type storage unit, and fixedly magnetic axis layer is represented the fixedly magnetic axis layer 63A and the 63B of reluctance type storage unit, and insulation course 2 is represented insulation course 65A, insulation course 1 is represented insulation course 65B, has 25% and 58% MR ratio respectively.Therefore, above-mentioned as can be known ferromagnetic layer has different resistance values when different magnetic axis direction configurations.
When will be when writing data according to the described storage unit of the utility model the 3rd embodiment, respectively provide first program current and second program current or three program current to produce magnetic field respectively to change the free magnetic axis layer 62A of reluctance type storage unit 61A or reluctance type storage unit 61B and the magnetic axis direction of 62B by bit line BL and line program PL1 or line program PL2 this moment, reaches the purpose that writes data.At this moment, the lead of character line WL1 and other storage unit ground connection all.As shown in Figure 8, suppose that default magnetic axis direction configuration is a configuration 1, free magnetic axis layer 1 and 2 magnetic axis direction are all to the right.Therefore, if will write the data of configuration 2 time, the magnetic axis direction of free magnetic axis layer 2 is switched in first total magnetic field that is provided by line program PL1 and bit line BL, promptly writes the data of configuration 2.If will write the data of configuration 3 time, switch the magnetic axis direction of free magnetic axis layer 1 by adjusting line program PL2 with second total magnetic field that bit line BL is provided, so can directly write the data of configuration 3 by applying second total magnetic field by configuration 1.If will write the data of configuration 4 time, only need to change the magnetic axis direction of free magnetic axis layer 1 and 2 this moment respectively at the magnetic field that line program PL1 and PL2 provide program current to combine bit line to provide, can finish the data write activity of configuration 4.
When will be when storage unit writes with reading of data, its action be identical with first embodiment, does not repeat them here to simplify explanation.
According to shown in Figure 10, because reluctance type storage unit 61A in parallel has different MR ratios with 61B, therefore its resulting impedance has nothing in common with each other under different configuration, when reading electric current and flow to earth point by bit line, the accurate difference in position of bit line that different configuration causes can be learnt by general circuit for detecting, die, can store the data of a plurality of characters according to the described storage unit of the utility model the 3rd embodiment.
In addition, according to the utility model, ferromagnetic layer described in the various embodiments described above (comprise free magnetic axis layer and fixedly free magnetic axis layer etc.), all can adopt synthetic anti-ferromagnetic layer (synthetic antiferromagnetlayer in addition, SAF) structure, as shown in figure 11, the feature of its structure is in ferromagnetic layer 70, utilizing a conductive spacer 72 that ferromagnetic layer is separated is two ferromagnetic layer 71A and the 71B that separate, and makes whole SAF structure have the magnetic line of force of sealing to avoid the interference to other ferromagnetic layers.Wherein, above-mentioned conductive spacer can use ruthenium (Ruthenium) metal to be material.
In sum, circuit according to magnetic random access memory provided by the utility model has the storage unit that is made of a plurality of mram cell, and the mram cell in each storage unit has different impedances, therefore, the storage unit of each storage unit can store the data of a plurality of characters.In the disclosed embodiment of the utility model, the resistance value of each mram cell and MR ratio all can be adjusted voluntarily by the deviser.Moreover a plurality of mram cells in the said memory cells are to share single switchgear, in conventional art, the number of switchgear must with the same number of situation of mram cell, significantly improve the integration of circuit and the size of storer.
Though the utility model discloses as above with preferred embodiment; so it is not in order to limit scope of the present utility model; anyly have the knack of this skill person; in not breaking away from spirit and scope of the present utility model; when doing a little change and retouching, therefore protection domain of the present utility model is as the criterion when looking accompanying the claim person of defining.
Claims (18)
1. reluctance type storage unit is characterized in that comprising:
One first free magnetic axis layer and one second free magnetic axis layer;
One fixing magnetic axis layer; And
A plurality of insulation courses are arranged at respectively between above-mentioned first and second free magnetic axis layer, and be arranged at said fixing magnetic axis layer and above-mentioned first free magnetic axis layer and second free magnetic axis layer one between, wherein above-mentioned insulation course has different magnetic resistance ratios.
2. reluctance type storage unit as claimed in claim 1 is characterized in that: the magnetic resistance ratio of above-mentioned insulation course is according to said fixing magnetic axis layer, first free magnetic axis layer, second free magnetic axis layer, and the material of above-mentioned insulation course determines.
3. magnetic random access memory circuit is characterized in that comprising:
One reluctance type storage unit, have fixedly magnetic axis layer, one first free magnetic axis layer, one second free magnetic axis layer, and be arranged between the said fixing magnetic axis layer and first free magnetic axis layer respectively and a plurality of insulation courses between above-mentioned first and second free magnetic axis layer;
One bit line is coupled to above-mentioned reluctance type storage unit, in order to one first magnetic field to be provided;
One first line program and one second line program provide one second magnetic field and one the 3rd magnetic field respectively, to change at least one magnetic axis direction of above-mentioned first free magnetic axis layer and second free magnetic axis layer respectively in conjunction with above-mentioned first magnetic field;
One switchgear, be coupled to above-mentioned reluctance type storage unit and above-mentioned first line program and second line program one between, and have a control sluice; And
One character line is coupled to above-mentioned control sluice, in order to provide a signal with the above-mentioned switchgear of conducting.
4. magnetic random access memory circuit as claimed in claim 3, it is characterized in that: when carrying out the programming action, above-mentioned character line ground connection, and first magnetic field that above-mentioned bit line provided is with at least one combines and changes at least one magnetic axis direction of above-mentioned first and second free magnetic axis layer by first line program and second magnetic field that second line program provided and the 3rd magnetic field respectively, to change the impedance of above-mentioned reluctance type storage unit.
5. magnetic random access memory circuit as claimed in claim 3, it is characterized in that: when action is read in execution, above-mentioned character line provides above-mentioned signal with the above-mentioned switchgear of conducting, and above-mentioned bit line provides one to read the electric current above-mentioned reluctance type storage unit of flowing through, flow to one of first line program that above-mentioned switchgear couples and second line program via above-mentioned switchgear, and read the data that are stored in above-mentioned reluctance type storage unit according to the voltage level of above-mentioned bit line.
6. magnetic random access memory circuit as claimed in claim 3 is characterized in that: above-mentioned insulation course has different magnetic resistance ratios.
7. magnetic random access memory circuit as claimed in claim 6 is characterized in that: the magnetic resistance ratio of above-mentioned insulation course is according to said fixing magnetic axis layer, first free magnetic axis layer, second free magnetic axis layer, and the material of above-mentioned insulation course determines.
8. magnetic random access memory circuit as claimed in claim 3 is characterized in that: above-mentioned first line program and second line program are adjacent to respectively near above-mentioned first free magnetic axis layer and second free magnetic axis layer.
9. magnetic random access memory circuit as claimed in claim 3 is characterized in that: above-mentioned switchgear is a transistor.
10. magnetic random access memory circuit is characterized in that comprising:
The reluctance type storage unit of a plurality of serial connections has fixedly magnetic axis layer, a free magnetic axis layer respectively, and is arranged at the insulation course between said fixing magnetic axis layer and the free magnetic axis layer, and above-mentioned reluctance type storage unit has different magnetic resistance ratios;
One bit line is coupled to the reluctance type storage unit of above-mentioned serial connection, in order to one first magnetic field to be provided;
A plurality of line program are arranged near the above-mentioned reluctance type storage unit separately, in order to one second magnetic field to be provided, with in conjunction with above-mentioned first magnetic field to change the impedance of corresponding reluctance type storage unit;
One switchgear, be coupled to above-mentioned reluctance type storage unit and above-mentioned line program one between, and have a control sluice; And
One character line is coupled to above-mentioned control sluice, in order to provide a signal with the above-mentioned switchgear of conducting.
11. magnetic random access memory circuit as claimed in claim 10, it is characterized in that: when carrying out the programming action, above-mentioned character line is a ground connection, and first magnetic field that above-mentioned bit line and line program are provided and second magnetic field change the magnetic axis direction of free magnetic axis layer of the pairing reluctance type storage unit of above-mentioned line program to change the impedance of above-mentioned reluctance type storage unit.
12. magnetic random access memory circuit as claimed in claim 10, it is characterized in that: when action is read in execution, above-mentioned character line provides above-mentioned signal with the above-mentioned switchgear of conducting, and above-mentioned bit line provides one to read the electric current above-mentioned reluctance type storage unit of flowing through, flow to the line program that above-mentioned switchgear couples via above-mentioned switchgear, and read the data that are stored in above-mentioned a plurality of reluctance type storage unit according to the voltage level of above-mentioned bit line.
13. magnetic random access memory circuit as claimed in claim 10 is characterized in that: the distance of above-mentioned line program and corresponding reluctance type storage unit less than with the distance of non-corresponding reluctance type storage unit.
14. magnetic random access memory circuit as claimed in claim 10 is characterized in that: above-mentioned switchgear is a transistor.
15. a magnetic random access memory circuit is characterized in that comprising:
One first reluctance type storage unit has one first fixedly magnetic axis layer, one first free magnetic axis layer, and is arranged at above-mentioned first fixing first insulation course between magnetic axis layer and first free magnetic axis layer;
One second reluctance type storage unit, have one second fixedly magnetic axis layer, one second free magnetic axis layer, and being arranged at above-mentioned second fixing second insulation course between magnetic axis layer and above-mentioned second free magnetic axis layer, the above-mentioned second reluctance type storage unit is in parallel with the above-mentioned first reluctance type storage unit;
One bit line directly electrically connects with above-mentioned first and second reluctance type storage unit, in order to one first magnetic field to be provided;
Two line program are arranged near above-mentioned first and second free magnetic axis layer separately, in order to one second magnetic field and one the 3rd magnetic field to be provided respectively, to change the magnetic axis direction of first and second corresponding free magnetic axis layer respectively in conjunction with above-mentioned first magnetic field;
One switchgear, be coupled to the tie point of above-mentioned first and second reluctance type storage unit and above-mentioned line program one between, and have a control sluice; And
One character line is coupled to above-mentioned control sluice, in order to provide a signal with the above-mentioned switchgear of conducting.
16. magnetic random access memory circuit as claimed in claim 15, it is characterized in that: when carrying out the programming action, above-mentioned character line is a ground connection, and first magnetic field that above-mentioned bit line provided is with at least one combines and changes at least one magnetic axis direction of above-mentioned first and second free magnetic axis layer by first line program and second magnetic field that second line program provided and the 3rd magnetic field respectively.
17. magnetic random access memory circuit as claimed in claim 15, it is characterized in that: when action is read in execution, above-mentioned character line provides above-mentioned signal with the above-mentioned switchgear of conducting, and above-mentioned bit line provides one to read electric current above-mentioned first and second reluctance type storage unit of flowing through, flow to the line program that above-mentioned switchgear couples via above-mentioned switchgear, and read the data that are stored in above-mentioned first and second reluctance type storage unit according to the voltage level of above-mentioned bit line.
18. magnetic random access memory circuit as claimed in claim 15 is characterized in that: above-mentioned switchgear is a transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200420084310 CN2757293Y (en) | 2003-07-17 | 2004-07-13 | Magnetic resistance type storage unit and magnetic resistance type random access storage circuit |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN03145942 | 2003-07-17 | ||
| CN03145942.0 | 2003-07-17 | ||
| CN 200420084310 CN2757293Y (en) | 2003-07-17 | 2004-07-13 | Magnetic resistance type storage unit and magnetic resistance type random access storage circuit |
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| Publication Number | Publication Date |
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| CN2757293Y true CN2757293Y (en) | 2006-02-08 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 200420084310 Expired - Lifetime CN2757293Y (en) | 2003-07-17 | 2004-07-13 | Magnetic resistance type storage unit and magnetic resistance type random access storage circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100461292C (en) * | 2003-07-17 | 2009-02-11 | 台湾积体电路制造股份有限公司 | Magnetic resistance type memory unit and magnetic resistance type random access storage device circuit |
| CN101546598B (en) * | 2008-03-27 | 2011-12-14 | 台湾积体电路制造股份有限公司 | Magnetoresistive random access memory device, switching method thereof and memory array |
-
2004
- 2004-07-13 CN CN 200420084310 patent/CN2757293Y/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100461292C (en) * | 2003-07-17 | 2009-02-11 | 台湾积体电路制造股份有限公司 | Magnetic resistance type memory unit and magnetic resistance type random access storage device circuit |
| CN101546598B (en) * | 2008-03-27 | 2011-12-14 | 台湾积体电路制造股份有限公司 | Magnetoresistive random access memory device, switching method thereof and memory array |
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