CN2710107Y - Magnetoresistive random access store circuit - Google Patents
Magnetoresistive random access store circuit Download PDFInfo
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- CN2710107Y CN2710107Y CN 200420049602 CN200420049602U CN2710107Y CN 2710107 Y CN2710107 Y CN 2710107Y CN 200420049602 CN200420049602 CN 200420049602 CN 200420049602 U CN200420049602 U CN 200420049602U CN 2710107 Y CN2710107 Y CN 2710107Y
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Abstract
The utility model discloses a magnetoresistive random access store circuit which includes a magnetoresistive memory cell and is provided with a fixed magnetic axis layer, a free magnetic axis layer and an insulating layer arranged between the fixed magnetic axis layer and the free magnetic axis layer. A first switch device is coupled with one end of the fixed magnetic axis layer and is provided with a first control lock. A second switch device is coupled with the free magnetic axis layer and is provided with a second control lock. A bit line is coupled with the second switch device and is used to provide the read electric current when reading the action. A first programming thread is coupled with one end of the fixed magnetic axis layer and is used to provide the programming electric current when executing the programming action. A second programming thread is coupled with the first switch device. A character thread is coupled with the first control lock and the second control lock and is used to provide the actuating signal to communicate the first switch device and the second switch device.
Description
Technical field
The utility model relates to a kind of storage array, particularly relevant for a kind of storage array of magnetic random access memory.
Background technology
Magnetic random access memory (Magnetic Random Access Memory, be designated hereinafter simply as MRAM) be a kind of metallicl magnetic material, its radiation resistance is more high than semiconductor material, belong to non-volatility memorizer (Non-volatile Random Access Memory), in the time of computer circuit breaking, shutdown, still can keep storage property.
MRAM utilizes magnetoresistance characteristics store recording information, has low power consuming, the non-volatile and characteristic of not having read-write number of times restriction.The ultimate principle of its running is the same with storage data on hard disk, and data are foundation with the direction of magnetic, save as 0 or 1, and stored data has permanent, after by extraneous influence of magnetic field, just can change this magnetic data.
Fig. 1 is the Organization Chart that shows traditional MRAM array.The top of mram cell 10A and 10B is to be coupled to bit line B
n, and its bottom is to be coupled to electrode 12.The grid of transistor 14 is to be coupled to character line (W
m, W
M+1), source electrode is a ground connection, and its drain is to be respectively coupled to corresponding electrode 12.In order to have an insulation course 13 between the data line (16A, 16B) that writes data and the electrode 12, in order to isolate data line 16A, 16B and electrode 12.
Fig. 2 A and Fig. 2 B are the detailed structure view that shows mram cell 10.Electric current can vertically see through insulation course (tunnel junction) 104 by a free magnetic axis layer 102 and flow through (or passing) fixedly magnetic axis layer 106.The magnetic axis direction of free magnetic axis layer 102 can be subjected to the influence in other magnetic field and change, and fixedly the magnetic axis direction of magnetic axis layer 106 is fixed, and its magnetic axis direction is respectively shown in the label 108A and 108B of Fig. 2 A and Fig. 2 B.As free magnetic axis layer 102 when fixedly the magnetic axis direction of magnetic axis layer 106 is same direction (shown in Fig. 2 A), mram cell has low-resistance situation, and when free magnetic axis layer 102 when fixedly magnetic axis layer 106 is different directions, then mram cell just has and has high-resistance speciality.Consult Fig. 1, the magnetic axis direction of free magnetic axis layer 102 is the magnetic field that produces by data line 16A, 16B and the magnetic field that produces in conjunction with the bit line and change.
The spin flip conversion magnetic field of each mram cell is by the bit line B that flows through
nWith the current field of data line common synthetic.Then have only the magnetic axis of selecteed mram cell to reverse through moving thus, and the action of smooth record.As for non-selected storage element part, then have only one of them person of bit line or data line can be applied in current field, therefore can't form enough reversing magnetic fields, so can't carry out the information write activity.
The magnetic field that electric current produced of above-mentioned bit line and data line must can make the MRAM array normally carry out the programming action through accurate design.Consult Fig. 3, Fig. 3 shows the magnetic field that bit line and data line are provided and the graph of a relation of MRAM switching condition.Transverse magnetic field H
tBe that electric current by the bit line is provided, and longitudinal magnetic field H
1Be that electric current by data line is provided, and do not having transverse magnetic field H
tSituation under, longitudinal magnetic field H
1Be H
0The time, will cause mram cell to switch its conducting degree.If transverse magnetic field H is arranged
tExistence, the critical value that switch mram cell this moment will reduce, and therefore, apply than H
0Little longitudinal magnetic field H
1Can make mram cell switch its conducting state.
In the formed regional A of dotted line, mram cell is first conducting state (is example with the high impedance), and the part beyond regional A, mram cell will be subjected to the influence in magnetic field and switch to another conducting state (is example with the Low ESR).
When reading the MRAM data, be example with mram cell 10A, this moment, character line Wm turn-on transistor 14, and according to the conducting state of mram cell 10A, can determine bit line B
nWhether the electric current that is provided can be via mram cell 10A, transistor 14 and is flow to earth point, uses the stored data of mram cell 10A that reads.
In write step, because the size in magnetic field and the kernel of section of electric current distance are inversely proportional to, under the framework of traditional MRAM array, if have program current on the data line 16A, the magnetic field that data line 16A is produced is except changing the conducting state of mram cell 10A, be arranged in the MRAM array, the mram cell of the full line at and mram cell 10A place parallel with data line 16A, its magnetic axis direction can be subjected to the influence of magnetic field that data line 16A is produced equally, even the mram cell 10B that is positioned at another row can be affected equally, therefore, the magnetic field supplied of data line 16A can not be excessive.
In addition, when the magnetic field that data line 16A is supplied is too small, can cause the conducting state of mram cell 10A to switch.Therefore, the bit line of traditional MRAM array and the magnitude of current of data line must can make the MRAM array normally carry out the programming action through accurate design.
That is when if the magnetic field supplied of data line 16A is excessive, this moment, no doubt mram cell 10A can write data, and so other mram cell also might so be written into data, causes misprogrammed (programming disturb).And when the magnetic field that data line 16A is supplied is too small, can't reach the effect of the data of writing again to specific mram cell.
Yet, if the magnitude of current of bit line and data line must be controlled ground so accurately, disturb as external magnetic field, or external environment condition is when occur changing (as temperature, humidity etc.), will certainly cause misprogrammed, show that tradition needs the MRAM framework of accurate control programming electric current to have the not good shortcoming of fiduciary level.
Therefore, integrated circuit manufacturing company in Taiwan proposes a kind of magnetic random access memory circuit to overcome above-mentioned shortcoming.Fig. 4 is the configuration diagram of the magnetic-resistance random access storage unit (MRAM cell) that shows that Taiwan integrated circuit manufacturing company is proposed.
The free magnetic axis layer of mram cell 40A and 40B is the bit line B that is electrically connected at a set direction configuration
n, and the fixedly magnetic axis layer of mram cell 40A and 40B is to be electrically connected at data line 42A and 42B respectively.Because the distance of free magnetic axis layer and data line only is several dusts (angstrom) (scope is about the 8-15 dust), therefore can receive very big magnetic field.So,, only need a spot of program current I compared to known techniques
WCan change the magnetic axis direction of free magnetic axis layer 102, therefore reach the effect of power saving.In addition, consult Fig. 4, the distance of data line 42A and mram cell 40A is very less than the distance of itself and mram cell 40B, therefore data line 42A, therefore can not change the impedance of adjacent mram cell 40B and the situation of misprogrammed takes place much larger than the influence to mram cell 40B the influence of mram cell 40A.
Fig. 5 is the Organization Chart that shows magnetic-resistance random access storage array (MRAM) circuit as described in Figure 4.In Fig. 5, for simplified, the display data line in fact, can not be considered as one with the fixedly magnetic axis layer of data line and mram cell.
When will be when mram cell 50 writes data, this moment storage array peripheral circuit selected word line W
m, and suspension joint bit line B
n, and by line program PL supply program current I
WOwing to character line W this moment
mBe high levels, so transistor 52A and 52B conducting, so program current I
WThe conducting state of flowing through mram cell 50 and changing mram cell 50 is to reach the purpose of the data of writing.
In the time will reading the stored data of mram cell 50, peripheral circuit is chosen the character line W under this mram cell 50
m, and line program PL, PL ground connection, this moment is in bit line B
nProvide and read electric current I
rMake its line program PL, PL of flowing to ground connection via transistor 52A, the 52B of mram cell 50 and conducting, be pursuant to the magnitude of voltage that bit line Bn detected again and learn mram cell stored data 50 this moment.
Yet when carrying out the programming action in foregoing circuit, program current must flow through transistor 52A and 52B because program current is quite big, therefore must strengthen the area of transistor 52A and 52B to bear a large amount of program currents.But, so but can cause the size of whole storage array to become big, make the development of dwindling of MRAM memory array size meet with technical bottleneck.
Summary of the invention
In view of this, in order to address the above problem, the utility model fundamental purpose is to provide a kind of magnetic-resistance random access storage array circuit, can effectively reduce the size of present MRAM storage array.
For obtaining above-mentioned purpose, the utility model proposes a kind of magnetic random access memory circuit, comprise following assembly.The reluctance type storage unit has fixedly magnetic axis layer, free magnetic axis layer, and is arranged at the insulation course between fixing magnetic axis layer and the free magnetic axis layer.First switchgear is to be coupled to a fixedly end of magnetic axis layer, and has first control sluice.The second switch device is to be coupled to free magnetic axis layer, and has second control sluice.The bit line is to be coupled to the second switch device, provides when being used to read action and reads electric current.First line program is to be coupled to the fixedly other end of magnetic axis layer, and program current is provided when being used to carry out the programming action.Second line program is to be coupled to first switchgear.Character line is to be coupled to first control sluice and second control sluice, in order to provide enable signal with conducting first switchgear and second switch device.
In addition, the utility model proposes a kind of magnetic random access memory circuit, comprise following assembly.The reluctance type storage unit has fixedly magnetic axis layer, free magnetic axis layer, and is arranged at the insulation course between fixing magnetic axis layer and the free magnetic axis layer.First pilot wire is to be coupled to a fixedly end of magnetic axis layer, provides when being used to read action to read electric current and program current is provided when programming.First switchgear is to be coupled to free magnetic axis layer, and has first control sluice.The second switch device is to be coupled to the fixedly other end of magnetic axis layer, and has second control sluice.First alternative line is to be coupled to first control sluice, chooses signal in order to provide first.Second alternative line is to be coupled to second control sluice, chooses signal in order to provide second.Second pilot wire is to be coupled to first switchgear and second switch device.
In addition, the utility model proposes a kind of magnetic random access memory circuit, comprise following assembly.A plurality of reluctance type storage unit have fixedly magnetic axis layer, free magnetic axis layer, and are arranged at the insulation course between fixing magnetic axis layer and the free magnetic axis layer.First pilot wire is to be coupled to a fixedly end of magnetic axis layer, provides when being used to read action to read electric current and program current is provided when programming.A plurality of character lines are coupled to free magnetic axis layer, provide when being used to read action and read electric current.A plurality of first switchgears are the two ends that are coupled to the fixedly magnetic axis layer of a reluctance type storage unit.A plurality of second switch devices are the two ends that are coupled to the fixedly magnetic axis layer of another reluctance type storage unit.A plurality of line program are to be coupled between first switchgear and the second switch device.First character line is to be coupled to above-mentioned first switchgear.And second character line is to be coupled to above-mentioned second switch device.
Description of drawings
Fig. 1 is the Organization Chart that shows traditional MRAM array.
Fig. 2 A and Fig. 2 B are the detailed structure view that shows mram cell 10.
Fig. 3 shows the magnetic field that bit line and data line are provided and the graph of a relation of MRAM switching condition.
Fig. 4 is the configuration diagram that shows another traditional magnetic-resistance random access storage unit (MRAM cell).
Fig. 5 is the Organization Chart that shows magnetic-resistance random access storage array (MRAM) circuit as described in Figure 4.
Fig. 6 is the structural drawing that shows according to the described magnetic-resistance random access storage of the utility model embodiment (MRAM) unit.
Fig. 7 is the Organization Chart that shows according to the described magnetic-resistance random access storage array of the utility model first embodiment (MRAM) circuit.
Fig. 8 is the Organization Chart that shows according to the described magnetic-resistance random access storage array of the utility model second embodiment (MRAM) circuit.
Fig. 9 is the Organization Chart that shows according to the described magnetic-resistance random access storage array of the utility model the 3rd embodiment (MRAM) circuit.
Symbol description:
10A, 10B, 40A, 40B, 50,60,70A, 70B, 80A, 80B, 90A, 90B:MRAM unit;
12: electrode; 13,104: insulation course;
14,52A, 52B, 62,64,72A, 72B, 74A, 74B, 82A, 82B, 84A, 84B, 92A, 92B, 94A, 94B: transistor;
16A, 16B, 42A, 42B: data line;
102,106: electromagnetic layer;
108A, 108B: label;
A: zone;
B
n, B1～B4: bit line, pilot wire;
H
t: transverse magnetic field;
H
1, H
0: longitudinal magnetic field;
I
W: program current; I
r: read electric current;
PL, PL, P1～P4: line program;
W
m, W1～W3, W1～W3: character line, alternative line.
Embodiment
Consult Fig. 6, Fig. 6 is the structural drawing that shows according to the described magnetic-resistance random access storage of the utility model embodiment (MRAM) unit.Mram cell 60 comprises fixedly magnetic axis layer 106, free magnetic axis layer 102, and being arranged at insulation course (magnetictunneling junction) 104 between fixing magnetic axis layer 106 and the free magnetic axis layer 102, the magnetic resistance of mram cell 60 (magneto-resistance) is determined by the fixing magnetic axis direction of magnetic axis layer 106 and free magnetic axis layer 102.When free magnetic axis layer 102 when fixedly the magnetic axis direction of magnetic axis layer 106 is same direction, mram cell has low-resistance situation, and when free magnetic axis layer 102 and when fixedly magnetic axis layer 106 is different directions, then mram cell just has and has high-resistance speciality.
Below will introduce design according to described magnetic-resistance random access storage array of the utility model embodiment and peripheral circuit.
First embodiment
Fig. 7 is the Organization Chart that shows according to the described magnetic-resistance random access storage array of the utility model first embodiment (MRAM) circuit.Wherein, W1～W3 and W1～W3 are character line, and P1～P4 is a line program, and B1～B4 is the bit line.
The source electrode of nmos pass transistor 72A and 72B is the free magnetic axis layer 102 that is respectively coupled to reluctance type storage unit 70A and 70B, and its grid is coupled to character line W2 and W2 respectively, and drain is coupled to bit line B3 and B2 respectively.In addition, the drain of nmos pass transistor 74A and 74B is the fixedly magnetic axis layer 106 that is respectively coupled to reluctance type storage unit 70A and 70B, and its grid is coupled to character line W2 and W2 equally respectively, and source electrode is to be coupled to line program P3 and P4 respectively.And line program P2 and P3 are coupled to the fixedly magnetic axis layer 106 of reluctance type storage unit 70A and 70B respectively.
When will be when mram cell 70A writes data, this moment, selected word line W2 be with conducting nmos pass transistor 74A, and provided program current I by line program P3
wAnd with line program P4 ground connection.So program current I
wFlow through the fixedly magnetic axis layer 106 of mram cell 70A, and via nmos pass transistor 74A and line program P4 and flow to earth point.At program current I
wFlow through in the mram cell 70A, the magnetic field of its generation will change the conducting state of mram cell 70A, reach the purpose of the data of writing.What pay special attention to is since this moment program current I
wThe impedance that is run into when flowing through mram cell is far above directly flowing into earth point via fixedly magnetic axis layer 106 and nmos pass transistor 74A, therefore the program current I of the overwhelming majority
wAll by fixedly magnetic axis layer 106 and nmos pass transistor 74A and flow into earth point.
In the time will reading the stored data of mram cell 70A, this moment, selected word line W2 was with conducting nmos pass transistor 72A and nmos pass transistor 74A, was read electric current I and bit line B3 provides
r70A flow to earth point via mram cell, and other circuit ground connection all, and can learn mram cell 70A stored data at present according to the voltage of detecting bit line B3.
Second embodiment
Fig. 8 is the Organization Chart that shows according to the described magnetic-resistance random access storage array of the utility model second embodiment (MRAM) circuit.Wherein, W1～W2 and W1～W2 are alternative line, and B1～B2 and B1～B2 are pilot wire.
The drain of nmos pass transistor 82A and 82B is the free magnetic axis layer 102 that is respectively coupled to reluctance type storage unit 80A and 80B, and its grid all is coupled to alternative line W2, and source electrode is coupled to pilot wire B2 and B1 respectively.In addition, the drain of nmos pass transistor 84A and 84B is the fixedly magnetic axis layer 106 that is respectively coupled to reluctance type storage unit 80A and 80B, and its grid all is coupled to alternative line W2, and source electrode is coupled to pilot wire B2 and B1 equally respectively.And pilot wire B1 and B2 are coupled to the fixedly magnetic axis layer 106 of reluctance type storage unit 80A and 80B respectively.
When will when mram cell 80A write data, choosing alternative line W2 with conducting nmos pass transistor 84A at this moment, and provide program current I by pilot wire B2
wAnd with pilot wire B2 ground connection.So program current I
wFlow through the fixedly magnetic axis layer 106 of mram cell 80A, and via nmos pass transistor 84A and pilot wire B2 and flow to earth point.At program current I
wFlow through in the mram cell 80A, the magnetic field of its generation will change the conducting state of mram cell 80A, reach the purpose of the data of writing.
In the time will reading the stored data of mram cell 80A, choose alternative line W2 with conducting nmos pass transistor 82A this moment, read electric current I and pilot wire B2 provides
rFlow to earth point via mram cell 80A and nmos pass transistor 82A, and can learn mram cell 80A stored data at present according to the voltage of detecting pilot wire B2.
The 3rd embodiment
Fig. 9 is the Organization Chart that shows according to the described magnetic-resistance random access storage array of the utility model the 3rd embodiment (MRAM) circuit.Wherein, W1～W2 and W1～W2 are character line, and P1～P3 is a line program, and B1～B2 is the bit line.
The source electrode of nmos pass transistor 92A and 94A is the fixedly magnetic axis layer that is respectively coupled to reluctance type storage unit 90A and 90B, and its grid is coupled to character line W1 and W1 respectively, and drain is coupled to line program P1 and P2 respectively.In addition, the drain of nmos pass transistor 92B and 94B is the fixedly magnetic axis layer that is respectively coupled to reluctance type storage unit 90A and 90B, and its grid is coupled to character line W1 and W1 equally respectively, and source electrode is to be coupled to line program P2 and P3 respectively.At this, bit line B1 and B2 are the free magnetic axis layers that is coupled to reluctance type storage unit 90A and 90B respectively, and line program P2 is the tie point that is coupled to nmos pass transistor 92B and 94A.
Character line W1 and W1 are respectively in order to the conducting of control nmos pass transistor 92A and 92B and nmos pass transistor 94A and 94B and close.Compared to conventional art as shown in Figure 4, use the line program of lesser amt according to the described magnetic-resistance random access storage array of the utility model the 3rd embodiment circuit, and increased character line.Because need between each line program and the nmos pass transistor just be contacted by contact hole, yet, because contact hole needs bigger area, so cause whole storage array to increase area because of a large amount of contact holes.In the present embodiment, control the storage unit of same delegation (row) by different character lines, therefore less to the influence of whole storage array volume because character line does not need the design of contact hole compared to line program, so effectively reduce the area of storage array.
When will be when mram cell 90B writes data, this moment storage array peripheral circuit selected word line W1, and suspension joint bit line B2, and by line program P2 supply program current I
WBecause this moment, character line W1 was a high levels, so transistor 94A and 94B conducting, so program current I
WThe conducting state of flowing through mram cell 90B and changing mram cell 90B is to reach the purpose of the data of writing.
In the time will reading the stored data of mram cell 90B, peripheral circuit is chosen the character line W1 under this mram cell 90B, and line program P1 and P3 ground connection, provides in bit line B2 at this moment and reads electric current I
rMake its line program P2, P3 of flowing to ground connection via transistor 94A, the 94B of mram cell 90B and conducting, be pursuant to the magnitude of voltage that bit line B2 detected again and learn stored data mram cell 90B this moment.
In addition, according to the utility model first embodiment, second embodiment and the described magnetic-resistance random access storage array of the 3rd embodiment circuit, wherein employed switch is not limited to nmos pass transistor, if it is accurate in order to the position of actuating switch signal to change circuit, then can adopt the PMOS transistor as switch equally, unavailable to limit scope of the present utility model.
In sum, according to magnetic-resistance random access storage array circuit described in the utility model, in first embodiment and second embodiment, can adopt the switch module of reduced size according to the actual needs of circuit, and in the 3rd embodiment, need take quite large-area line program to replace by increasing the character line that needs less area.The disclosed circuit of the various embodiments described above all can effectively reduce the size of present MRAM storage array.
Claims (20)
1. magnetic random access memory circuit is characterized in that comprising:
One reluctance type storage unit has fixedly magnetic axis layer, a free magnetic axis layer, and is arranged at the insulation course between said fixing magnetic axis layer and the free magnetic axis layer, and above-mentioned reluctance type storage unit has one first conducting state;
One first switchgear is coupled to an end of said fixing magnetic axis layer, and has one first control sluice;
One second switch device is coupled to above-mentioned free magnetic axis layer, and has one second control sluice;
One bit line is coupled to above-mentioned second switch device, provides when being used to read action and reads electric current;
One first line program is coupled to the other end of said fixing magnetic axis layer, and program current is provided when being used to carry out the programming action;
One second line program is coupled to above-mentioned first switchgear; And
One character line is coupled to above-mentioned first control sluice and second control sluice, in order to provide an activation signal with above-mentioned first switchgear of conducting and second switch device.
2. magnetic random access memory circuit according to claim 1, it is characterized in that: when carrying out the programming action, above-mentioned second line program is a ground connection, and above-mentioned first switchgear of above-mentioned enable signal conducting and second switch device, make above-mentioned program current via said fixing magnetic axis layer and second switch device and flow to above-mentioned second line program, and the magnetic field that above-mentioned program current is produced when flowing through the said fixing magnetic axis layer changes the magnetic axis direction of above-mentioned free magnetic axis layer, makes the conducting state of above-mentioned reluctance type storage unit change into one second conducting state by above-mentioned first conducting state.
3. magnetic random access memory circuit according to claim 1, it is characterized in that: when action is read in execution, above-mentioned first line program and second line program are ground connection, and above-mentioned first switchgear of above-mentioned enable signal conducting and second switch device, make the above-mentioned electric current that reads flow to above-mentioned first line program and second line program, and read the data that is stored in above-mentioned reluctance type storage unit according to the voltage level of above-mentioned bit line via above-mentioned second switch device, reluctance type storage unit and first switchgear.
4. magnetic random access memory circuit according to claim 1 is characterized in that: above-mentioned program current is hundred times of twices to two that read electric current.
5. magnetic random access memory circuit according to claim 1 is characterized in that: the size of above-mentioned first switchgear is greater than above-mentioned second switch device size.
6. magnetic random access memory circuit according to claim 1 is characterized in that: above-mentioned first conducting state is a high impedance status.
7. magnetic random access memory circuit according to claim 6 is characterized in that: above-mentioned second conducting state is a low impedance state.
8. magnetic random access memory circuit according to claim 1 is characterized in that: above-mentioned first switchgear and second switch device are transistor.
9. magnetic random access memory circuit according to claim 8 is characterized in that: above-mentioned first switchgear and second switch device are nmos pass transistor.
10. magnetic random access memory circuit according to claim 8 is characterized in that: above-mentioned first switchgear and second switch device are the PMOS transistor.
11. a magnetic random access memory circuit comprises:
One reluctance type storage unit has fixedly magnetic axis layer, a free magnetic axis layer, and is arranged at the insulation course between said fixing magnetic axis layer and the free magnetic axis layer, and above-mentioned reluctance type storage unit has one first conducting state;
One first pilot wire is coupled to an end of said fixing magnetic axis layer, provides when being used to read action to read electric current and program current is provided when programming;
One first switchgear is coupled to above-mentioned free magnetic axis layer, and has one first control sluice;
One second switch device is coupled to the other end of said fixing magnetic axis layer, and has one second control sluice;
One first alternative line is coupled to above-mentioned first control sluice, chooses signal in order to provide one first;
One second alternative line is coupled to above-mentioned second control sluice, chooses signal in order to provide one second; And
One second pilot wire is coupled to above-mentioned first switchgear and second switch device.
12. magnetic random access memory circuit according to claim 11, it is characterized in that: when carrying out the programming action, above-mentioned second pilot wire is a ground connection, and above-mentioned second chooses the above-mentioned second switch device of signal conduction, make above-mentioned program current via said fixing magnetic axis layer and second switch device and flow to above-mentioned second pilot wire, and the magnetic field that above-mentioned program current is produced when flowing through the said fixing magnetic axis layer changes the magnetic axis direction of above-mentioned free magnetic axis layer, makes the conducting state of above-mentioned reluctance type storage unit change into one second conducting state by above-mentioned first conducting state.
13. magnetic random access memory circuit according to claim 11, it is characterized in that: when action is read in execution, above-mentioned second pilot wire is a ground connection, and above-mentioned first chooses above-mentioned first switchgear of signal conduction, make the above-mentioned electric current that reads via above-mentioned reluctance type storage unit and first switchgear and flow to above-mentioned second pilot wire, and read the data that is stored in above-mentioned reluctance type storage unit according to the voltage level of above-mentioned first pilot wire.
14. magnetic random access memory circuit according to claim 11 is characterized in that: above-mentioned program current is hundred times of twices to two that read electric current.
15. magnetic random access memory circuit according to claim 11 is characterized in that: the size of above-mentioned first switchgear is less than above-mentioned second switch device size.
16. magnetic random access memory circuit according to claim 11 is characterized in that: above-mentioned first conducting state is a high impedance status.
17. magnetic random access memory circuit according to claim 16 is characterized in that: above-mentioned second conducting state is a low impedance state.
18. magnetic random access memory circuit according to claim 11 is characterized in that: above-mentioned first switchgear and second switch device are transistor.
19. a magnetic random access memory circuit comprises:
One first reluctance type storage unit has one first fixedly magnetic axis layer, one first free magnetic axis layer, and is arranged at above-mentioned first fixing first insulation course between magnetic axis layer and first free magnetic axis layer;
One first bit line is coupled to above-mentioned first free magnetic axis layer, provides when being used to read action and reads electric current;
One first switchgear is coupled to the above-mentioned first fixing end of magnetic axis layer, and has one first control sluice;
One second switch device is coupled to the above-mentioned first fixing other end of magnetic axis layer, and has one second control sluice;
One first line program is coupled to above-mentioned first switchgear, and program current is provided when being used to carry out the programming action;
One second reluctance type storage unit has one second fixedly magnetic axis layer, one second free magnetic axis layer, and is arranged at above-mentioned second fixing second insulation course between magnetic axis layer and second free magnetic axis layer;
One second bit line is coupled to above-mentioned second free magnetic axis layer, provides when being used to read action and reads electric current;
One the 3rd switchgear is coupled to the above-mentioned second fixing end of magnetic axis layer, and has one the 3rd control sluice;
One the 4th switchgear is coupled to the above-mentioned second fixing other end of magnetic axis layer, and has one the 4th control sluice;
One second line program is coupled to above-mentioned second switch device and the 3rd switchgear;
One the 3rd line program is coupled to above-mentioned the 4th switchgear;
One first character line is coupled to above-mentioned first control sluice and second control sluice, in order to provide an activation signal with above-mentioned first switchgear of conducting and second switch device; And
One second character line is coupled to above-mentioned the 3rd control sluice and the 4th control sluice, in order to provide above-mentioned enable signal with above-mentioned the 3rd switchgear of conducting and the 4th switchgear.
20. magnetic random access memory circuit according to claim 19 is characterized in that: above-mentioned first switchgear, second switch device, the 3rd switchgear and the 4th switchgear are transistor.
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| CN 200420049602 CN2710107Y (en) | 2004-04-22 | 2004-04-22 | Magnetoresistive random access store circuit |
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| CN 200420049602 CN2710107Y (en) | 2004-04-22 | 2004-04-22 | Magnetoresistive random access store circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102568579A (en) * | 2010-12-09 | 2012-07-11 | 英飞凌科技股份有限公司 | Nonvolatile memory with enhanced efficiency to address asymmetric NVM cells |
-
2004
- 2004-04-22 CN CN 200420049602 patent/CN2710107Y/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102568579A (en) * | 2010-12-09 | 2012-07-11 | 英飞凌科技股份有限公司 | Nonvolatile memory with enhanced efficiency to address asymmetric NVM cells |
| CN102568579B (en) * | 2010-12-09 | 2016-04-20 | 英飞凌科技股份有限公司 | The asymmetric NVM unit in address is had to the nonvolatile memory of the efficiency of enhancing |
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