HK1045894B - 電腦元件之間有一經改良界面的方法及儀器 - Google Patents

電腦元件之間有一經改良界面的方法及儀器

Info

Publication number
HK1045894B
HK1045894B HK02107265.1A HK02107265A HK1045894B HK 1045894 B HK1045894 B HK 1045894B HK 02107265 A HK02107265 A HK 02107265A HK 1045894 B HK1045894 B HK 1045894B
Authority
HK
Hong Kong
Prior art keywords
computer components
improved interface
interface
improved
computer
Prior art date
Application number
HK02107265.1A
Other languages
English (en)
Other versions
HK1045894A1 (en
Inventor
Ajanovic Jasmin
j harriman David
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of HK1045894A1 publication Critical patent/HK1045894A1/xx
Publication of HK1045894B publication Critical patent/HK1045894B/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Information Transfer Systems (AREA)
  • Debugging And Monitoring (AREA)
  • Bus Control (AREA)
HK02107265.1A 1999-10-26 2002-10-03 電腦元件之間有一經改良界面的方法及儀器 HK1045894B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/428,134 US20030110317A1 (en) 1998-11-03 1999-10-26 Method and apparatus for an improved interface between a memory control hub and an input/output control hub
PCT/US2000/029275 WO2001031460A1 (en) 1999-10-26 2000-10-23 Method and apparatus for an improved interface between computer components

Publications (2)

Publication Number Publication Date
HK1045894A1 HK1045894A1 (en) 2002-12-13
HK1045894B true HK1045894B (zh) 2005-03-18

Family

ID=23697679

Family Applications (1)

Application Number Title Priority Date Filing Date
HK02107265.1A HK1045894B (zh) 1999-10-26 2002-10-03 電腦元件之間有一經改良界面的方法及儀器

Country Status (9)

Country Link
US (1) US20030110317A1 (zh)
KR (1) KR100432701B1 (zh)
CN (1) CN100338593C (zh)
AU (1) AU1341201A (zh)
DE (1) DE10085140T1 (zh)
GB (1) GB2372359B (zh)
HK (1) HK1045894B (zh)
TW (1) TW514787B (zh)
WO (1) WO2001031460A1 (zh)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6516375B1 (en) 1999-11-03 2003-02-04 Intel Corporation Peripheral component interconnect (PCI) configuration emulation for hub interface
US7039047B1 (en) 1999-11-03 2006-05-02 Intel Corporation Virtual wire signaling
US7099318B2 (en) 2001-12-28 2006-08-29 Intel Corporation Communicating message request transaction types between agents in a computer system using multiple message groups
CN100362504C (zh) * 2005-01-21 2008-01-16 瑞传科技股份有限公司 用于工业电脑的单板电脑机板
US9946683B2 (en) 2014-12-24 2018-04-17 Intel Corporation Reducing precision timing measurement uncertainty
KR20170025868A (ko) * 2015-08-31 2017-03-08 에스케이하이닉스 주식회사 고속 통신을 위한 전송 장치, 이를 포함하는 인터페이스 회로 및 시스템

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US5191649A (en) * 1990-12-21 1993-03-02 Intel Corporation Multiprocessor computer system with data bus and ordered and out-of-order split data transactions
JP3411300B2 (ja) * 1992-02-18 2003-05-26 株式会社日立製作所 情報処理装置
US5553310A (en) * 1992-10-02 1996-09-03 Compaq Computer Corporation Split transactions and pipelined arbitration of microprocessors in multiprocessing computer systems
US5590292A (en) * 1992-12-08 1996-12-31 Compaq Computer Corporation Scalable tree structured high speed input/output subsystem architecture
US5687388A (en) * 1992-12-08 1997-11-11 Compaq Computer Corporation Scalable tree structured high speed input/output subsystem architecture
US5469435A (en) * 1994-01-25 1995-11-21 Apple Computer, Inc. Bus deadlock avoidance during master split-transactions
US5533204A (en) * 1994-04-18 1996-07-02 Compaq Computer Corporation Split transaction protocol for the peripheral component interconnect bus
US5546546A (en) * 1994-05-20 1996-08-13 Intel Corporation Method and apparatus for maintaining transaction ordering and arbitrating in a bus bridge
US5742847A (en) * 1994-10-31 1998-04-21 Intel Corporation M&A for dynamically generating and maintaining frame based polling schedules for polling isochronous and asynchronous functions that guaranty latencies and bandwidths to the isochronous functions
US5621897A (en) * 1995-04-13 1997-04-15 International Business Machines Corporation Method and apparatus for arbitrating for a bus to enable split transaction bus protocols
US5933612A (en) * 1995-05-02 1999-08-03 Apple Computer, Inc. Deadlock avoidance in a split-bus computer system
JPH0954746A (ja) * 1995-08-11 1997-02-25 Toshiba Corp コンピュータシステム
US5761444A (en) * 1995-09-05 1998-06-02 Intel Corporation Method and apparatus for dynamically deferring transactions
US5754807A (en) * 1995-11-20 1998-05-19 Advanced Micro Devices, Inc. Computer system including a multimedia bus which utilizes a separate local expansion bus for addressing and control cycles
US5911052A (en) * 1996-07-01 1999-06-08 Sun Microsystems, Inc. Split transaction snooping bus protocol
US5729760A (en) * 1996-06-21 1998-03-17 Intel Corporation System for providing first type access to register if processor in first mode and second type access to register if processor not in first mode
US5870567A (en) * 1996-12-31 1999-02-09 Compaq Computer Corporation Delayed transaction protocol for computer system bus
US5832243A (en) * 1996-12-31 1998-11-03 Compaq Computer Corporation Computer system implementing a stop clock acknowledge special cycle
US5918025A (en) * 1996-12-31 1999-06-29 Intel Corporation Method and apparatus for converting a five wire arbitration/buffer management protocol into a two wire protocol
US5930485A (en) * 1997-01-07 1999-07-27 Apple Computer, Inc. Deadlock avoidance in a computer system having unordered slaves
US5991824A (en) * 1997-02-06 1999-11-23 Silicon Graphics, Inc. Method and system for simultaneous high bandwidth input output
US5909594A (en) * 1997-02-24 1999-06-01 Silicon Graphics, Inc. System for communications where first priority data transfer is not disturbed by second priority data transfer and where allocated bandwidth is removed when process terminates abnormally
US6088370A (en) * 1997-09-22 2000-07-11 Intel Corporation Fast 16 bit, split transaction I/O bus
US6195722B1 (en) * 1998-01-26 2001-02-27 Intel Corporation Method and apparatus for deferring transactions on a host bus having a third party agent
US6101566A (en) * 1998-03-13 2000-08-08 Compaq Computer Corporation Computer system with bridge logic that includes an internal modular expansion bus and a common target interface for internal target devices
US6308255B1 (en) * 1998-05-26 2001-10-23 Advanced Micro Devices, Inc. Symmetrical multiprocessing bus and chipset used for coprocessor support allowing non-native code to run in a system
US6148357A (en) * 1998-06-17 2000-11-14 Advanced Micro Devices, Inc. Integrated CPU and memory controller utilizing a communication link having isochronous and asynchronous priority modes
US6175889B1 (en) * 1998-10-21 2001-01-16 Compaq Computer Corporation Apparatus, method and system for a computer CPU and memory to high speed peripheral interconnect bridge having a plurality of physical buses with a single logical bus number
US6145039A (en) * 1998-11-03 2000-11-07 Intel Corporation Method and apparatus for an improved interface between computer components
US6567876B1 (en) * 1999-12-03 2003-05-20 Hewlett-Packard Development Company, L.P. Docking PCI to PCI bridge using IEEE 1394 link

Also Published As

Publication number Publication date
HK1045894A1 (en) 2002-12-13
AU1341201A (en) 2001-05-08
GB2372359B (en) 2004-08-25
US20030110317A1 (en) 2003-06-12
DE10085140T1 (de) 2002-11-07
CN100338593C (zh) 2007-09-19
WO2001031460A1 (en) 2001-05-03
TW514787B (en) 2002-12-21
KR20020069007A (ko) 2002-08-28
KR100432701B1 (ko) 2004-05-24
GB0211909D0 (en) 2002-07-03
WO2001031460A9 (en) 2002-07-04
GB2372359A (en) 2002-08-21
CN1415094A (zh) 2003-04-30

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Legal Events

Date Code Title Description
PC Patent ceased (i.e. patent has lapsed due to the failure to pay the renewal fee)

Effective date: 20131023